JPH0449290B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is directed to IIL (Integrated Injection Logic).
This invention relates to an integrated circuit interface circuit in which circuits and linear circuits coexist.

[Prior art]

IIL gates are digital elements that can coexist on the same chip as linear circuits. In recent years, especially IC
With the advancement of process miniaturization technology, large-scale
IC development is being carried out one after another. For this reason, IIL circuits that can coexist with linear circuits are very often used.

For example, in the color signal circuit of a VTR, the color signal processing circuit and the color synchronization circuit that performs digital processing are integrated into a single chip, resulting in significant cost reductions.

However, in ICs where linear circuits and IIL circuits coexist, waveform distortion and crosstalk between signals occur in the interface circuit from the IIL circuit to the linear circuit, often causing problems.
For example, APC (Auto
phase control) circuit, etc.
FIG. 1 is an example of a conventional phase detector. R1～
R9 is a resistor, V ₁ to _{V 3} are voltage sources, Q1, Q3, Q
4 is a PNP transistor, Q2, Q5 to Q14 are
NPN transistors C1 and C2 are capacitors.
I ² L gate G11 with two transistors Q1 and Q2
and invert the output of input terminal 1,
I ² Outputs from the L section output terminal 2 to the base of the transistor Q11. A burst signal is input from the input terminal 3, and switching is performed by the burst signal input to the differential pair of transistors Q9 and Q10.
From input terminal 4, a signal synchronized with the burst signal and 90° out of phase is sent to transistor Q, which constitutes a multiplier.
6, input to the base of Q7. transistor Q
5 to Q8 are turned on and off according to the input from input terminal 4, and are multiplied by the switched currents of transistors Q9 and Q10. The multiplied output current is from IC pin 6 to external resistor R9 and capacitor C.
1 and C2 is output to the detection filter 7.
Resistors R1 and R2 (resistance value of R1=R2) and transistors Q3 and Q4 constitute a current mirror circuit, and an equal current always flows through the collectors of transistors Q3 and Q4. Therefore, input terminal 3,
The base of transistor Q3 according to the phase difference of 4,
From the collector to transistor Q5 and transistor Q
The current flowing through the collector of the transistor Q4 changes, and accordingly, a current flows out or flows into the detection filter 7 from the collector side of the transistor Q4. As a result, the DC voltage at the output end of the detection filter 7 rises or falls, and a control voltage is output.

The transistor Q11 and the resistor R3 are constant current sources, and the phase detection section operates only when the transistor Q11 is turned on.

Resistors R5-R7, transistors Q12-Q14
is a bias section, and diode-connected transistors Q12 and Q13 are transistors Q13 and Q11.
etc., and creates a reference potential for the base of transistor Q11.

When the transistor Q11 turns on, the output terminal 1 of the IIL gate G1 goes low and the transistor Q2 of the gate G1 turns off, and the transistor Q11 turns on.
The base potential of transistor Q11 (V _Q11B ) is
It is the value obtained by subtracting the voltage drop caused by the resistor R4 (R4×Io/h _FEQ11 ) from the emitter potential of No. 14 (V _Q14E ).

When the transistor Q11 turns off, the output terminal 1 of the IIL gate G1 becomes high and the transistor Q2 of the gate G1 turns on, and the transistor Q11 turns off.
The base potential of transistor Q2 becomes the emitter potential (OV) of transistor Q2.

Problems with the above circuit are shown below. The phase detector is connected to the transistor Q11 by the output of the output terminal 2.
turns on and off and works. When transistor Q11 is turned off, current flows from the reference potential point of transistor Q14 to the collector of transistor Q2 via resistor R4. However, the value of the current flowing at this time cannot take a large value due to the limit of the drawing ability of the collector of the transistor Q2 of the IIL gate, and is limited. Furthermore, if the value of resistor R4 is increased to reduce the current, variations will occur in the current Io flowing through resistor R3 when transistor Q11 is turned on.
This also causes variations in detection sensitivity. The reason for the variation in the current Io is that the current amplification factor (h _FE ) of the transistor used in the integrated circuit is low and the variation is large (usually varies by about 4 times), and the absolute value variation of the resistor R4 is large (± 30%), the base and emitter potentials of transistor Q11 vary. R of the variation of this current Io
As the current Io flowing through the circuit 3 varies, the detection sensitivity also varies. A specific example will be explained using FIG.

Originally, if the emitter potential of the transistor Q11 was constant, the current _t0 should be constant, but the resistance R
4, the emitter potential of the transistor Q11 varies, and as a result, the current _I0 varies. For example, if the base potential of the transistor Q11 is 1V, the emitter potential is 0.3V, and the current sucked by the transistor Q2 of the gate G1 is 0.2mA, the resistance R4 is 5KΩ. When _hFE is 100 and resistance R ₃ =300Ω, current Io flows at 1mA. h If _FE varies from 50 to 200, the current flowing through resistor _R4 will be from 20 μA to 5 μA, and the resistor
The voltage drop across _R4 will be 0.1V to 25mV. base·
If the emitter voltage is 0.7V, transistor Q
11 The emitter potential is 0.25V to 0.325V, and the current
The variation in Io is -16.7% to +8.3%, which is 25%.
The degree will vary. Current flowing through resistor R3
As Io varies, the detection sensitivity also varies. Furthermore, when the transistor Q11 is turned on in response to the output 2, there is a drawback that the output waveform of the terminal 1 is rounded due to parasitic capacitance between the base and collector of the transistor Q2 and between the base and collector of the transistor Q11. Since the parasitic capacitance is charged via the resistor R4, the larger the value of the resistor R4, the larger the time constant, and the larger the waveform distortion and phase delay.
Due to these waveform distortions and phase delays, the control signal output in step 2 becomes error-prone, and the system becomes unstable and does not operate correctly.

In general, the yield of integrated circuits decreases in proportion to the chip area, so in order to improve the yield, circuit blocks that can be used in common are shared as much as possible to reduce the chip area. In particular, reference potential points such as bias circuits are often shared. The fact that the emitter potential of transistor Q14 in FIG. 1 is also used as the reference potential for the IIL gate of other circuit blocks and the interface part of the linear circuit is extremely effective for reducing the number of elements and simplifying the circuit, and is also a general It is something. However, in this case, crosstalk between each circuit block becomes a problem. That is, when a current source such as the one composed of the transistor Q11 and the resistor R3 is turned on and when it is turned off, the transistor Q14
The value of the current flowing from the emitter of the two is greatly different. Therefore, the base-emitter voltage V _BE of the transistor Q14 is different, and the emitter potential of the transistor Q14 is no longer a constant potential. That is, by switching various current source circuits, transistor Q
Since the emitter potential of 14 changes, crosstalk occurs between each control signal.

[Object of the invention] The present invention is an interface circuit between an IIL circuit and a linear circuit, in which the output signal of the IIL gate is distorted.
The present invention provides an interface circuit that has no crosstalk and propagates to a linear circuit without being affected by temperature characteristics.

[Summary of the invention]

The present invention allows level shifting with low impedance when the diode is forward biased, and high impedance when reverse biased.
It is used to interface between the IIL gate and the linear circuit, and the switching is performed by the IIL gate output. In other words, when the output transistor of the IIL gate is off (high), the circuit block connected to the anode of the diode is operated by the reference potential level-shifted from the anode side of the diode connected to the constant current supply source. .
When the output transistor of the IIL gate is on (becomes low), the current from the constant current supply source flows to the reference point, the potential of the anode of the diode becomes the reference potential, and all the circuit blocks connected to the anode of the diode do not operate. It disappears.

In this way, normally this diode can shift the level between the cathode and anode by the same amount as the base-emitter voltage drop (V _BE ) of the emitter follower transistor for the reference voltage.
The number of diodes in the base of the emitter follower transistor can be reduced by one. In other words, in the conventional example shown in FIG. 1, the base of the emitter follower transistor Q14 is connected to the emitter follower transistor Q14 and the current source transistor Q1.
Two diodes Q12 and Q13 are connected in order to correct the temperature characteristics and the variation in V _be of 1, but in the present invention, only one diode is required.

The fact that only one diode is required is advantageous when operating at a low power supply voltage. Further, at this time, since the increase in impedance due to this diode can be made to be less than several hundred ohms, a large number of constant current sources can be driven at once from the anode portion of this diode.

For example, assume that the current of the constant current supply source (transistor Q22 in FIG. 2) is 0.2 mA, and that five constant current sources (transistors Q27 and Q28) are provided, each having a current of 1 mA. As aforementioned
h If _FE varies from 50 to 200, the total value of the base current of the five constant current sources will vary from 0.1 to 0.025 mA. As a result, the diode (transistor Q2
6) side, 0.1 to 0.17 mA will flow, and the variation in the voltage between the anode and cathode of the diode due to the variation in this current will be about 18 mA. The center voltage of the emitter of the constant current source transistor is
If it is 0.3V, the emitter potential will vary from 0.291 to 0.309V (variation of approximately ±3%). Therefore, even if five constant current sources are driven at once, the variation is smaller than in the conventional example in which one constant current source is driven.

Also, if the bias current of this diode is bypassed on the anode side, this diode becomes reverse biased, the impedance becomes extremely high (usually several MΩ or more), and no current flows from the emitter follower. For this reason, the IIL gate, which is a switch for bypassing, only needs to pass the bypass current, so a normal-sized IIL gate is sufficient and it is possible to switch the constant current source extremely efficiently.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. In Figure 2, Q24, Q21, Q26, Q
29 is a transistor whose base and collector are connected in common and operates as a diode; Q25 is a transistor forming an emitter follower; Q2
2 and Q23 are transistors for applying bias current to transistors Q26 and Q29, and together with transistor Q21, they constitute a current mirror circuit. Q27, Q28, Q30, and Q31 are transistors that each constitute a constant current source, and Q32 and Q
33 constitutes IIL gate G2, Q34 and Q35 constitute IIL gate G3, and R1
1 and R12 are resistors for applying a bias to the emitter follower transistor Q25, R13 is a resistor for applying a bias current to the emitter follower transistor Q25, R14, R15,
R16 and R17 are the current value I ₁ of the constant current source, respectively
Resistors for providing I ₂ , I ₃ , and I ₄ , V ₅ is the voltage source of the linear circuit, and V ₆ is the voltage source of the IIL gate.

When a high (0.7V) signal is input to the control signal input terminal 8, the transistor Q of the IIL gate G2
33 is turned on, and the base-collector connection portion of transistor Q26 becomes approximately 0V. Further, the constant current sources of transistors Q27 and Q28 are also turned off, and the circuit blocks connected to the collectors of transistors Q27 and Q28 become inoperable. At this time transistor Q
Since transistor Q22 is a constant current circuit along with transistors Q23 and Q21, the current flowing from the collector of transistor Q22 is a current that can be sufficiently absorbed by a normal IIL gate if the collector current of transistor Q22 is set from about 100 μA to several tens of μA. This allows transistors Q27 and Q28 to be quickly turned off. Note that the transistor Q26 is reverse biased and has a high impedance, so that almost no current flows, and the current consumption when the constant current source is off is only the bypass current of the transistor Q22, which is extremely small.

When the signal at the control signal input terminal 8 is Low (=0V), the transistor Q33 of the IIL gate G2 is turned off. Therefore, transistor Q26 is forward biased, and the base-collector potential of transistor Q26 becomes a potential based on the base of transistor Q25, turning on transistors Q27 and Q28. At this time, variations in the currents I ₁ and I ₂ flowing through the collectors of the transistors Q27 and Q28 are almost negligible, as shown below. The temperature characteristic of V _BE of transistor Q25 is that of diode Q24.
With the temperature characteristics of V _BE , transistors Q27 and Q2
The temperature characteristics of V _BE of 8 are corrected by the temperature characteristics of V _BE of diode Q26, so the emitter voltages of transistors Q27 and Q28 have almost no temperature characteristics, so the currents I ₁ ,
There is almost no variation in I ₂ .

Further, in the transient response from off to on of the transistors Q27 and Q28, no waveform distortion or phase delay occurs because there is no resistance between the collector of the constant current source transistor Q22 and the bases of the transistors Q27 and Q28. Accordingly, no variation occurs in the operating currents I ₁ and I ₂ .

Transistors Q27, Q28 and transistor Q
The signal crosstalk between the circuit blocks 30 and Q31 is caused by the transistor Q26 and the transistor Q2.
When 9 is reverse biased, the impedance is large (several MΩ or more) and the emitter resistance re of transistor Q25 (26Ω at I ₀ = 1 mA, 130 Ω at I ₀ = 0.2 mA) is small, so crosstalk occurs at the emitter of transistor Q25. is divided by the resistance and can be almost ignored.

Also, transistors Q21 and Q22 or Q23
The current mirror circuit consisting of transistor Q
Since it is provided on the collector side of transistors Q25, Q26, and Q29, even if the emitter current of transistor Q25 changes due to turning on or off of one of transistors Q26 and Q29,
Even if a change occurs in the base-emitter voltage Vbe of transistor Q25, a change similar to this change (with the same direction of change and a magnitude corresponding to the current ratio of the current mirror circuit) will occur in the other transistor of transistors Q26 and Q29. occurs in the base-emitter voltage Vbe. That is, for example, even if the base-emitter voltage Vbe of transistor Q25 increases due to transistor Q29 being turned off, and its emitter potential decreases, the base-emitter voltage of transistor Q26 remains unchanged.
As Vbe increases, its base potential changes little. Therefore, the crosstalk generated in transistor Q26 by turning on and off transistor Q29 can be almost ignored. Similarly,
The crosstalk generated in transistor Q29 by turning on and off transistor Q26 can also be almost ignored.

Also, in Figure 2, the control signal of the IIL gate output is 2.
Although the circuit blocks have been described in several locations, it is needless to say that the number of circuit blocks is not limited to two locations, and there is no problem with one or more locations.

Furthermore, up to this point, an NPN transistor has been used as the constant current source, but it goes without saying that this can be easily changed to a circuit using PNP.

FIG. 3 shows another example of an embodiment in which a PNP transistor is used in the current limiting circuit of the interface circuit of the present invention. In this embodiment, transistor Q5
The NPN transistor No. 4 has a constant potential at its base, a power supply at its collector, and a resistor R32 at its emitter, making it a constant current source. By making the current flowing through resistor R32 larger than the current flowing from each of transistors Q56, Q57, and Q58, fluctuations in the emitter potential of transistor Q54 are eliminated, and when each of the constant current sources of transistors Q61 to Q63 is turned on, each This eliminates fluctuations in the base potential of , and eliminates variations in the flowing currents I ₈ to _{I 10} .

〔Effect of the invention〕

As stated above, the present invention can be applied to linear circuits and IIL circuits.
By using it in an interface circuit with a gate circuit, the output waveform from the IIL gate can be propagated without distortion, and the constant current source can be turned on and off without being affected by crosstalk or temperature characteristics of other gate outputs.
This makes it possible to turn off the power extremely economically and easily, resulting in significant performance and cost benefits.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an example of a conventional interface, Fig. 2 is a circuit diagram showing an embodiment of an interface circuit according to the present invention, and Fig. 3 is a circuit diagram showing an embodiment of an interface circuit according to the present invention. FIG. 3 is a circuit diagram of another example used. 8, 9...Limit signal input terminal, G2, G3...
IIL gate, Q26, Q29...Diode-connected transistor, Q25, Q27, Q28, Q
30, Q31...Transistor.

Claims (1)

[Claims] 1. It has an emitter connected to a first reference potential via a first resistor, and a base and a collector that are conductively connected to each other, and the base-collector connection part is connected to a second reference potential. a first transistor Q24 connected to the first transistor Q24; a base connected to the base-collector connection of the first transistor;
a second emitter connected to a reference potential of
a transistor Q25, current mirror circuits Q21 and Q22 provided at the collector of the second transistor, an emitter connected to the emitter of the second transistor, and a base and a collector conductively connected to each other, - A third transistor Q26 whose collector connection part is connected to the output of the current mirror circuit, an IIL gate G2 whose output end is connected to the base-collector connection part of the third transistor, and the base of the third transistor.・The base connected to the collector connection part and the first
Each has an emitter connected to a reference potential of IIL
An interface circuit comprising: a current source circuit comprising one or more transistors Q27 and Q28 controlled simultaneously by gates;