JPH0448626A - Dry etching apparatus - Google Patents
Dry etching apparatusInfo
- Publication number
- JPH0448626A JPH0448626A JP15791190A JP15791190A JPH0448626A JP H0448626 A JPH0448626 A JP H0448626A JP 15791190 A JP15791190 A JP 15791190A JP 15791190 A JP15791190 A JP 15791190A JP H0448626 A JPH0448626 A JP H0448626A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- chamber
- cooling
- processing
- semiconductor wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001312 dry etching Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 238000001816 cooling Methods 0.000 claims abstract description 24
- 235000012431 wafers Nutrition 0.000 claims description 43
- 230000005684 electric field Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 238000010943 off-gassing Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 5
- 241000257465 Echinoidea Species 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 244000228957 Ferula foetida Species 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000706 filtrate Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- ing And Chemical Polishing (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
乙の発明は、半導体ウェハプロセスで、半導体ウェハに
ドライ処理を施すドライエツチング装置に関するもので
ある。[Detailed Description of the Invention] [Industrial Application Field] The invention of Part B relates to a dry etching apparatus for performing dry processing on a semiconductor wafer in a semiconductor wafer process.
従来のこの種のドライエツチング装置の概略構成図を第
2図に示す。この図で、1は処理室で、気密が保たれる
ように構成されており、その底面に設けた排気路2に真
空ポンプ(図示せず)を接続して室内を真空引きする。FIG. 2 shows a schematic diagram of a conventional dry etching apparatus of this type. In this figure, reference numeral 1 denotes a processing chamber, which is configured to be airtight, and a vacuum pump (not shown) is connected to an exhaust path 2 provided at the bottom of the chamber to evacuate the chamber.
3は前記処理室1内に配置され、半導体ウェハ4を載置
保持するステジてあり、半導体ウェハ4を冷却させる冷
却機5が接続されている。また、処理室1の上部には処
理ガスを室内に導入するためのガス導入#56が設けら
れている。7は前記処理室1の上部に石英窓8を介して
設けられている導液管で、マイクロ波発生装置9が接続
され、処理室1内へマイクロ波を印加する。10は前記
処理室1の外部に設けられたコイルであり、ステージ3
に載置された半導体ウェハ4の面に垂直方向に磁界が発
生するように設計されている。11は予備室で、処理室
1に真空開閉手段12を介し隣接している。13はウェ
ハバッファ室で、予備室11に真空開閉手段14を介し
隣接し、室内には半導体ウェハ4を収納するカセット1
5が収容されている。16はウェハ搬送手段で、ウェハ
バッファ室13から処理室1までの間の半導体ウェハ4
の搬送を行う。A stage 3 is arranged in the processing chamber 1 and holds a semiconductor wafer 4 thereon, and a cooler 5 for cooling the semiconductor wafer 4 is connected thereto. Furthermore, a gas introduction #56 is provided at the upper part of the processing chamber 1 for introducing processing gas into the chamber. Reference numeral 7 denotes a liquid guiding pipe provided in the upper part of the processing chamber 1 through a quartz window 8, to which a microwave generator 9 is connected and applies microwaves to the inside of the processing chamber 1. 10 is a coil provided outside the processing chamber 1, and the stage 3
The magnetic field is designed to be generated in a direction perpendicular to the surface of the semiconductor wafer 4 placed on the substrate. A preliminary chamber 11 is adjacent to the processing chamber 1 via a vacuum opening/closing means 12. Reference numeral 13 denotes a wafer buffer chamber, which is adjacent to the preparatory chamber 11 via a vacuum opening/closing means 14, in which a cassette 1 for storing semiconductor wafers 4 is placed.
5 is accommodated. Reference numeral 16 denotes a wafer transport means for transporting the semiconductor wafer 4 between the wafer buffer chamber 13 and the processing chamber 1.
transportation.
次に、動作について説明する。Next, the operation will be explained.
半導体ウェハ4が収納されたカセット15がウェハバッ
ファ室13に収容され、排気が完了すると、真空開閉手
段12と真空開閉手段14が開き、半導体ウェハ4はウ
ェハバッファ室13より処理室1ヘウエへ搬送手段16
により搬送され、真空開閉手段12が閉じられると一連
の処理シーケンスが開始される。The cassette 15 containing the semiconductor wafer 4 is stored in the wafer buffer chamber 13, and when the evacuation is completed, the vacuum opening/closing means 12 and the vacuum opening/closing means 14 are opened, and the semiconductor wafer 4 is transferred from the wafer buffer chamber 13 to the processing chamber 1. Means 16
When the vacuum opening/closing means 12 is closed, a series of processing sequences are started.
まず、所期の真空排気を行い、同時に半導体ウェハ4を
冷却する。それぞれ所期の値に達すると、ガス導入路6
より所定のガスを導入し、所定の圧力に達すると磁場と
マイクロ波を印加し、プラズマを発生させエツチング処
理を行う。前述の真空排気とウェハ冷却は、この種のE
CR(ElectronCyclotron Etc
hing )原理を利用した装置においてはエツチング
処理上重要なファクタであり、真空排気は処理ガスを導
入する前に処理室1内の不純物を取り除く目的であり、
lXl0−’〜1O−6Torr台くらいまで排気する
。また、ウェハ冷却は、第3図(a)に示すようなマス
ク17の寸法通りに被エツチング[18をエツチングす
るために必要であり、冷却を行わなければ、第3図(b
)に示すような形状になってしまう。冷却温度は使用す
る処理ガスにより異なるが、通常O℃〜−数十℃くらい
である。しかし、第2図の構成のように、半導体ウェハ
4を常温より冷却する場合、例えば30℃くらいに冷却
する場合に1分程度の時間を要する。また、冷却するた
めに半導体ウニへ4上に付着している水分等のアラ1−
ガスがしずらくなり、所期真空度のI X 10 ’−
’〜10−’Torrまでに真空排気するまでにも数分
の時間を要するという不具合があった。First, a desired vacuum evacuation is performed, and at the same time, the semiconductor wafer 4 is cooled. When the respective desired values are reached, the gas introduction path 6
A predetermined gas is introduced, and when a predetermined pressure is reached, a magnetic field and microwaves are applied to generate plasma and perform etching processing. The vacuum evacuation and wafer cooling described above are
CR (Electron Cyclotron etc.
hing) principle is an important factor in etching processing, and the purpose of vacuum evacuation is to remove impurities in the processing chamber 1 before introducing the processing gas.
Evacuate to about 1X10-' to 10-6 Torr. Further, wafer cooling is necessary in order to etch the etching target [18] according to the dimensions of the mask 17 as shown in FIG. 3(a), and if cooling is not performed,
). The cooling temperature varies depending on the processing gas used, but is usually about 0°C to -several tens of degrees Celsius. However, as in the configuration shown in FIG. 2, when the semiconductor wafer 4 is cooled from room temperature, for example to about 30° C., it takes about 1 minute. In addition, in order to cool the semiconductor sea urchin, remove moisture etc.
The gas becomes weak and the desired degree of vacuum is I x 10'-
There was a problem in that it took several minutes to evacuate to 10-10 Torr.
上記のように、従来例によるドライエツチング装置にお
いては、処理室1内のステージ3上で半導体ウェハ4を
常温まり一数十℃まで冷却を行うので、冷却完了まで時
間がかかり、また、冷却することにより半導体ウエノ飄
4上に付着してし)ろ水分等のアウトガスがしずらくな
り、所定の真空度のI X 1.0−’ 〜10−’T
orrまでに真空排気するまでにも数分の時間がかかり
、エツチング処理上でのスルーブッ)・を著しく低下さ
せるという問題点があった。As mentioned above, in the conventional dry etching apparatus, the semiconductor wafer 4 is cooled from room temperature to a few tens of degrees Celsius on the stage 3 in the processing chamber 1, so it takes time to complete cooling, and This makes it difficult for outgases such as filtrate water to adhere to the semiconductor substrate 4, and to reduce the temperature at a predetermined degree of vacuum from 1.0-' to 10-'T.
It takes several minutes to evacuate to orr, which poses a problem in that the throughput during the etching process is significantly reduced.
この発明は、上記のような問題点を解消するためになさ
れたもので、あらかじめ半導体ウエノ1上の水分等のア
ラ)−ガスと冷却を行っておき、処理室内での処理を迅
速に行えるようにしたドライエツチング装置を得ること
を目的とするものである。This invention was made in order to solve the above-mentioned problems, and by cooling the semiconductor wafer 1 with a gas such as moisture in advance, it is possible to speed up the processing in the processing chamber. The object of the present invention is to obtain a dry etching device with a high temperature.
この発明に係るドライエツチング装置は、予備室または
ウェハバッファ室に、予備室またはウェハバッファ室内
であらかしめ半導体ウニ/’1を昇温させる昇温手段と
、同じく冷却させる冷却手段とを備えたものである。The dry etching apparatus according to the present invention is provided with a temperature raising means for raising the temperature of the semiconductor urchin/'1 in the preliminary chamber or the wafer buffer chamber, and a cooling means for cooling the same. It is.
この発明におけるドライエツチング装置は、処理室内に
搬送される前にあらかじめ予備室内またはウェハバッフ
ァ室内において半導体ウニ/4に付着した水分等のアウ
トガスや、冷却を行った後に処理室内へ搬送するように
したので、処理室内においての所期の冷却温度に達する
までの冷却時間と、所期の真空度に達するまでの真空排
気時間を大きく短縮することができる。In the dry etching apparatus of the present invention, outgas such as moisture adhering to the semiconductor urchin/4 is removed in advance in the preliminary chamber or wafer buffer chamber before being transported into the processing chamber, and then the semiconductor wafer is cooled before being transported into the processing chamber. Therefore, the cooling time in the processing chamber to reach the desired cooling temperature and the evacuation time to reach the desired degree of vacuum can be greatly shortened.
以下、この発明の一実施例を第1図について説明する。 An embodiment of the present invention will be described below with reference to FIG.
第1図はこの発明の一実施例を示すドライエツチング装
置の概略構成図である。この図で、1〜16は第2図と
同一部分を示す。19は前記予備室11内に設けた予備
ステージで、半導体ウェハ4を100℃くらいまで昇温
させる乙とができる昇温機20と、−数十℃まで冷却さ
する冷却機21が接続されている。FIG. 1 is a schematic diagram of a dry etching apparatus showing an embodiment of the present invention. In this figure, 1 to 16 indicate the same parts as in FIG. 2. Reference numeral 19 denotes a preliminary stage provided in the preliminary chamber 11, to which a heating machine 20 capable of raising the temperature of the semiconductor wafer 4 to about 100 degrees Celsius and a cooler 21 capable of cooling it down to -several tens of degrees Celsius are connected. There is.
さて、このように構成されたこの発明の実施例において
は、処理室1内へ半導体ウェハ4を搬送する前に半導体
ウェハ4を予備ステージ19上に載置し、まず、半導体
ウェハ4を昇温させ、半導体ウェハ4上に付着した水分
等のアウトガスを行い、その後、半導体ウェハ4を所期
の値まで冷却する。この昇温、冷却は前の半導体ウェハ
4が処理室1でエツチング処理が行われている間に行わ
れ、処理終了とともに処理室1に搬送される。この後、
従来と同様の処理シーケンスが開始されるが、あらかじ
めアウトガスと冷却が行われているため、所定の真空度
、温度に達するまでの時間が大幅に短縮される。Now, in the embodiment of the present invention configured in this way, the semiconductor wafer 4 is placed on the preliminary stage 19 before being transported into the processing chamber 1, and the temperature of the semiconductor wafer 4 is first raised. The semiconductor wafer 4 is then cooled down to a desired temperature. This heating and cooling is performed while the previous semiconductor wafer 4 is undergoing etching processing in the processing chamber 1, and is transferred to the processing chamber 1 upon completion of the processing. After this,
The same processing sequence as before is started, but since outgassing and cooling have been performed in advance, the time it takes to reach the predetermined degree of vacuum and temperature is significantly shortened.
なお、上記実施例においては、半導体ウェハ4の昇温に
よるアウトガスおよび冷却を予備室11内で行ったが、
ウェハバッファ室13内において行っても良く、上記実
施例と同様の効果を奏する。In the above embodiment, outgassing and cooling of the semiconductor wafer 4 due to temperature rise were performed in the preliminary chamber 11.
It may also be carried out within the wafer buffer chamber 13, and the same effects as in the above embodiment can be achieved.
以上説明したように、この発明は、予備室またはウェハ
バッファ室に、予備室またはウニ八バッファ室内であら
かしめ半導体ウェハを昇温させる昇温手段と、同じく冷
却させる冷却手段とを備えたので、その後の処理シーケ
ンス内でのウェハ冷却真空排気の時間を大幅に短縮でき
、エツチング処理上のスルーブツトを大きく改善させる
という極めて優れた特徴を有するものである。As explained above, in the present invention, the preparatory chamber or the wafer buffer chamber is provided with a temperature raising means for warming the semiconductor wafer in the preparatory chamber or the wafer buffer chamber, and a cooling means for cooling the semiconductor wafer in the same manner. This method has extremely excellent features in that the time required for wafer cooling and vacuum evacuation in the subsequent processing sequence can be significantly shortened, and the throughput in etching processing can be greatly improved.
第1図はこの発明の一実施例を示すドライエツチング装
置の概要構成図、第2図のドライエツチング装置の概要
構成図、第3図はエツチング処理後のウェハ断面を示す
図である。
図において、1は処理室、2は排気路、3はステージ、
4は半導体ウェハ、5は冷却機、6はガス導入路、7は
導波管、8は石英窓、9はマイクロ波発生装置、10は
コイル、11は予備室、12は真空開閉手段、13はウ
ェハバッファ室、14は真空開閉手段、15はカセット
、16はウェハ搬送手段、19は予備ステージ、2oは
昇温機、21は冷却機である。
なお、各図中の同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄 (外2名)第1図
第2図
(a)
(b)
]○ コイルFIG. 1 is a schematic block diagram of a dry etching apparatus showing an embodiment of the present invention, FIG. 2 is a schematic block diagram of the dry etching apparatus shown in FIG. 2, and FIG. 3 is a diagram showing a cross section of a wafer after etching processing. In the figure, 1 is a processing chamber, 2 is an exhaust path, 3 is a stage,
4 is a semiconductor wafer, 5 is a cooler, 6 is a gas introduction path, 7 is a waveguide, 8 is a quartz window, 9 is a microwave generator, 10 is a coil, 11 is a preliminary chamber, 12 is a vacuum opening/closing means, 13 14 is a wafer buffer chamber, 14 is a vacuum opening/closing means, 15 is a cassette, 16 is a wafer transfer means, 19 is a preliminary stage, 2o is a temperature riser, and 21 is a cooler. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 (a) (b) ]○ Coil
Claims (1)
マ化し、半導体ウェハにドライ処理を施す処理室と、前
記処理室に真空開閉手段を介して具備された予備室と、
この予備室に真空開閉手段を介して具備されたウェハバ
ッファ室とで構成されたドライエッチング装置において
、前記予備室またはウェハバッファ室に、前記予備室ま
たはウェハバッファ室内であらかじめ前記半導体ウェハ
を昇温させる昇温手段と、同じく冷却させる冷却手段と
を備えたことを特徴とするドライエッチング装置。a processing chamber in which a processing gas is turned into plasma by a magnetic field and an electric field generated by microwaves to perform dry processing on semiconductor wafers; a preliminary chamber provided in the processing chamber via a vacuum opening/closing means;
In a dry etching apparatus comprising a wafer buffer chamber provided in the preliminary chamber via a vacuum opening/closing means, the semiconductor wafer is heated in advance in the preliminary chamber or wafer buffer chamber. A dry etching apparatus characterized in that it is equipped with a means for raising the temperature and a means for cooling the same.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15791190A JPH0448626A (en) | 1990-06-14 | 1990-06-14 | Dry etching apparatus |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15791190A JPH0448626A (en) | 1990-06-14 | 1990-06-14 | Dry etching apparatus |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0448626A true JPH0448626A (en) | 1992-02-18 |
Family
ID=15660148
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15791190A Pending JPH0448626A (en) | 1990-06-14 | 1990-06-14 | Dry etching apparatus |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0448626A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100364089B1 (en) * | 2000-08-03 | 2002-12-12 | 주식회사 아펙스 | Hot plate apparatus with vacuum buffer chamber |
-
1990
- 1990-06-14 JP JP15791190A patent/JPH0448626A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100364089B1 (en) * | 2000-08-03 | 2002-12-12 | 주식회사 아펙스 | Hot plate apparatus with vacuum buffer chamber |
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