JPH044756B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a notched insulated gate static induction transistor capable of high-speed switching and a method for manufacturing a notched insulated gate static induction transistor integrated circuit with high speed and low power consumption. .

(Prior Art) Insulated gate transistors have been used for high frequency amplification and integrated circuits, but they have the drawback of low driving capability. Currently, as a means of overcoming the drawbacks of such insulated gate transistors and increasing their speed, shortening the channel is being actively promoted. Gansho 52-1756
(No.) and a notched insulated gate static induction transistor (for example, Japanese Patent Application No. 13707/1982) have been proposed.

Insulated gate static induction transistors are designed so that the effect of the drain electric field extends to the source, and because current flows not only at the semiconductor/insulating film interface but also through the substrate, it has unsaturated current-voltage characteristics, making it difficult to drive. It has characteristics such as great ability. In particular, in the notch type insulated gate static induction transistor, since the channel is formed in the depth direction of the semiconductor substrate, the channel length and gate length can be easily controlled, and it is suitable for shortening the channel. Therefore, the driving capacity can be increased,
Additionally, because parasitic capacitance can be reduced, it exhibits superior performance as a high-speed transistor or a high-speed, low-power integrated circuit.

An example of a known manufacturing process for this notched insulated gate static induction transistor will be described with reference to FIG.

FIG. 5a Semiconductor substrate 5 used as a drain
After growing an epitaxial layer 52 to become a channel on 1 and introducing channel impurities by thermal diffusion or ion implantation, a U-shaped groove is formed in a part of the main surface of the semiconductor substrate by anisotropic plasma etching or the like.

FIG. 5b: Using ordinary photolithography technology and selective oxidation, a field oxide film 53 is formed, and a window is opened in a part of the semiconductor substrate surface including the sidewalls of the U-shaped groove, and the gate oxide is oxidized. A film 54 is formed.

Fig. 5c Polycrystalline silicon 55 which becomes the gate electrode
is deposited on the entire surface of the semiconductor substrate, including the side walls of the U-shaped groove, and then
After etching is performed so as to remain on the gate oxide film on the sidewalls of the trench, a source region 56 is formed by thermal diffusion or ion implantation.

FIG. 5d A passivation film 57 is deposited on the entire surface of the semiconductor substrate including the side walls of the U-shaped groove, a contact hole is formed, a drain electrode 51' is formed on the opposite surface of the semiconductor substrate, and a gate electrode 55' and a source electrode are formed on the surface of the semiconductor substrate. 56' respectively.

The impurity density of the drain region 51 and the source region 56 is about 10 ¹⁸ to 10 ²¹ cm ⁻³ , respectively.
Of course, the conductivity type may be P type or N type, and contrary to the above description, 51 may be a source region and 56 may be a drain region. The impurity density of the channel region 52 is
The conductivity type thereof may be ^the same as or opposite to that of the drain region and ^source region, and may have ^a multilayer structure. However, at least in a part of the operating region, the depletion layer extending from the drain region must reach the source region, and to meet this requirement, the impurity density is determined together with the depth of the U-shaped trench. be done. Also,
The thickness of the gate oxide film 54 is set to about 100 to 1000 Å, and polycrystalline silicon or the like is usually used for the gate electrode, and the thickness is set to about 1000 Å to 1 μm. The conventional notch-type insulated gate static induction transistor shown in this figure is originally formed in the depth direction of the semiconductor substrate, so the dimensions of the transistor can be controlled by the precision of the film formation, and short-channel high-speed Very suitable for transistors.

(Problems to be Solved by the Invention) However, the conventional manufacturing method for notched insulated gate static induction transistors uses normal photolithography technology, which requires a margin for mask alignment. However, it was difficult to form the gate electrode 55 only on the side walls of the U-shaped groove.

For example, FIG. 6 shows an example of a planar structure of a conventional notched insulated gate static induction transistor corresponding to the manufacturing process shown in FIG. In the figure, 61 is a side wall of a U-shaped trench, 62 is a window formed by selective oxidation, 63 is a polycrystalline semiconductor gate electrode, 64 and 65 are a drain contact hole and a gate contact hole, respectively, and 66 and 67 are respectively They are a drain electrode and a gate electrode. The BB' cross section in the same figure is the 5th section.
Shown in Figure d. 1 _b and 1 _c in the same figure are the 5th
This is the mask alignment margin for photolithography in steps (b) and (c) in the figure, and is usually set to about 0.1 to 2 μm.

Figure 7a shows an example of the drain current-drain voltage characteristics of transistors with different mask alignment margins _1c .
Shown in ~c. In this case, the channel length is approximately 0.5μm,
The channel impurity dose is approximately 1.5×10 ¹³ cm ^-2 , the gate oxide film thickness is approximately 250 Å, and the mask alignment margin _1c is 0 μm for (a), 1 μm for each of (b) and (c),
It is 2μm. The case shown in FIG. 5A exhibits unsaturated current-voltage characteristics, has a large driving capability, and exhibits well the characteristics of a notched insulated gate static induction transistor, but has the drawback of poor yield. On the other hand, in the cases of b and c in the same figure, since the portion corresponding to the mask alignment margin operates similarly to a planar transistor, the effective channel length becomes longer and the driving ability deteriorates.

An object of the present invention is to eliminate the drawbacks of the above-mentioned method for manufacturing a notched insulated gate static induction transistor, to form a gate oxide film and a gate electrode in a self-aligned manner only on the side walls of a U-shaped trench, and to improve reproducibility and reliability. The present invention aims to provide a method for manufacturing a notched insulated gate static induction transistor with improved properties.

(Means for Solving the Problem) In the notched insulated gate static induction transistor of the present invention and the method for manufacturing its integrated circuit, an anisotropic method is employed in which a U-shaped groove is formed on the surface of a semiconductor substrate serving as a drain or a source. etching process,
Using photolithography technology and selective oxidation method,
forming a field oxide film and a gate oxide film at predetermined positions on the surface of the semiconductor substrate including the side walls of the U-shaped trench; forming a gate electrode on the gate oxide film on the side walls of the U-shaped trench; Step of forming a source or drain region on the surface of the semiconductor substrate, the drain and gate electrodes are placed on the surface of the semiconductor substrate, and the source electrode is placed on the opposite surface of the semiconductor substrate in a single transistor, and on the surface of the semiconductor substrate in an integrated circuit. In the method for manufacturing a notch-type insulated gate static induction transistor, the step of forming the field oxide film and the gate oxide film applies selective oxidation mask material to the semiconductor substrate including the U-shaped groove sidewalls. a step of depositing the mask material over the entire surface; a step of removing the mask material except for a portion of the side wall of the U-shaped groove on which a gate oxide film will later be formed, and a region that will become a source or drain having a slight distance therefrom; The method consists of a step of forming a field oxide film by selective oxidation using the remaining mask material as a mask, and a step of removing the mask material and forming a gate oxide film in the area opened by the selective oxidation. Features.

Furthermore, as a method for forming the mask material for selective oxidation, a silicon nitride film is used as the mask material, and a polycrystalline silicon film deposited on the silicon nitride film is etched on the side walls of the U-shaped groove by anisotropic etching. The silicon nitride film is left in a self-aligned manner and is used as a mask to form a mask of the silicon nitride film.

Thereby, the gate oxide film and the gate electrode can be formed without being affected by variations in the mask alignment process, etc., and reproducibility and reliability can be improved.

(Examples) The present invention will be explained in detail below using examples.

FIG. 1 shows an embodiment of the manufacturing process of the notched insulated gate electrostatic induction according to the present invention.

Figure 1a Semiconductor substrate 1 used as a drain
After growing an epitaxial layer 12 to become a channel on 1 and introducing channel impurities by thermal diffusion or ion implantation, a U-shaped groove is formed in a part of the main surface of the semiconductor substrate by anisotropic plasma etching or the like.

Figure b: A selective oxidation mask material 13 is deposited over the entire surface of the semiconductor substrate, including the side walls of the U-shaped groove, and by combining ordinary photolithography and anisotropic plasma etching, the source material on the main surface of the semiconductor substrate is etched. Mask material is left in the area to be used as the gate and in the area on the side wall of the U-shaped groove to be used as the gate.

In addition to forming a field oxide film 15 using the selective oxidation method shown in FIG. Form.

Figure d: Polycrystalline silicon 16, which will become the gate electrode, is deposited over the entire surface of the semiconductor substrate, including the side walls of the U-shaped trench, and is deposited on the gate oxide film 14 on the side walls of the U-shaped trench using ordinary photolithography technology. After etching, a source region 17 is formed by thermal diffusion or ion implantation.

In the same figure, a passivation film 18 is deposited on the entire surface of the semiconductor substrate including the side walls of the U-shaped groove, a contact hole is formed, and a drain electrode 1 is formed on the opposite surface of the semiconductor substrate.
1', a gate electrode 16' and a source electrode 17' are formed on the surface of the semiconductor substrate, respectively.

At this time, the drain region 11, the source region 17
The impurity density of each is about 10 ¹⁸ to 10 ²¹ cm ^-3 . Of course, the conductivity type may be P type or N type, and 11
may be used as a source region and 17 as a drain region. The impurity density of the channel region 12 is 10 ¹² to 10 ¹⁶
cm ^-3 and its conductivity type may be the same as or opposite to the drain region 11 and source region 17, and may have a multilayer structure. However, at least in a part of the active region, the impurity density is determined together with the depth of the U-shaped trench so that the depletion layer extending from the drain region reaches the source region. Further, the thickness of the gate oxide film 14 is set to about 100 to 1000 Å.

According to this manufacturing process, the gate oxide film, which has the greatest effect on the characteristics of the device, can be formed in a self-aligned manner only on the side walls of the U-shaped trench, resulting in high reproducibility and reliability.
A notch insulated gate static induction transistor having device characteristics as shown in FIG. 7a can be obtained.

FIG. 2 shows in more detail the process of forming the mask material 13 shown in FIG. 1b.

Figure 2a Semiconductor substrate 2 used as a drain
After growing an epitaxial layer 22 to become a channel on the semiconductor substrate 1 and introducing channel impurities by thermal diffusion or ion implantation, a U-shaped groove is formed in a part of the semiconductor substrate surface by anisotropic plasma etching or the like.

Figure b: Silicon nitride film 23, which serves as a mask material for selective oxidation, and polycrystalline silicon 24, which serves as a mask material when patterning silicon nitride film 23, are successively deposited.
It is deposited over the entire surface of the semiconductor substrate, including the side walls of the U-shaped groove, using a CVD method or the like.

Figure c: By combining ordinary photolithography technology and anisotropic plasma etching, polycrystalline silicon 2 is formed on the source region on the main surface of the semiconductor substrate and the gate region on the side wall of the U-shaped trench.
Leave 4. Anisotropic plasma etching of the polycrystalline silicon 24 is possible using, for example, PCl ₃ at a gas pressure of about 0.1 Torr.

FIG. 4D: Using the polycrystalline semiconductor 24 as a mask material, the silicon nitride film 23, which will serve as a mask material for selective oxidation, is etched.

Through such a process, the silicon nitride film, which is a mask material for selective oxidation, can be formed only on the U-shaped sidewalls in a self-aligned manner. Of course, it is also possible to perform anisotropic etching directly on the silicon nitride film, but according to this method, the silicon nitride film can be etched by wet etching using phosphoric acid boiling, etc., and is etched without causing damage. can be done.

FIG. 3 shows an example of a planar structure of a notched insulated gate static induction transistor corresponding to the manufacturing process shown in FIGS. 1 and 2. In the figure, 31 is a side wall of a U-shaped trench, 32 is a window formed by selective oxidation that becomes an element region, and 3
3 is a gate electrode of a polycrystalline semiconductor, 34 and 35 are a drain contact hole and a gate contact hole, respectively, and 36 and 37 are a drain electrode and a gate electrode, respectively. A- in the same figure
Section A' is shown in FIG. 1e. I _d in the figure is the mask alignment margin for the photolithography step (d) shown in the first diagram, and is usually set to about 0.1 μm to 2 μm, but since this part is a thick field oxide film, the gate electrode Even if they overlap, it does not have a major effect on the device characteristics.

FIG. 4 shows an example of the cross-sectional structure of one gate when this notched insulated gate static induction transistor is applied to a complementary insulated gate integrated circuit. 40 in the same figure is a semiconductor substrate, and a U-shaped groove is provided in a part of its main surface. Also 41 is N ⁺
Drain region, 42 is P ⁺ drain region, 43 is
The N ⁺ source region and 44 are P ⁺ source regions, each having an impurity density of about 10 ¹⁸ to 10 ²¹ cm ⁻³ . 4
5 is a P channel region, and 46 is an N channel region, each having an impurity density of about 10 ¹² to ^{10 16} cm ^-3 ,
The impurity density is determined together with the depth of the U-shaped groove so that a depletion layer extending from the drain region reaches the source region in at least a part of the active region. 47 is a gate insulating film such as an oxide film, which has a thickness of about 100 to 1000 Å;
7' is a gate electrode, and 48 is a field oxide film. Further, 49 is a P well for separating the P channel and the N channel. The gate electrode 47' is a logic input, the drain electrodes 41' and 42' are logic outputs, and a source electrode, not shown, is formed on the surface of the semiconductor substrate at a portion shifted in the direction perpendicular to the plane of the paper, and a power supply voltage is applied thereto.

Such integrated circuits can be manufactured using almost the same manufacturing process as shown in Figure 1, except for the structure on the substrate side, and can be used to create complementary insulated gate integrated circuits that are reproducible, reliable, high speed, and have low power consumption. can be provided. For example, in the ring oscillator of the complementary insulated gate integrated circuit shown in FIG. 4, a propagation delay time of 430 psec is obtained at a power consumption of 10 mW.

(Effects of the Invention) As described above, according to the present invention, the drawbacks of the manufacturing process of the conventional notch type insulated gate static induction transistor are improved, and the gate oxide film is formed in a self-aligned manner only on the sidewalls of the U-shaped trench. Therefore, it is possible to form notched insulated gate static induction transistors capable of high-speed switching and notched insulated gate static induction transistor integrated circuits with high speed and low power consumption with high reproducibility and reliability. It can be produced and its industrial value is extremely large.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the manufacturing process showing one embodiment of the method for manufacturing a notched insulated gate static induction transistor of the present invention, FIG. 2 is a detailed explanatory diagram of the mask material forming process, and FIG. 3 is an explanatory diagram of the manufacturing method of the invention. FIG. 4 is a cross-sectional view showing an embodiment of the notched insulated gate static induction transistor integrated circuit of the present invention, and FIG. 5 is a conventional notched insulated gate static induction transistor integrated circuit. An explanatory diagram of a manufacturing process showing an example of a method for manufacturing an insulated gate static induction transistor, FIG. 6 is a plan view showing the planar structure of the notched insulated gate static induction transistor, and FIG. 7 is a conventional notched insulated gate static induction transistor. FIG. 2 is a characteristic diagram showing an example of drain current-drain voltage characteristics of an insulated gate static induction transistor. 11, 21, 40, 51: semiconductor substrate (drain region), 12, 22, 45, 46, 52: channel region, 13, 23, 24: mask material, 15,
48, 53: Field oxide film, 14, 47, 5
4: Gate insulating film, 16, 33, 55: Gate electrode, 11', 36, 51': Drain electrode, 17,
43, 44, 56: source area, 17', 56':
Source electrode, 18, 57: Passivation film,
31: U-shaped groove side wall, 32: Element area window, 49:
Separation layer.

Claims (1)

[Claims] 1. An anisotropic etching process for forming a U-shaped groove on the surface of a semiconductor substrate that will become a drain or source;
Using photolithography technology and selective oxidation method,
forming a field oxide film and a gate oxide film at predetermined positions on the surface of the semiconductor substrate including the side walls of the U-shaped trench; forming a gate electrode on the gate oxide film on the side walls of the U-shaped trench; Forming the field oxide film and the gate oxide film in a method for manufacturing a notch-type insulated gate static induction transistor, comprising a step of forming a source or drain region in a region, and a step of forming a drain, gate, and source electrode at predetermined positions, respectively. The step of depositing a mask material for selective oxidation on the entire surface of the semiconductor substrate including the sidewalls of the U-shaped trench, the portion of the sidewall of the U-shaped trench on which a gate oxide film will later be formed, and a small distance therebetween. a step of removing the mask material except for a region that will become a source or a drain having 〓, a step of forming a field oxide film by a selective oxidation method using the remaining mask material as a mask, removing the mask material, A manufacturing method comprising the step of forming a gate oxide film in the portion opened by the selective oxidation. 2. Using a silicon nitride film as a mask material for the selective oxidation, the polycrystalline silicon film deposited on the silicon nitride film is left in a self-aligned manner on the side wall of the U-shaped groove by anisotropic etching; Claim 1, further comprising the step of forming a mask of the silicon nitride film using this as a mask.
A method for manufacturing a notch-type insulated gate static induction transistor. 3. Manufacturing a notched insulated gate static induction transistor according to claim 1 or 2, characterized in that a large number of notched insulated gate static induction transistors are integrally formed on a semiconductor substrate by the above method. Method.