JPH0447453B2 - - Google Patents

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Publication number
JPH0447453B2
JPH0447453B2 JP56122874A JP12287481A JPH0447453B2 JP H0447453 B2 JPH0447453 B2 JP H0447453B2 JP 56122874 A JP56122874 A JP 56122874A JP 12287481 A JP12287481 A JP 12287481A JP H0447453 B2 JPH0447453 B2 JP H0447453B2
Authority
JP
Japan
Prior art keywords
amorphous silicon
layer
light
type
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56122874A
Other languages
Japanese (ja)
Other versions
JPS5823434A (en
Inventor
Yoshihiro Hamakawa
Yoshihisa Oowada
Kazunaga Tsushimo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kanegafuchi Chemical Industry Co Ltd
Original Assignee
Kanegafuchi Chemical Industry Co Ltd
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Application filed by Kanegafuchi Chemical Industry Co Ltd filed Critical Kanegafuchi Chemical Industry Co Ltd
Priority to JP56122874A priority Critical patent/JPS5823434A/en
Publication of JPS5823434A publication Critical patent/JPS5823434A/en
Publication of JPH0447453B2 publication Critical patent/JPH0447453B2/ja
Granted legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/48Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation
    • C23C16/482Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating by irradiation, e.g. photolysis, radiolysis, particle radiation using incoherent light, UV to IR, e.g. lamps
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/517Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using a combination of discharges covered by two or more of groups C23C16/503 - C23C16/515
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Organic Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Plasma & Fusion (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Photovoltaic Devices (AREA)

Description

【発明の詳細な説明】 本発明はアモルフアスシリコン系の半導体及び
その製造方法、殊に光起電力素子とその製造方法
に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amorphous silicon semiconductor and a method for manufacturing the same, and particularly to a photovoltaic device and a method for manufacturing the same.

シラン(SiH4)のプラズマ分解法で得られる
アモルフアスシリコンは、W.E.Spear等によつ
て、PH3やB2H6でドープする事により、その伝
導度を大きく変える事ができる事が発見され
(1976年)、D.E.Carlson等によつてアモルフアス
シリコンを用いた太陽電池が試作(1976年)され
て以来注目を集め、アモルフアスシリコン薄膜太
陽電池の効率を改善する研究が活発に行なわれて
いる。
It was discovered by WESpear et al. that the conductivity of amorphous silicon obtained by plasma decomposition of silane (SiH 4 ) could be greatly changed by doping it with PH 3 or B 2 H 6 ( Since solar cells using amorphous silicon were prototyped by DE Carlson et al. (1976), they have attracted attention, and research has been actively conducted to improve the efficiency of amorphous silicon thin-film solar cells.

これまでの研究により、アモルフアスシリコン
薄膜光電素子の構造としてはシヨツトキーバリヤ
ー型、pin型、MIS型、ヘテロ型合型があり、そ
のうち前三者が高効率太陽電池として有望視され
ている。すなわちシヨツトキーバリヤー型で5.5
%(D.E.カールソン他、1977年)、MIS型で4.8%
(J.I.B.ウイルソン他、1978)、pin型で4.5%(浜
川圭弘1978)の変換効率が達成されている。
Research has shown that amorphous silicon thin-film photovoltaic devices can be structured as shot-key barrier type, pin type, MIS type, or heterostructure type, of which the first three are considered to be promising as high-efficiency solar cells. . i.e. 5.5 for shot key barrier type.
% (DE Carlson et al., 1977), 4.8% for MIS type
(JIB Wilson et al., 1978), and a conversion efficiency of 4.5% (Keihiro Hamakawa, 1978) has been achieved in the pin type.

ところが、このような素子の製膜において、特
にi層の成長速度が1〜2Å/秒と遅く、この成
長速度の遅いことが安価な素子を製造するという
点では大きな阻害要因となつていた。このような
欠点を改善する為に反応条件を変更しようとする
種々の試みがなされてきた。例えば、グロー放電
におけるパワーを増大せしめて成長速度を上げよ
うとする試みがそれである。しかし、パワーを上
げればプラズマによるボンバードメントの影響が
大きくなり、膜質が悪くなつてしまう現状である
〔J.C.Knights:Appl.Phys.Lett.35(3)244(1979)〕。
または、動作圧力を調整したり、基板温度を変更
したりすることによつて、成長速度を上げようと
する試みもなされていたが、いずれも膜質(特に
電気特性)の低下を招いてしまうという欠点を有
していた。
However, in the film formation of such devices, the growth rate of the i-layer in particular is as slow as 1 to 2 Å/sec, and this slow growth rate has been a major impediment to manufacturing inexpensive devices. Various attempts have been made to modify the reaction conditions in order to improve these drawbacks. For example, attempts have been made to increase the growth rate by increasing the power in glow discharge. However, as the power is increased, the effect of plasma bombardment increases, and the film quality deteriorates [JCKnights: Appl. Phys. Lett. 35(3) 244 (1979)].
Alternatively, attempts have been made to increase the growth rate by adjusting the operating pressure or changing the substrate temperature, but these methods lead to a decrease in film quality (especially electrical properties). It had drawbacks.

本発明者らは膜質の低下をきたさないで薄膜の
成長速度を増大させることを主眼にして鋭意研究
努力した結果、グロー放電分解に際して、好まし
くは5000Å以下の波長を有する光による光分解反
応を補助的に用いることにより、実用的な成長速
度で、電気的にも光学的にも良質の薄膜が得られ
ることを見い出した。
As a result of intensive research efforts focused on increasing the growth rate of thin films without deteriorating film quality, the present inventors have found that during glow discharge decomposition, the photolysis reaction is assisted by light having a wavelength of preferably 5000 Å or less. We have discovered that by using this method, thin films with good electrical and optical quality can be obtained at a practical growth rate.

しかも、驚くべきことに、p型又はn型のアモ
ルフアスシリコン半導体の製膜においては、上記
の光を照射することによりドーピング効率をかな
りの程度まで改善できることをも見い出し、本発
明を完成するに至つた。
Surprisingly, it was also discovered that the doping efficiency can be improved to a considerable extent by irradiating the above light in the film formation of p-type or n-type amorphous silicon semiconductors. I've reached it.

以下にその詳細を説明する。 The details will be explained below.

本発明のアモルフアスシリコン系半導体は、シ
リコン化合物の気体又は希釈用ガスと混合された
シリコン化合物の気体を、容量結合法又は誘導結
合法による高周波グロー放電分解又は直流グロー
放電分解するに際して、補助的に後述の如き光分
解反応を用いることにより得られる。シリコン化
合物としてはシラン(SiH4)又はその誘導体、
フツ化シラン(SiH4)又はその誘導体、或はこ
れらの混合物が主に使用される。シリコン化合物
と混合する希釈用ガスとしては、水素、アルゴン
ガス、ヘリウム、又は炭素の水素若しは窒素若し
はフツ素化合物、窒素の水素若しくはフツ素化合
物、或はこれらの混合物が使用される。混合ガス
中のシリコン化合物の濃度は、通常0.5%以上で
ある。勿論、希釈用ガスを使用しなくても差支え
ない。
The amorphous silicon-based semiconductor of the present invention can be used as an auxiliary when decomposing a silicon compound gas or a silicon compound gas mixed with a diluent gas by high frequency glow discharge or direct current glow discharge using a capacitive coupling method or an inductive coupling method. can be obtained by using a photolysis reaction as described below. As silicon compounds, silane (SiH 4 ) or its derivatives,
Fluorinated silane (SiH 4 ) or its derivatives or mixtures thereof are mainly used. As the diluting gas to be mixed with the silicon compound, hydrogen, argon gas, helium, a hydrogen or nitrogen or fluorine compound of carbon, a hydrogen or fluorine compound of nitrogen, or a mixture thereof is used. . The concentration of silicon compounds in the mixed gas is usually 0.5% or more. Of course, there is no problem even if the dilution gas is not used.

グロー放電分解の条件は一般に採用されている
のと同様の条件でよく、例えば特開昭52−122471
号公報、特開昭55−68681号公報等に記載されて
いるものが採用できる。
The conditions for glow discharge decomposition may be the same as those generally adopted, for example, as described in JP-A-52-122471.
Those described in Japanese Patent Application Laid-Open No. 55-68681, etc. can be used.

グロー放電分解によりアモルフアスシリコン、
アモルフアスシリコンカーバイド、アモルフアス
シリコンナイトライド又はこれらの混合物から成
る半導体(以下、これらをすべて含めてアモルフ
アスシリコン系半導体という)を製造できる訳で
あるが、周期律表族の元素でドーピングするこ
とによりp型のアモルフアスシリコン系半導体
を、また周期律表族の元素でドーピングするこ
とによりn系のアモルフアスシリコン系半導体を
得ることができる。
Amorphous silicon is produced by glow discharge decomposition.
Semiconductors made of amorphous silicon carbide, amorphous silicon nitride, or a mixture thereof (hereinafter referred to as amorphous silicon-based semiconductors) can be manufactured by doping with elements from the periodic table group. By doping a p-type amorphous silicon-based semiconductor with an element of the periodic table, an n-type amorphous silicon-based semiconductor can be obtained.

本発明ではp層、i層、又はn層のうちの少な
くとも一つの層の成長時において、グロー放電と
ともにシリコン化合物等を分解し得る光(通常
5000Å以下好ましくは4200Å以下の波長で、20m
W/cm2以上好ましくは50W/cm2以上の強度を有す
る光)を照射し、該層の膜の成長速度を大幅に増
大させるものである。また、グロー放電を実施す
る反応器の直前に前室を設け、これに上記の光を
照射するようにしてもよい。
In the present invention, during the growth of at least one of the p-layer, i-layer, or n-layer, light (usually
20m at a wavelength of 5000Å or less, preferably 4200Å or less
The growth rate of the layer is greatly increased by irradiating the layer with light having an intensity of W/cm 2 or more, preferably 50 W/cm 2 or more. Alternatively, a front chamber may be provided immediately before the reactor in which glow discharge is performed, and the above-mentioned light may be irradiated onto the front chamber.

照射する光の波長に関しては5000Å以下又、そ
の強度に関しては20W/cm2以上であるならば、特
に制限はないが、エネルギーコスト等の経済性並
びに光を投入する窓材料の問題等から、波長に関
しては700Å以上、強度に関しては1000W/cm2
下が好ましい。
There are no particular restrictions on the wavelength of the irradiated light as long as it is 5000 Å or less, and as long as its intensity is 20 W/cm 2 or more, but due to economic considerations such as energy costs and problems with the window material that inputs the light, the wavelength In terms of strength, it is preferably 700 Å or more, and in terms of strength, it is preferably 1000 W/cm 2 or less.

本発明の効果は、電気的特性に代表される膜質
を損うことなく成長速度を著しく増大できること
であり、更にドーピング効率をも改善できるとい
うことである。
The effects of the present invention are that the growth rate can be significantly increased without impairing the film quality represented by the electrical properties, and that the doping efficiency can also be improved.

本発明のアモルフアスシリコン系半導体は通常
のアモルフアスシリコン系半導体と同様に、太陽
電池、光スイツチ、光検出器又は感光体材料等に
適用できる。このうち、光起電力素子である太陽
電池に適用した場合を例にとつて、本発明を詳細
に説明する。
The amorphous silicon semiconductor of the present invention can be applied to solar cells, optical switches, photodetectors, photoreceptor materials, etc. in the same way as ordinary amorphous silicon semiconductors. The present invention will be described in detail by taking as an example the case where the present invention is applied to a solar cell which is a photovoltaic element.

本発明の適用が可能な太陽電池は、p層側から
太陽光を照射するタイプ、例えばガラス/透明電
極/p−i−nアモルフアスシリコン/アルミニ
ウムの構成のもの、又はn層側から太陽光を照射
するタイプ、例えばステンレス/p−i−nアモ
ルフアスシリコン/透明電極の構成のもの等、
種々のものがある。他の例としては、p層と透明
電極との間に薄い絶縁層をつけたり、薄い金属層
をつけた構造のもの、或はシヨツトキーバリヤー
型のもの、MIS型のもの等がある。要は以下に述
べる如く、真性アモルフアスシリコンを活性層と
する太陽電池であればいかなる構成のものであつ
てもよい。
A solar cell to which the present invention can be applied is a type in which sunlight is irradiated from the p-layer side, such as a structure of glass/transparent electrode/p-i-n amorphous silicon/aluminum, or a solar cell that irradiates sunlight from the n-layer side. Types that emit light, such as stainless steel/p-i-n amorphous silicon/transparent electrode configurations, etc.
There are various types. Other examples include structures in which a thin insulating layer is provided between the p-layer and the transparent electrode, a thin metal layer is provided, a shot key barrier type, and an MIS type. In short, as described below, the solar cell may have any configuration as long as it has an active layer of intrinsic amorphous silicon.

使用する基板としては、透明電極(ITO、
SnO2等)を蒸着したガラスや高分子フイルム、
金属等、通常の太陽電池の構成に用いられるあら
ゆる基板が使用可能である。
The substrate used is a transparent electrode (ITO,
Glass or polymer film with vapor-deposited SnO 2 , etc.
Any substrate used in typical solar cell construction can be used, such as metal.

シリコン化合物或は希釈用ガスと混合されたシ
リコン化合物をグロー放電分解として得られる約
10-7秒以上のキヤリヤー寿命で約1017cm-2eV-1
下の局在準位密度及び10-3cm2/V・秒以上の易
動度をもつ真性アモルフアスシリコンをi層と
し、例えばp型ドープ半導体とn型ドープ半導体
で接合したpin接合構造にする。pin接合を用いた
場合の太陽電池としての代表的な構成は透明電
極/p型アモルフアス半導体/i型アモルフアス
半導体/n型アモルフアス半導体/電極の構造
で、透明電極側から光を照射する。透明電極は
ITOやSnO2特にSnO2が好ましく、ガラス基板に
あらかじめ蒸着して用いたりp型アモルフアス半
導体上に直接蒸着してもよい。太陽光を照射する
側のp層の厚みは約30〜300Å好ましくは50〜200
Å、i層の厚みは約2500〜10000Åが用いられる。
n層はオーミツクコンタクトをとる為の層でもあ
り厚みは限定されないが、約150〜600Åが用いら
れる。
Approx. obtained by glow discharge decomposition of silicon compounds or silicon compounds mixed with diluent gas.
The i-layer is made of intrinsic amorphous silicon, which has a carrier lifetime of 10 -7 seconds or more, a local level density of about 10 17 cm -2 eV -1 or less, and a mobility of 10 -3 cm 2 /V sec or more. For example, a pin junction structure is formed in which a p-type doped semiconductor and an n-type doped semiconductor are connected. A typical configuration of a solar cell using a pin junction is a structure of transparent electrode/p-type amorphous semiconductor/i-type amorphous semiconductor/n-type amorphous semiconductor/electrode, and light is irradiated from the transparent electrode side. The transparent electrode
ITO and SnO 2 , particularly SnO 2 , are preferred, and may be used by being vapor-deposited on a glass substrate in advance, or may be directly vapor-deposited on a p-type amorphous semiconductor. The thickness of the p layer on the side exposed to sunlight is approximately 30 to 300 Å, preferably 50 to 200 Å.
The thickness of the i-layer is about 2,500 to 10,000 Å.
The n-layer is also a layer for establishing ohmic contact, and its thickness is not limited, but approximately 150 to 600 Å is used.

もう一つの代表的な構成は 透明電極/n型アモルフアス半導体/i型アモ
ルフアス半導体/p型アモルフアス半導体/電極
の構造で、透明電極側から太陽光を照射する。光
を照射する側のn層の厚みは約30〜300Å好まし
くは50〜200Å、i層の厚みは2500〜10000Åが通
常用いられる。p層の厚みは限定されないが約
150〜600Åが用いられる。透明電極の素材及び蒸
着法については前同様である。
Another typical configuration is a transparent electrode/n-type amorphous semiconductor/i-type amorphous semiconductor/p-type amorphous semiconductor/electrode structure, in which sunlight is irradiated from the transparent electrode side. The thickness of the n-layer on the side to which light is irradiated is approximately 30 to 300 Å, preferably 50 to 200 Å, and the thickness of the i-layer is generally 2,500 to 10,000 Å. The thickness of the p layer is not limited, but is approximately
150-600 Å is used. The material and vapor deposition method for the transparent electrode are the same as before.

次に、実施例により本発明の効果について説明
するが、本発明は以下の実施例による限定される
ものではない。
Next, the effects of the present invention will be explained with reference to examples, but the present invention is not limited to the following examples.

対照例 内径11cmの石英反応管を用い基板温度250℃に
て13.56MHzの高周波でグロー放電分解を行つた。
i型アモルフアスシリコンは水素で希釈したシラ
ンを5Torrでグロー放電分解して得られた。n型
アモルフアスシリコンは水素で希釈したシランと
フオスフイン(PH3)(PH3/SiH4=0.5モル%)
を同様にグロー放電分解して得られた。p型アモ
ルフアスシリコンは水素で希釈したシランとジボ
ラン(B2H6)(B2H6/SiH4=0.2モル%)を同様
にグロー放電分解して得られた。i層の成長速度
は1.8Å/秒であつた。また、p層及びn層の20
℃における暗電気伝導度はそれぞれ4×10-3
(Ω・cm)-1、2×10-2(Ω・cm)-1であつた。
Control Example Glow discharge decomposition was performed using a quartz reaction tube with an inner diameter of 11 cm and a high frequency of 13.56 MHz at a substrate temperature of 250°C.
I-type amorphous silicon was obtained by glow discharge decomposition of silane diluted with hydrogen at 5 Torr. N-type amorphous silicon is made of silane diluted with hydrogen and phosphine (PH 3 ) (PH 3 /SiH 4 = 0.5 mol%)
was similarly obtained by glow discharge decomposition. P-type amorphous silicon was similarly obtained by glow discharge decomposition of silane diluted with hydrogen and diborane (B 2 H 6 ) (B 2 H 6 /SiH 4 =0.2 mol %). The growth rate of the i-layer was 1.8 Å/sec. In addition, 20
The dark conductivity at °C is 4×10 -3 respectively.
(Ω・cm) -1 and 2×10 -2 (Ω・cm) -1 .

太陽電池の構成は、25Ω/□のSnO2の薄膜の
ついたガラス基板のSnO2面上にアモルフアスシ
リコンをp型、i型、n型の順に成長せしめ最後
に3.3mm2のアルミニウムを蒸着し成るものであつ
た。次に、AM−1(100mW/cm2)のソーラーシ
ユミレーターを用いて太陽電池特性を調べた。p
層が135Å、i層が500Å、n層が500Åの厚みを
有する上記構成に係る太陽電池の特性は短絡電流
Jsc=10.3mA/cm2、開放電圧Voc=0.75volts、
変換効率η=4.6%であつた。
The structure of the solar cell is to grow amorphous silicon in the order of p-type, i-type, and n-type on the SnO 2 surface of a glass substrate with a 25Ω/□ SnO 2 thin film, and finally evaporate 3.3 mm 2 of aluminum. It was something that could be done. Next, solar cell characteristics were investigated using an AM-1 (100 mW/cm 2 ) solar simulator. p
The characteristics of the solar cell according to the above structure, in which the layer has a thickness of 135 Å, the i-layer has a thickness of 500 Å, and the n-layer has a thickness of 500 Å, are short-circuit current.
Jsc=10.3mA/cm 2 , open circuit voltage Voc=0.75volts,
The conversion efficiency η was 4.6%.

実施例 1 対照例と同じ反応管の一部にCaF2の窓を設け、
光源から光線を、基板の上面に基板面と平行に導
入できるようにした。1500〜2000Åの波長範囲で
連続光を有する低圧キセノンランプを光源とし、
前記CaF2の窓から50mW/cm2の強度で入射させ
た。他の条件は、対照例と同様にした。
Example 1 A CaF 2 window was provided in a part of the same reaction tube as in the control example,
The light beam from the light source can be introduced onto the top surface of the substrate parallel to the substrate surface. The light source is a low-pressure xenon lamp with continuous light in the wavelength range of 1500 to 2000 Å,
The light was applied through the CaF 2 window at an intensity of 50 mW/cm 2 . Other conditions were the same as in the control example.

i層の成長速度は7Å/秒、p層及びn層の20
℃における暗電気伝導度はそれぞれ8×10-3
(Ω・cm)-1、5×10-2(Ω・cm)-1であつた。
The growth rate of the i-layer is 7 Å/sec, and the growth rate of the p-layer and n-layer is 20
The dark conductivity at ℃ is 8×10 -3 respectively.
(Ω・cm) -1 and 5×10 -2 (Ω・cm) -1 .

また、この製造方法により、対照例と同じ厚み
を有する太陽電池を製造した。該太陽電池の特性
は、 Jsc=11.9mA/cm2、Voc=0.79volts、η=5.7% であつた。
Furthermore, a solar cell having the same thickness as the control example was manufactured using this manufacturing method. The characteristics of the solar cell were: Jsc=11.9 mA/cm 2 , Voc=0.79 volts, and η=5.7%.

このように、i層の成長速度は光を照射しない
場合の約4倍となつた。またp層及びn層の20℃
における暗電気伝導度はいずれも2倍程度向上し
た。これらにより太陽電池の性能は24%も改善さ
れた。
Thus, the growth rate of the i-layer was approximately four times that of the case without irradiation with light. Also, 20℃ of p layer and n layer
The dark electrical conductivity in both cases was improved by about 2 times. These improvements improved solar cell performance by 24%.

実施例 2 光源を高圧キセノンランプとし、5000Å以上の
波長部分をフイルターにより除去した後、前記
CaF2の窓から20mW/cm2の強度で光線を入射さ
せた他は、すべて実施例1と同様にした。
Example 2 A high-pressure xenon lamp was used as the light source, and after removing the wavelength region of 5000 Å or more with a filter,
Everything was the same as in Example 1, except that a light beam was made incident through the CaF 2 window at an intensity of 20 mW/cm 2 .

i層の成長速度は4Å/秒となり、光を照射し
ない場合の約2倍の速度を得た。
The growth rate of the i-layer was 4 Å/sec, which was about twice the growth rate when no light was irradiated.

実施例 3 光分解反応を実施するための前室をグロー放電
分解反応器の直前に設置し、これにLiFの窓を設
け、このLiFの窓から、1200〜1800Åの波長範囲
で連続光を有する低圧クリプトンランプを光源と
する30mW/cm2の強度の光を入射させた。他の条
件は対照例と同じであつた。
Example 3 An antechamber for carrying out the photolysis reaction was installed immediately before the glow discharge decomposition reactor, and a LiF window was provided in it, from which continuous light was emitted in the wavelength range of 1200 to 1800 Å. Light with an intensity of 30 mW/cm 2 was incident from a low-pressure krypton lamp as a light source. Other conditions were the same as the control example.

i層の成長速度は10Å/秒、p層及びn層の20
℃における暗電気伝導度はそれぞれ2.5×10-2
(Ω・cm)-1、7×10-2(Ω・cm)-1となり、成長速
度及びドーピング効率が大きく向上した。
The growth rate of the i-layer is 10 Å/sec, and the growth rate of the p-layer and n-layer is 20 Å/sec.
The dark conductivity at °C is 2.5×10 -2 respectively.
(Ω·cm) -1 and 7×10 -2 (Ω·cm) -1 , and the growth rate and doping efficiency were greatly improved.

実施例 4 実施例3で用いた光源を使用し、実施例1で用
いた装置の窓材料のみをLiFに変更した装置に、
水素で希釈したシラン、シボラン、メタン
(CH4)をSiH4/CH4=1、B2H6/(SiH4
CH4)=0.2モル%の流量比で導入する以外は実施
例1と同様にした。得られたp層の暗電気伝導度
(20℃)は、4×10-5(Ω・cm)-1であつた。なお、
他の条件を同じにして光を照射しない場合に得ら
れたp層の暗電気伝導度は、20℃で5×10-6
(Ω・cm)-1であつた。
Example 4 The light source used in Example 3 was used, and only the window material of the device used in Example 1 was changed to LiF.
Silane, siborane, and methane (CH 4 ) diluted with hydrogen are prepared as SiH 4 /CH 4 =1, B 2 H 6 /(SiH 4 +
The procedure was the same as in Example 1 except that CH 4 ) was introduced at a flow rate of 0.2 mol %. The dark electrical conductivity (20° C.) of the obtained p-layer was 4×10 −5 (Ω·cm) −1 . In addition,
The dark electrical conductivity of the p-layer obtained when other conditions are the same and no light is irradiated is 5 × 10 -6 at 20°C.
(Ω・cm) -1 .

Claims (1)

【特許請求の範囲】 1 少くともi層製膜時に5000Å以下の波長の光
による光分解反応を補助的に施して、シリコン化
合物をプラズマ分解することによりアモルフアス
シリコン系半導体のpin接合を有する光起電力装
置の製造方法。 2 前記プラズマ分解に際し、周期律表族又は
族の元素でドーピングすることを特徴とする特
許請求の範囲第1項記載の光起電力装置の製造方
法。 3 前記アモルフアスシリコン系半導体はアモル
フアスシリコン、アモルフアスシリコンカーバイ
ド(a−SiC)、アモルフアスシリコンナイトラ
イド(a−SiN)又はそれらの混合物であること
を特徴とする特許請求の範囲第1項又は第2項記
載の光起電力装置の製造方法。 4 光分解反応に用いる光の強度が20mw/cm2
上であることを特徴とする特許請求の範囲第1項
又は第2項記載の光起電力装置の製造方法。
[Claims] 1. At least during the formation of the i-layer film, a photolysis reaction using light with a wavelength of 5000 Å or less is auxiliary to plasma decompose a silicon compound, thereby forming a pin junction of an amorphous silicon semiconductor. Method for manufacturing an electromotive force device. 2. The method for manufacturing a photovoltaic device according to claim 1, wherein during the plasma decomposition, doping is performed with an element belonging to a group or groups of the periodic table. 3. Claim 1, wherein the amorphous silicon-based semiconductor is amorphous silicon, amorphous silicon carbide (a-SiC), amorphous silicon nitride (a-SiN), or a mixture thereof. Or the method for manufacturing a photovoltaic device according to item 2. 4. The method for manufacturing a photovoltaic device according to claim 1 or 2, wherein the intensity of the light used for the photodecomposition reaction is 20 mw/cm 2 or more.
JP56122874A 1981-08-04 1981-08-04 Amorphous silicon semiconductor Granted JPS5823434A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56122874A JPS5823434A (en) 1981-08-04 1981-08-04 Amorphous silicon semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56122874A JPS5823434A (en) 1981-08-04 1981-08-04 Amorphous silicon semiconductor

Publications (2)

Publication Number Publication Date
JPS5823434A JPS5823434A (en) 1983-02-12
JPH0447453B2 true JPH0447453B2 (en) 1992-08-04

Family

ID=14846759

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56122874A Granted JPS5823434A (en) 1981-08-04 1981-08-04 Amorphous silicon semiconductor

Country Status (1)

Country Link
JP (1) JPS5823434A (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59177919A (en) * 1983-03-28 1984-10-08 Nippon Telegr & Teleph Corp <Ntt> Selective growth of thin film
JPS59188641A (en) 1983-04-11 1984-10-26 Fuji Photo Film Co Ltd Silver halide photographic emulsion
JPS60175411A (en) * 1984-02-22 1985-09-09 Hitachi Ltd Manufacture of thin semiconductor film and apparatus thereof
JP2577543B2 (en) * 1984-08-08 1997-02-05 新技術事業団 Single crystal thin film growth equipment
US5753017A (en) 1995-10-16 1998-05-19 Konica Corporation Ink jet recording ink and recording method employing the same
CN102496663A (en) * 2011-12-29 2012-06-13 普乐新能源(蚌埠)有限公司 Method for reducing attenuation rate of amorphous silicon solar cell

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56124229A (en) * 1980-03-05 1981-09-29 Matsushita Electric Ind Co Ltd Manufacture of thin film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56124229A (en) * 1980-03-05 1981-09-29 Matsushita Electric Ind Co Ltd Manufacture of thin film

Also Published As

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