JPH0445584A - Phase transition type memory element and its manufacture - Google Patents

Abstract

PURPOSE:To reduce a current value of reset pulse which changes a chalcogenide semiconductor from crystal state to amorphous state and reloads a memory element from 'on' state to 'off' state by making an entire region of a semiconductor layer a current path. CONSTITUTION:A through-hole of a small diameter (1.5 to 0.1mum) which is smaller than a diameter (2 to 3mum) of a current path which is formed in a semiconductor layer of a conventional phase transition type memory element is provided to a layer insulating film which insulates a lower electrode and an upper electrode. A chalcogenide semiconductor layer is filled inside the through-hole. Thereby, an entire region of the semiconductor layer becomes a current path. According to the phase transition type memory element, a diameter of the through-hole, that is, a diameter of a semiconductor layer which is filled inside the through-hole is small and a volume of a current path (a volume of an entire of the semiconductor layer) is thereby small; therefore, it is possible to reduce a current value of reset pulse which changes the chalcogenide semiconductor from crystal state to amorphous state and reloads a memory element from 'on' state to 'off' state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase change memory element using a chalcogenide semiconductor and a method for manufacturing the same.

[Conventional technology]

Recently, phase change type memory elements using chalcogenide semiconductors have been developed as nonvolatile memory elements.

This phase change type memory element basically has a chalcogenide semiconductor layer interposed between a pair of electrodes, and conventional phase change type memory elements have a structure as shown in Figure 4. It has been known.

To explain the structure of this phase change type memory element, 1 in the figure is an insulating substrate made of a glass plate or the like, a lower electrode 2 and its line portion 2a are formed on this substrate 1, and further on this substrate 1. An interlayer insulating film 3 is formed to cover the lower electrode 2 and the line portion 2a. An opening 4 is formed in this insulating film 3 to expose a part of the lower electrode 2, and this opening 4 is generally formed to have a diameter of 5 μm to 10 μm. The chalcogenide semiconductor layer 5 is formed from within the opening 4 of the insulating film 3 to the upper surface of the surrounding insulating film, and is in contact with the upper surface of the lower electrode 2 at the lower surface of the portion inside the opening 4. Further, an upper electrode 6 is provided on the insulating film 3, covering the semiconductor layer 5.
is formed, and the upper surface of the semiconductor layer 5 is in contact with the upper electrode 6. Note that 6a is a line portion of the upper electrode 6.

This phase change memory element is rewritten into an on state and an off state by utilizing the phase transition of a chalcogenide semiconductor from an amorphous state to a crystalline state and from a crystalline state to an amorphous state. 0
．． A phase change memory element with a pulse width of 3μm has a pulse width of 30μm.
See~200μsec, application of set pulse with wave height 5v~IOV turns on state, pulse width 0.3μ
sec.

It is returned to the off state by applying a reset pulse with a current value of 100 mA. That is, when the set pulse is applied between the lower electrode 2 and the upper electrode 6, Joule heat is generated by the current flowing through the filament-shaped current bus A generated in the semiconductor layer 5 between the electrodes 2 and 6, and the semiconductor The current path A portion of the layer 5 undergoes a phase transition from an amorphous state to a crystalline state, the resistance value of the current bus A decreases, and the memory element turns on. Although the current bus A generated in the semiconductor layer 5 is shown in the center of the semiconductor layer 5 in FIG. 4, the current bus A is formed at a location in the semiconductor layer 5 where current most easily flows. Furthermore, after crystallizing a chalcogenide semiconductor, even if the applied voltage is lowered to eliminate Joule heat, the chalcogenide semiconductor does not return to the amorphous state, and therefore the ON state of the memory element remains unchanged. Further, when the reset pulse is applied between the electrodes 2 and 6, the current bus A portion of the semiconductor layer 5 is once melted, and then the heat is absorbed by the surrounding semiconductor layer 5 and rapidly cooled, and this current bus A portion is crystallized. The state returns to the amorphous state, the resistance value of the current bus A becomes high, and the memory element turns off. Further, readout is performed by applying a readout pulse to one of the electrodes 2 and 6 and reading the output of the other electrode, which changes depending on the on/off state of the memory element.

By the way, in this phase change type memory element, the diameter φ of the filament-shaped current bus A generated in the semiconductor layer 5 is about 2 μm to 3 μm, and the phase transition between the amorphous state and the crystalline state of the semiconductor layer 5 is caused by the current flow. This occurs only in the path A portion, but if the entire portion of the semiconductor layer 5 excluding the phase transition region (where the current bus A is formed) is in an amorphous state, then Since the portion always has a high resistance, there is almost no difference in the characteristics of the memory element no matter how large the area of the semiconductor layer 5 is. Therefore, in the conventional phase change memory element, the interlayer insulating film 3 that insulates between the electrodes 2.6 has a diameter of 5 μm.
An opening 4 having a size of 10 .mu.m is provided, and a semiconductor layer 5 is formed over this entire portion.

[Problem to be solved by the invention]

However, in the conventional phase change memory element, the diameter φ of the current bus A generated in the semiconductor layer 5 is 2 μm to 3 μm.
μm, and since the semiconductor in this current bus A portion undergoes a phase transition between a crystalline state and an amorphous state, the volume of this phase transition region is large, and therefore the phase transition region of the semiconductor layer 5 changes from a crystalline state to an amorphous state. A large current pulse (the thickness of the semiconductor layer 5 is O13 μm) is used as a reset pulse to return the memory element from the on state to the off state.
The problem was that 100 mA was required in the case of

In addition, in the conventional phase change memory element, the entire region of the semiconductor layer 5 excluding the phase change region must be in an amorphous state, so there are restrictions on the process temperature during manufacturing. I also had problems.

This is because the process temperature exceeds the crystallization temperature (temperature at which the phase changes from an amorphous state to a crystalline state) of the chalcogenide semiconductor (the temperature at which the phase transitions from an amorphous state to a crystalline state) occurs during the manufacturing process of a phase change memory element.
Moreover, if the semiconductor layer 5 is then slowly cooled, the entire semiconductor layer 5 will be crystallized. Note that even if the semiconductor layer 5 is crystallized, the semiconductor layer 5 can be returned to an amorphous state by melting and rapidly cooling it, but a large current pulse is required to return the entire semiconductor layer 5, which has a large area, to an amorphous state. (For example, if the width of the semiconductor layer 5 is 10 μm and the thickness of each layer is 0.3 μm, several 100 mA) must be applied between the electrodes 26, causing dielectric breakdown in the insulating film 3 that insulates between the electrodes 2. may occur.

For this reason, conventional phase change memory elements are manufactured at a process temperature that does not exceed the crystallization temperature Tc, but the crystallization temperature Tc of a chalcogenide semiconductor is 50°C, although it depends on the composition of this semiconductor. ~200°C, the degree of freedom in the manufacturing process is greatly restricted in order to keep the process temperature below this temperature. When forming thin film transistors constituting a circuit, the manufacturing process of the thin film transistors is also subject to temperature restrictions.

Further, the conventional phase change memory element has a semiconductor layer 5.
Since the area of the memory device is large, there is also the problem that it is not possible to reduce the area of the memory element and increase the degree of integration.

The present invention has been made in view of these circumstances, and its purpose is to provide a reset pulse current that changes a chalcogenide semiconductor from a crystalline state to an amorphous state and rewrites a memory element from an on state to an off state. We are developing a phase change memory element that can reduce the value, increase the degree of freedom in the manufacturing process by eliminating restrictions on process temperature during manufacturing, and also reduce the element area and increase the degree of integration. The object of the present invention is to provide a method for manufacturing the same.

[Means to solve the problem]

The phase change memory element of the present invention includes a lower electrode formed on an insulating substrate, an interlayer insulating film formed on the substrate covering the lower electrode, and a part of the lower electrode on the insulating film. a chalcogenide semiconductor layer filled in the through hole and in contact with the lower electrode at its lower end surface; and a chalcogenide semiconductor layer formed on the insulating film and partially in contact with the upper end surface of the semiconductor layer. and an upper electrode in contact with the through hole, and the diameter of the through hole is in the range of 1.5 μm to 0.1 μm.

Further, the method for manufacturing a phase change memory element of the present invention includes forming a lower electrode and an interlayer insulating film covering the lower electrode on an insulating substrate, and making the insulating film correspond to a part of the lower electrode. A step of forming a through hole with a diameter of 1.5 μm to 0.1 μm, depositing a chalcogenide semiconductor layer on the insulating film and in the through hole, and then removing the semiconductor layer on the insulating film by etching. The method is characterized by comprising a step of leaving a semiconductor layer only in the through hole, and a step of forming an upper electrode on the insulating film so as to cover the semiconductor layer in the through hole.

In this manufacturing method, after depositing a chalcogenide-based semiconductor layer on the insulating film and in its through-hole,
It is desirable to heat this semiconductor layer to a temperature equal to or higher than its melting point, and then remove the semiconductor layer on the insulating film by etching.

[Effect]

That is, the phase change type memory element of the present invention has a diameter (2 μm) of the current bus formed in the semiconductor layer in the conventional phase change type memory element, in the interlayer insulating film that insulates between the lower electrode and the upper electrode. ~3 μm) smaller diameter (1,5 μm)
By providing a through hole with a diameter of 0.1 μm) and filling this through hole with a chalcogenide semiconductor layer,
The entire area of this semiconductor layer serves as a current path, and according to this phase change memory element, the diameter of the through hole, that is, the diameter of the semiconductor layer filled in this through hole is small, and the Since the volume of the current path (volume of the entire semiconductor layer) is small, the current value of the reset pulse that changes the chalcogenide semiconductor from the crystalline state to the amorphous state and rewrites the memory element from the on state to the off state can be made small. In addition, in the present invention, the diameter of the through hole is in the range of 1.5 μm to 0.1 μm because
If the diameter of the through hole is made larger than 1.5 μm, the diameter of the semiconductor layer filled in the through hole becomes large, making it impossible to reduce the current value of the reset pulse very much. If it is smaller than 1 μm,
This is because the diameter of the semiconductor layer filled in this through hole becomes too small, making it impossible to obtain stable phase transition. In addition, in this phase change type memory element, the entire area of the semiconductor layer becomes a current path and the entire semiconductor layer undergoes a phase transition between an amorphous state and a crystalline state, so the initial state of the semiconductor layer may be either an amorphous state or a crystalline state. Therefore, since it does not matter if the process temperature exceeds the crystallization temperature of the semiconductor during the manufacturing process, there is no restriction on the process temperature during manufacturing, and the degree of freedom in the manufacturing process can be increased. Moreover, in this phase change type memory element, since the diameter of the semiconductor layer is reduced, the element area can also be reduced and the degree of integration can be increased.

Further, according to the method for manufacturing a phase change memory element of the present invention, the interlayer insulating film is made to correspond to a part of the lower electrode with a diameter of 1.5 mm.
After forming a through hole of μm to 0.1 μm and depositing a chalcogenide semiconductor layer on the insulating film and inside the through hole, the semiconductor layer on the insulating film is removed by etching, and only the inside of the through hole is etched. Since the semiconductor layer is left in the insulating film, it is possible to manufacture the phase change memory element in which the through hole of the insulating film is filled with the semiconductor layer.

In addition, in this manufacturing method, after depositing a chalcogenide semiconductor layer on the insulating film and in its through-hole, if this semiconductor layer is heated to a temperature equal to or higher than its melting point, the through-hole during deposition of the semiconductor layer can be heated. Even if the filling of the semiconductor inside is incomplete, the semiconductor layer becomes fluid due to heating and the semiconductor on the insulating film flows into the through hole. A dense filmy semiconductor layer can be formed within the hole.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view of the phase change type memory element of this embodiment, in which a lower electrode 12 and its line portion 12a are formed on an insulating substrate 11 made of a glass plate or the like, and further on this substrate 11. is the lower electrode 12 and the line part 1
Interlayer insulation 1i13 covering 2a is 0.1 μm to 0.5 μm
It is formed to a thickness of . This interlayer insulating film 13 includes a first insulating film 13a that covers almost the entire surface of the substrate, in which a circular opening 14 with a diameter of approximately 2 μm to 5 μm is formed in a portion corresponding to the lower electrode 12; A second insulating film 13b is formed in the opening 14 to have the same thickness as the first insulating film 13a, and a diameter a of 1.5 μm to 0.0 μm is formed at the center of the second insulating film 13b. A substantially circular through hole 15 with a diameter of .1 μm is formed. And this through hole 15
A chalcogenide semiconductor layer 16 is densely filled inside, and this semiconductor layer 16 is in contact with the lower electrode 12 at its lower end surface. Note that chalcogenide semiconductors include, for example, Ge-Te, In-5e, and Sb.
There are semiconductors with various compositions such as -Ge-Te, and these semiconductors are used in this embodiment. Further, an upper electrode 17 is formed on the interlayer insulating film 13 to cover the semiconductor layer 16 filled in the through hole 15, and the upper surface of the semiconductor layer 16 is in contact with the upper electrode 17. . Note that 17a is a line portion of the upper electrode 17.

FIG. 2 is a manufacturing process diagram of the phase change type memory element,
This phase change type memory element is manufactured as follows.

First, as shown in FIG. 2(a), a metal film such as Cr is deposited on the substrate 11, and this metal film is patterned by photolithography to form the lower electrode 12 and its line portion 1.
Form 2a.

Next, as shown in FIG. 2(b), a first insulating film 13a such as SIN or 510□ is deposited over the entire surface of the substrate 11 to a thickness of 0.1 μm to 0.5 μm.

Next, as shown in FIG. 2(C), the first insulating film 1
A circular opening 14 having a diameter of approximately 2 μm to 5 μm is formed in a portion corresponding to the lower electrode 12 of 3H by photolithography.

Next, as shown in FIG. 2(d), the first insulating film 13a is
A second insulating film 13b is deposited on the opening 14, the wall surface of the opening 14, and the lower electrode 12 exposed in the opening 14. Note that the second insulating film 13b may be made of any material, but for example, it may be made of the same insulating material as the first insulating film 13a (St
N or 8102, etc.). This second insulating film 13
The deposition thickness b is controlled to a thickness that leaves a vertical hole portion 15' having a diameter corresponding to the diameter a of the through hole 15 filled with the chalcogenide semiconductor in the center of the opening 14.

Further, the second insulating film 13b is deposited by CVD. In the deposition of the film by this CVD method, the raw material gas undergoes a chemical reaction on the surface of the film deposition surface and grows as a film. It is deposited on both the upper surface and the wall surface of the opening 14 in a direction perpendicular to these surfaces to a uniform film thickness d.

Next, as shown in FIG. 2(e), the second insulating film 1
3b is etched back under etching conditions such that etching proceeds in a direction perpendicular to the surface of the substrate 11 until the upper surfaces of the first insulating film 13a and the lower electrode 12 are exposed. The etching back of this second insulating film 13b is R
This is done by anisotropic etching such as IE method or sputter etching method. When the second insulating film 13b is etched back by anisotropic etching in this way, the first insulating film 13b! The portion deposited on the upper surface of I 13a and the bottom portion of the vertical hole 15' are etched away, and finally, only the insulating film 13b deposited on the wall surface of the opening 14 remains, and the vertical hole 15' is removed by etching. This becomes a through hole 15 that reaches the electrode 12. Note that the through hole 4
The diameter a is -a+wl)-2Xd, and for example, the opening 1 formed in the first insulating film 13a by photolithography
If the diameter of the through hole 4 is 3 μm, and the thickness d of the second insulating film 13b left on the wall of the opening 14 is 1.45 μm, the diameter a of the through hole 4 is a-3-2X1.45 μm-0, 1
It becomes μm.

After forming the interlayer insulating film 13 consisting of the first insulating film 13a and the second insulating film 13b having the through holes 15 in this way, as shown in FIG. A chalcogenide semiconductor layer 16 is deposited on the film 13 and in the through hole 15 thereof by CVD or the like, and the through hole 15 is filled with the semiconductor layer 16 .

However, in this case, if the aspect ratio of the through hole 15, that is, the ratio of the hole height (thickness of the interlayer insulating film 13) h to the hole diameter a (h/a) is about 1 or more, The deposited semiconductor layer 16 may not completely fill the through hole 15, and holes S as shown in FIG. 2(f) may be formed in the semiconductor layer 16.

Therefore, in this embodiment, after depositing a chalcogenide semiconductor layer 16 on the interlayer insulating film 13 and in its through hole 15, this semiconductor layer 16 is heated (reflowed) to a temperature higher than its melting point, and the semiconductor layer 16 is The hole 15 is completely filled with semiconductor.

FIG. 2(g) shows this state, and if the deposited semiconductor layer 16 is heated to a temperature higher than its melting point, the through hole 15 will not be filled with semiconductor completely during the deposition of the semiconductor layer 16. Even in this case, the semiconductor layer 16 becomes fluid due to heating and the semiconductor on the insulating film 13 flows into the through hole 15, so the through hole is completely filled with the semiconductor and a dense film is formed inside the through hole. It is possible to form a semiconductor layer of. In addition,
In this case, when the semiconductor layer 16 is slowly cooled after heating, the semiconductor layer 16 becomes a crystalline state, and when rapidly cooled, the semiconductor layer 16 becomes an amorphous state. or quenching.

After this, as shown in FIG. 2(h), the interlayer insulating film 13
The upper semiconductor layer 16 is etched away to form the through hole 15.
The semiconductor layer 16 is left only inside.

Next, as shown in FIG. 2(i), the interlayer insulating film 13
A metal film such as Cr is deposited thereon, and this metal film is patterned by photolithography to form the through holes 15.
The lower electrode 17 covering the semiconductor layer 16 inside and its line portion 1
7a is formed to complete a phase change type memory element.

That is, the phase change memory element of this embodiment has an interlayer insulating film 13 that insulates between the lower electrode 12 and the upper electrode 17.
A through hole 15 with a diameter a of 1.5 μm to 0.1 μm is provided in the device, and a chalcogenide semiconductor layer 16 is filled in the through hole 15. 16 (diameter a of the through hole 15) is smaller than the diameter (2 μm to 3 μm) of the current bus formed in the semiconductor layer in a conventional phase change memory element, so the entire area of the semiconductor layer 16 is used as the current bus. Become.

According to this phase change memory element, the semiconductor layer 1
6 is small in diameter and therefore the volume of the current bus (volume of the entire semiconductor layer 16) is small, so the current value of the reset pulse that changes the chalcogenide semiconductor from the crystalline state to the amorphous state and rewrites the memory element from the on state to the off state is can be made smaller.

That is, the table below shows the thickness of the semiconductor layer 16 (through hole 1
5 shows the relationship between the diameter of the semiconductor layer 16 and the current value of the reset pulse required to phase transition the semiconductor layer 16 from the crystalline state to the amorphous state, when the diameter of the semiconductor layer 16 is set to 0.3 μm. .

As shown in Table 2, when the diameter of the semiconductor layer 16 is approximately the same as the diameter (2 μm) of the current bus formed in the semiconductor layer in a conventional phase change memory element, the semiconductor layer 16
The current value of the reset pulse required to cause a phase transition from a crystalline state to an amorphous state is 100 mA, which is almost the same as that of a conventional phase change type memory element, but if the diameter of the semiconductor layer 16 is 1.5 μm, The current value of the reset pulse is 56.3 mA, which is about 1/2 of that of a conventional phase change memory element, and if the diameter of the semiconductor layer 16 is further reduced, the current value of the reset pulse can be even smaller.

In this embodiment, the diameter a of the through hole 15 is set in the range of 1.5 μm to 0.1 μm, because if the diameter a of the through hole 15 is larger than 1.5 μm, the inside of the through hole 15 will be filled. If the diameter of the semiconductor layer 16 becomes large and the current value of the reset pulse cannot be made very small, and if the diameter of the through hole 15 is made smaller than 0.1 μm, the semiconductor layer filled in the through hole 15 becomes larger. 1
This is because the diameter of 6 becomes too small and stable phase transition cannot be obtained.

In addition, in this phase change type memory element, the entire area of the semiconductor layer 16 becomes a current bus, and the entire semiconductor layer undergoes a phase transition between an amorphous state and a crystalline state. Therefore, since the process temperature may exceed the crystallization temperature of the semiconductor 16 during the manufacturing process, there is no restriction on the process temperature during manufacturing, and the degree of freedom in the manufacturing process can be increased. Therefore, for example, even when phase change memory elements are arranged in a matrix on the same substrate 11 and thin film transistors constituting the drive circuit are formed, the manufacturing process of the thin film transistors is not subject to temperature restrictions.

Moreover, in this phase change type memory element, since the diameter of the semiconductor layer 16 is made small, the element area can also be made small and the degree of integration can be increased.

Further, in the method for manufacturing a phase change memory element according to the embodiment, a through hole 14 having a diameter of 1.5 μm to 0.1 μm is formed in the interlayer insulating film 13 in correspondence with a part of the lower electrode 12, and the insulating film After the chalcogenide semiconductor layer 16 is deposited on the insulating film 13 and in the through hole 15, the semiconductor layer 16 on the insulating film 13 is removed by etching, leaving the semiconductor layer 16 only in the through hole 15. , it is possible to manufacture the phase change memory element in which the through hole 15 of the insulating film 13 is filled with the semiconductor layer 16.

Moreover, in this manufacturing method, the through hole 15 provided in the interlayer insulating film 13 is formed by first forming the first insulating film 13a, forming the opening 14 in the first insulating film 13a, and forming the through hole 15 on the wall surface of the opening 14. By controlling the deposition thickness of the second insulating film 13b, a very small through hole 15 with a diameter a of 1.5 μm to 0.1 μm can be formed. can be formed.

Further, in the manufacturing method of the embodiment, a chalcogenide semiconductor layer 1 is formed on the insulating film 13 and in the through hole 14 thereof.
After depositing the semiconductor layer 16, the semiconductor layer 16 is heated to a temperature higher than its melting point.
The semiconductor layer 16 is heated to a fluidized state, and the semiconductor on the insulating film 13 flows into the through hole 15, completely filling the through hole 15 with the semiconductor and forming a dense film semiconductor layer 16 in the through hole 15. can be formed.

In the above embodiment, the through hole 15 provided in the interlayer insulating film 13 is formed by depositing the second insulating film 13b on the wall surface of the opening 14 formed in the first insulating film 13a. The through hole 15 may be formed by photolithography, and even with the current photolithography technology, 1
It is possible to form through-holes with diameters slightly smaller than μm.

FIG. 3 shows an embodiment of a phase change memory element in which a through hole 15 is formed by photolithography. The through hole 15 is formed by a lithography method.

Further, in the manufacturing method of the embodiment, a chalcogenide semiconductor layer 1 is formed on the interlayer insulating film 13 and in the through hole 14 thereof.
After depositing the semiconductor layer 16, the semiconductor layer 16 is heated to a temperature higher than its melting point, and the semiconductor on the insulating film 13 flows into the through hole 15.
When the film thickness h of the through hole 15 is smaller than the hole diameter a of the through hole 15 and the aspect ratio (h/a) is smaller than 1, the semiconductor layer -16
Since the through hole 15 is completely filled with the semiconductor layer 16 during deposition, the heating step may be omitted in this case.

〔Effect of the invention〕

The phase change memory element of the present invention has an interlayer insulating film that insulates between the lower electrode and the upper electrode.
2 μm to 3 μm) smaller diameter (1,5 μm to 0.1
By providing a through hole with a diameter of μm) and filling this through hole with a chalcogenide semiconductor layer, the entire area of this semiconductor layer becomes a current path. It is possible to reduce the current value of the reset pulse that changes the memory element from an on state to an off state by setting it in an amorphous state, and the entire semiconductor layer becomes a current path, so that the entire semiconductor layer can be switched between an amorphous state and a crystalline state. Since the initial state of the semiconductor layer can be either an amorphous state or a crystalline state, there is no restriction on process temperature during manufacturing, increasing the flexibility of the manufacturing process. In the device, since the diameter of the semiconductor layer is made small, the device area can also be made small and the degree of integration can be increased.

Further, according to the method for manufacturing a phase change memory element of the present invention, the interlayer insulating film is made to correspond to a part of the lower electrode with a diameter of 1.5 mm.
After forming a through hole of μm to 0.1 μm and depositing a chalcogenide-based semiconductor layer on the insulating film and inside the through hole, the semiconductor layer on the insulating film is removed by etching and only the inside of the through hole is etched. Since the semiconductor layer is left in the insulating film, it is possible to manufacture the phase change memory element in which the semiconductor layer is filled in the through hole of the insulating film.

In addition, in this manufacturing method, after depositing a chalcogenide semiconductor layer on the insulating film and in its through-hole, if this semiconductor layer is heated to a temperature equal to or higher than its melting point, the through-hole during deposition of the semiconductor layer can be heated. Even if the filling of the semiconductor inside is incomplete, the semiconductor layer becomes fluid due to heating and the semiconductor on the insulating film flows into the through hole. A dense filmy semiconductor layer can be formed within the hole.

[Brief explanation of drawings]

FIGS. 1 and 2 are cross-sectional views of a phase change memory element showing one embodiment of the present invention and a diagram of its manufacturing process, and FIG. 3 is a cross-sectional view of a phase change memory element showing another embodiment of the present invention. figure,
FIG. 4 is a cross-sectional view of a conventional phase change type memory element. DESCRIPTION OF SYMBOLS 11... Substrate, 12... Lower electrode, 13... Interlayer insulating film, 13a... First insulating film, 13b... Second
insulating film, 14... opening, 15... through hole, 15.
... Chalcogenide semiconductor layer, 17... Upper electrode.

Claims (3)

[Claims] (1) A lower electrode formed on an insulating substrate, an interlayer insulating film formed on the substrate to cover this lower electrode, and an interlayer insulating film provided on this insulating film to correspond to a part of the lower electrode. It consists of a through hole, a chalcogenide-based semiconductor layer filled in the through hole and in contact with the lower electrode at its lower end surface, and an upper electrode formed on the insulating film and partially in contact with the upper end surface of the semiconductor layer. , and a diameter of the through hole is in the range of 1.5 μm to 0.1 μm. (2) A lower electrode and an interlayer insulating film covering the lower electrode are formed on an insulating substrate, and a through hole with a diameter of 1.5 μm to 0.1 μm is formed in this insulating film to correspond to a part of the lower electrode. a step of depositing a chalcogenide-based semiconductor layer on the insulating film and in the through hole thereof, and then etching away the semiconductor layer on the insulating film to leave the semiconductor layer only in the through hole; A method for manufacturing a phase change memory element, comprising the step of forming an upper electrode on the insulating film so as to cover the semiconductor layer in the through hole. (3) After depositing a chalcogenide-based semiconductor layer on the insulating film and in its through-hole, heating this semiconductor layer to a temperature equal to or higher than its melting point, and then etching away the semiconductor layer on the insulating film. 3. The method for manufacturing a phase change memory element according to claim 2.