US20130284998A1

US20130284998A1 - Forming heaters for phase change memories

Info

Publication number: US20130284998A1
Application number: US13/863,253
Authority: US
Inventors: Carla Maria Lazzari; Silvia Borsari
Original assignee: Micron Technology Inc
Current assignee: US Bank NA
Priority date: 2010-11-11
Filing date: 2013-04-15
Publication date: 2013-10-31
Also published as: US8420171B2; US20120121864A1

Abstract

A heater for a phase change memory may be thrilled by depositing a first material into a trench such that the material is thicker on the side wall than on the bottom of the trench. In one embodiment, because the trench side walls are of a different material than the bottom, differential deposition occurs. Then a heater material is deposited thereover. The heater material may react with the first material at the bottom of the trench to make Ohmic contact with an underlying metal layer. As a result, a vertical heater may be formed which is capable of making a small area contact with an overlying chalcogenide material.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a divisional of pending U.S. patent application Ser. No. 12/944,134, filed Nov. 11, 2010, which application is incorporated herein by reference, in its entirety, for any purpose.

BACKGROUND

This relates generally to phase change memories. Phase change memories use a chalcogenide layer that changes phase between more amorphous and less amorphous or more crystalline phases. Generally, the phase transition is the result of Joule heating of the chalcogenide layer. In sonic cases, the heating of the chalcogenide layer is due to electrical heating through a heating element proximate to the phase change material layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an enlarged, partial, cross-sectional view alone embodiment of the present invention at an early stage;

FIG. 2 is an enlarged, cross-sectional view at a subsequent stage according to one embodiment;

FIG. 3 is an enlarged, cross-sectional view at still a subsequent stage in accordance with one embodiment;

FIG. 4 is an enlarged, cross-sectional view at a subsequent stage in accordance with one embodiment;

FIG. 5 is an enlarged, cross-sectional view at a subsequent stage according to one embodiment; and

FIG. 6 is an enlarged, cross-sectional view at a subsequent stage according to one embodiment.

DETAILED DESCRIPTION

In accordance with some embodiments, differential deposition can be used to form vertical high aspect ratio heaters for phase change memories. The vertical heaters may be more effective because they have a smaller point of contact with the chalcogenide material, that point of contact determined h the thickness in the horizontal dimension of the phase change material heater, which is deposited as a layer in the vertical direction.
Therefore, the heater can have a critical dimension thinner than any thickness possible with lithographic techniques. As a result of the thin area of contact between the heater and the phase change material layer, less material in the phase change layer must be required to change phase and, therefore, less energy is needed to make the phase transition. As a result, power consumption may be improved in some embodiments.
Referring to FIG. 1, in some embodiments, a vertical wall dielectric 14 may be formed. In some cases, the dielectric 14 may be formed with a trench, Figure I only showing the left side of a trench. The dielectric 14, in one embodiment, may be stacked oxide and nitride layers. However, any dielectric may be utilized. The dielectric 14 is formed on top of a metal layer 12 which acts as to conductor lower electrode, or address line.
In some embodiments, a deposition technique is used to form a layer composed of a thicker vertical portion 16 on the dielectric 14 and a thinner horizontal portion 18 on the metal 12. The difference in deposition thickness is the result of the differential deposition that occurs on metal, compared to dielectric materials. Specifically, with some deposition processes, such as atomic layer deposition, more material is deposited on dielectrics than on metals. For example, in a flow of boron B₂H₆, the boron is well physisorbed on an oxide/nitride layer 14 and less effectively physisorbed on metals, resulting in differential thicknesses. Another technique that can be utilized is SiH₄deposition, however, the film performance may not be as good as that achieved with boron.
Next, a heater material 20 is deposited, as indicated in FIG. 2, using a deposition technique, such as atomic layer deposition. For example, the atomic layer deposition of tungsten may he used to form the heater material 20 which has a vertical portion and a horizontal portion 22. However, the horizontal portion 18 on the metal 12 is consumed during the heater material 20 deposition process As a result, physical contact is achieved between the heater material 20 and the metal 12. Next, to second boron layer may be deposited, again, using B₂H₆flow, in one embodiment, to form the capping layer 24, as shown in FIG. 3. Again, atomic layer deposition may be used, for example.
More specifically, the reason for the consumption of the baron forming the horizontal portion 18 at the bottom of the trench is that tungsten fluoride (WF₆) reacts with any boron at the metal surface, achieving Ohmic contact to the metal surface, Good adhesion between the tungsten based layer and the dielectric 14 is guaranteed by the residual of boron deposited on the dielectric and still remaining on the dielectric 14. The second B₂H₆atomic layer caps the in situ heater material 20.
Next as shown in FIG. 4, a dielectric layer 26 is blanket deposited over the structure and then planarized down to the upper surface 28 of the dielectric 14, as shown in FIG. 5,
Finally, a chalcogenide layer 30 is deposited, as indicated in FIG. 6. The vertical heater material 20 makes a small area or point contact with the chalcogenide layer 30. Thereafter, the chalcogenide layer may be covered with additional layers, including another electrode or metal layer (not shown). Then, additional layers (also not shown may be deposited, such as the layers forming an ovonic threshold switch, as one example. In some embodiments, the surface area of contact between the vertically oriented heater material 20 and the chalcogenide layer 30 is governed by the thickness of the deposition of the heater material 20. Using atomic layer deposition, this layer can be made extremely is small, resulting in a very small area of contact between the chalcogenide layer 30 and the heater material 20.
While the figures depict the formation of the single cell, a large number of cells may be formed at the same time, for example, by forming a plurality of spaced trenches in a dielectric 14. Then, in each trench, the layers shown in FIGS. 1-6 may be deposited and processed in the fashion indicated. As a result, a number of cells may be formed, initially, with a common chalcogenide layer 30. In some embodiments, the chalcogenide layer may then be singulated so that the chalcogenide layer is no longer continuous across the plurality of cells, but is distinct and constitutes a dot at each cell. Thus, a plurality of cells may be formed along a line, defined by the metal 12 and perpendicular lines may be defined by conductors extending transversely to the length of the metal 12, contacting the upper surface of the chalcogenide 30 after it has been singulated.
Programming to alter the state or phase of the material may be accomplished by applying voltage potentials to the address lines, thereby generating a voltage potential across a memory element including a phase change layer 30. When the voltage potential is greater than the threshold voltages of any select device and memory element, then an electrical current may flow through the phase change layer 30 in response to the applied voltage potentials, and may result in heating of the phase change layer 30 through the action of the heater 20.
This heating may alter the memory state or phase of the layer 30, in one embodiment. Altering the phase or state of the layer 30 may alter the electrical characteristic of memory material, e.g., the resistance or threshold voltage of the material may be altered by altering the phase of the memory material. Memory material may also be referred to as a programmable resistance material.
In the “reset” state, memory material may be in an amorphous or semi-amorphous state and in the “set” state, memory material may be in a crystalline or semi-crystalline state. The resistance of memory material in the amorphous or semi-amorphous state may be greater than the resistance of memory material in the crystalline or semi-crystalline state. It is to be appreciated that the association of reset and set with amorphous and crystal line states, respectively, is a convention and that at least an opposite convention may be adopted. Using electrical current, memory material may be heated to a relatively higher temperature to melt and then quenched to vitrify and “reset” memory material in an amorphous state (e.g., program memory material to a logic “0” value). Heating the volume of memory material to a relatively lower crystallization temperature may crystallize or devitrify memory material and “set” memory material (e.g., program memory material to a logic “1” value). Various resistances of memory material may be achieved to store information by varying the amount of current flow and duration through the volume of memory material.
References throughout this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims

What is claimed is:

1. An apparatus comprising:

a substrate;

a vertical wall defined over the substrate:

a material formed on the vertical wall; and

a heater material including a horizontal portion formed in contact with the substrate and a vertical portion formed in contact with the material.

2. The apparatus of claim 1, wherein the substrate is formed of metal and the vertical wall is formed in a dielectric.

3. The apparatus of claim 2, further comprising a layer of the material formed over the heater material.

4. The apparatus of claim 1, wherein the material includes boron.

5. An apparatus comprising:

a metal material;

a heater including a horizontal portion formed adjacent to the metal material and a vertical portion formed between two columns of a material, wherein the vertical portion of the heater contacts the material of the two columns.

6. The apparatus of claim 5, wherein the material comprises boron.

7. The apparatus of claim 5, farther comprising a phase change material defined over the vertical portion and the two columns of the material.

8. The apparatus of claim 7, wherein the phase change material comprises a chalcogenide material.

9. The apparatus of claim 7, wherein the phase change material has a first resistance in a first state and a second resistance in at second state.

10. The apparatus of claim 5, wherein the metal material is coupled to a address line.

11. An apparatus comprising:

a plurality of phase change memory (PCM) cells, wherein a PCM cell of the plurality of PCM cells comprises a substrate, a heater, and a chalocogenide material, wherein a first portion of the heater contacts the substrate and a second portion of the heater contacts the chalcogenide material, wherein the second portion of the beater is formed between a first layer of a first material and a second layer of a second material, wherein the second portion of the heater contacts the first layer and the second layer, wherein the first material and the second material each comprise boron.

12. The apparatus of claim 11, wherein the first material is the same material as the second material.

13. The apparatus of claim 11, wherein each PCM cell of the plurality of PCM cells comprises a dot of the chalcogenide material.

14. The apparatus of claim 13, wherein a first subset of the plurality of PCM cells comprises the substrate, wherein the first subset of the plurality of PCM cells forms a line defined by the substrate.

15. The apparatus of claim 14, wherein the substrate comprises a first conductive line.

16. The apparatus of claim 15, wherein the dot of the chalcogenide material is coupled to a second conductive line that extends transversely to a length of the first conductive line, wherein a second subset of the plurality of PCM cells forms a line defined by the second conductive line that is perpendicular to the first conductive line.

17. The apparatus of claim 16, wherein the first conductive line and the second conductive line each comprise a metallic material.

18. The apparatus of claim 11, wherein the chalcogenide material of the PCM cell is configured to have a first resistance in a first state and a second resistance in the second state.

19. The apparatus of claim 11, wherein the first layer contacts a dielectric material.

20. A memory cell comprising:

a heater between a metal material and a phase-change material, wherein the heater comprises a vertical portion and a horizontal portion, wherein the horizontal portion of the heater is in physical contact with the metal material, and wherein a layer of a material is between the vertical portion of the heater and a vertical wall.

21. The memory cell of claim 20 wherein as contact between the horizontal portion of the heater and the metal material is devoid of the material.

22. The memory cell of claim 20, wherein the material includes boron.

23. The memory cell of claim 20, further comprising a capping layer of a second material, wherein the vertical portion of the heater is between the layer of the material and the capping layer of the second material.

24. The memory cell of claim 23, wherein the vertical portion of the heater contacts the layer of the material and contacts the capping layer of the second material.

25. The memory cell of claim 23, wherein the material and the second material each include boron.