JPH0445016B2 - - Google Patents
Info
- Publication number
- JPH0445016B2 JPH0445016B2 JP62182446A JP18244687A JPH0445016B2 JP H0445016 B2 JPH0445016 B2 JP H0445016B2 JP 62182446 A JP62182446 A JP 62182446A JP 18244687 A JP18244687 A JP 18244687A JP H0445016 B2 JPH0445016 B2 JP H0445016B2
- Authority
- JP
- Japan
- Prior art keywords
- stage
- mrc
- remainder
- input
- rom
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/14—Conversion to or from non-weighted codes
- H03M7/18—Conversion to or from residue codes
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/729—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using representation by a residue number system
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Quality & Reliability (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Detection And Correction Of Errors (AREA)
- Error Detection And Correction (AREA)
- Read Only Memory (AREA)
- Advance Control (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/890,252 US4752904A (en) | 1986-07-28 | 1986-07-28 | Efficient structure for computing mixed-radix projections from residue number systems |
| US890252 | 1986-07-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6336614A JPS6336614A (ja) | 1988-02-17 |
| JPH0445016B2 true JPH0445016B2 (enExample) | 1992-07-23 |
Family
ID=25396456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62182446A Granted JPS6336614A (ja) | 1986-07-28 | 1987-07-23 | 剰余数表現のデ−タを混合基数射影デ−タに変換する装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4752904A (enExample) |
| EP (1) | EP0254821A3 (enExample) |
| JP (1) | JPS6336614A (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1318027C (en) * | 1987-10-12 | 1993-05-18 | Jun Takayama | Method and apparatus for encoding and decoding data in residue number system |
| US4924467A (en) * | 1988-08-24 | 1990-05-08 | Unisys Corporation | System for checking duplicate logic using complementary residue codes to achieve high error coverage with a minimum of interface signals |
| US5081629A (en) * | 1989-05-08 | 1992-01-14 | Unisys Corporation | Fault isolation for multiphase clock signals supplied to dual modules which are checked by comparison using residue code generators |
| US5050120A (en) * | 1989-09-29 | 1991-09-17 | The Boeing Company | Residue addition overflow detection processor |
| US4996527A (en) * | 1989-09-29 | 1991-02-26 | The Boeing Company | Pipelined residue to mixed base converter and base extension processor |
| US4963869A (en) * | 1989-09-29 | 1990-10-16 | The Boeing Company | Parallel residue to mixed base converter |
| EP2438511B1 (en) | 2010-03-22 | 2019-07-03 | LRDC Systems, LLC | A method of identifying and protecting the integrity of a set of source data |
| US11755288B2 (en) * | 2016-11-08 | 2023-09-12 | Koninklijke Philips N.V. | Secure transformation from a residue number system to a radix representation |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4107783A (en) * | 1977-02-02 | 1978-08-15 | The Board Of Trustees Of The Leland Stanford Junior University | System for processing arithmetic information using residue arithmetic |
| US4281391A (en) * | 1979-01-15 | 1981-07-28 | Leland Stanford Junior University | Number theoretic processor |
| US4458327A (en) * | 1979-06-28 | 1984-07-03 | John Larson | Prime or relatively prime radix data processing system |
| US4418394A (en) * | 1980-08-13 | 1983-11-29 | Environmental Research Institute Of Michigan | Optical residue arithmetic computer having programmable computation module |
| US4537502A (en) * | 1982-09-30 | 1985-08-27 | The Boeing Company | Multiple discrete frequency ranging with error detection and correction |
-
1986
- 1986-07-28 US US06/890,252 patent/US4752904A/en not_active Expired - Lifetime
-
1987
- 1987-05-05 EP EP87106474A patent/EP0254821A3/en not_active Withdrawn
- 1987-07-23 JP JP62182446A patent/JPS6336614A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6336614A (ja) | 1988-02-17 |
| EP0254821A3 (en) | 1990-04-25 |
| US4752904A (en) | 1988-06-21 |
| EP0254821A2 (en) | 1988-02-03 |
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