JPH0444971B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an address conversion circuit, and particularly to an address conversion circuit for performing address emulation between models having different numbers of address bits.

[Background of the invention]

When a new computer is developed and replaced with an old model, an emulation machine is used to inherit the programs developed and used on the old model. There are various emulation methods, ranging from those that fully use hardware such as microprograms to those that use a combination of hardware and software. When emulation is performed using hardware, it is necessary to switch between a native mode in which the new machine, ie, the host computer, operates as it should, and an emulation mode, in which the old model machine, ie, the target computer, operates. For example, if an older machine uses 16-bit addresses and a newer machine uses 24-bit addresses, the 16-bit word address must be converted to a 24-bit byte address, and when used for either , the address conversion circuit is switched and used. As shown in Figure 3a, the 24-bit address space exists at addresses 0 to ²²⁴ , and the 16-bit address space is included as part of the 24-bit address space, so the emulation mode is indicated by diagonal lines. Limited to a range. When specifying a range for this emulation mode by the emulation mode program counter (PCEM), the number of address bits used is 24 bits instead of 16 bits, since it is part of a 24-bit address space. Bit address is required.

Conventionally, in the address conversion method described in Japanese Patent Application Laid-Open No. 57-161941, as shown in FIG. ing. In other words, when two 24-bit program counters are installed, one for emulation (PCEM) and one for native (PCNT), and the output of the flip-flop for mode switching is set to emulation mode (EMOD),
The contents of the PCEM counter are output to the address bus, and when the flip-flop output is in native mode, the contents of the PCNT counter are output to the address bus.

Furthermore, in the address conversion method described in Japanese Patent Application Laid-Open No. 57-105043, as shown in FIG. Addresses are converted by concatenation. In other words, the 24-bit program counter for native mode is divided into the upper 8 bits and lower 16 bits.
It is divided into bits, and the contents of the lower bits are shared even in emulation mode. In emulation mode, a value is set in an 8-bit register for the extension bits, and this specifies which part of the emulation address space is divided into 16 bits.

FIG. 4 is a block diagram showing the address control section of FIG. 3c in more detail. In Figure 4, 1
is the base address register that sets the emulation mode extension bits, 2 is the native mode program address register divided into upper and lower bits, 3 is the operand address register divided into upper and lower bits, and 4 is the next 8 is an adder that increments against the previous address to specify the address of register 1, 2,
A selection circuit selects one of the outputs of 3, and c and d are upper and lower address buses. Note that in the case of the base register in Figure 4, if a carry occurs in the lower address relative to the upper address due to updating of the address field, the emulation target page shown in Figure 3a will be removed and emulation will not be possible. This is necessary to prevent it from running out. First, in the native mode, the value of the program address register 2 is incremented by 1 by the adder 4 and the lower bits are output to the lower address bus d, and the upper bits are selected by the selection circuit 8 and output to the upper address bus c. . Next, in order to read the operand from the main memory, a value is set in the operand address register 3, the lower bits are output to the address bus d, and the upper bits are selected by the selection circuit 8 and output to the address bus c. In addition, in the emulation mode, only the lower bits are set in the program address register 2, this is incremented by 1 by the adder 4, and then outputted to the address bus d, and the extension bits are set in the base address register 1. This is selected by the selection circuit 8 and output to the address bus c. For operand addresses, same as before. In this manner, address conversion is performed by switching the base address portion of the calculation result using the selection circuit 8. In this way, in the conventional address translation circuit,
Both require dedicated hardware registers, which increases costs and increases the size of the device.

[Purpose of the invention]

An object of the present invention is to improve such conventional problems and to provide an address conversion circuit that can perform address conversion to emulation mode without providing a dedicated hardware register for storing address bits for conversion. Our goal is to provide the following.

[Summary of the invention]

In order to achieve the above object, the address conversion circuit of the present invention includes a program counter that indicates an instruction word address, and an operand address that indicates the address of an operand required to execute the instruction word read by the program counter. In a main memory address control circuit equipped with a register,
Each has a program counter and an operand address register divided into two fields, a base part and a displacement part. In emulation mode, the displacement part output of the program counter and the base part output of the operand address register are connected. , the main memory is accessed as the instruction word address, and only the displaced portion of the operand address register is updated as the operand address.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 2 is a diagram for explaining the operating principle of the present invention. In a computer using program storage, the instructions of the program stored in the storage device are retrieved one by one, decoded, and the operations of each instruction are executed repeatedly to proceed with the processing instructed by the program. . That is, looking at each instruction one by one, as shown in Figure 2, after reading the instruction (step 10), it is determined whether or not this instruction requires an operand (step 11). If the instruction requires an operand, read the operand from the storage device (step 12), decode the operation part (OP part) of the instruction, branch to each instruction (step 13), and execute the operation of each instruction. (steps 14-16). When the execution of the command operation is completed, the process returns to step 10 and the next command is read. Computer processing proceeds in this order, but in conventional address conversion circuits, as shown in Figure 4, an address is divided into a base part and a displacement part, and when converting an address, the contents of the base part are replaced. By doing, I was going. However, the second
For the address when reading the instruction shown in the figure, only the lower bits and the value of the base address register 1 are set in the program address register 2 of FIG. 4, and the operand address register 3 is not used. In FIG. 2, when it is determined that an operand is necessary, an address value is set in the operand address register 3 in order to read the operand. In the present invention, in order to reduce redundant hardware, we focused on the fact that the operand address register 3 can double as the base address register 1 in FIG. 4 by using hardware that is not used when reading instructions. Also, if base address register 1 is removed and the instruction read operation and operand read operation are performed at different times, the fourth
We focused on the fact that the selection circuit 8 shown in the figure is also unnecessary. That is, in the present invention, the address register itself is divided into a base part and a displacement part, and only the displacement part is updated during address translation mode, and the base part is set in the base part of the operand address register.

FIG. 1 is a block diagram of an address conversion circuit showing one embodiment of the present invention. In Figure 1,
As is clear from a comparison with FIG. 4, the base address register 1 and selection circuit 8 in FIG. 4 are removed, the native mode and emulation mode are switched by the flip-flop output j, and the The difference is that the output of 7 and the output of operand address register 6 are directly connected to the address bus.

In FIG. 1, 5 is a program counter, 6
is an operand address register, 7 is an arithmetic unit for incrementing or decrementing the program counter, j is an operation mode signal for mode switching,
e is the base address input signal of the instruction or operand, f is the displacement address input signal of the instruction or operand, g is the upper bit line of the address bus, and h is the lower bit line of the address bus. First, in the native mode, since the operation mode signal j is "0", the setting to the operand address register 6 and the output of the arithmetic unit 7 are not prohibited. Therefore, the base address of the operand is set, and the operation The base address part of the device 7 is also connected to the address bus g and output freely. In this case, a base address input signal e and a displacement address input signal f are stored in the program counter 5 and connected to the arithmetic unit 7 for instruction reading. All the addresses of the calculation results are output, and the base part is sent to the base address bus g.
The displacement units are respectively connected to a displacement address bus h and sent to the main memory. Next, since the operation mode signal j is "0" when reading the operand in the native mode, the base address and displacement address are set in the operand address register 6, and then directly connected to the base address bus g and the displacement address bus. h and sent to main memory.

Next, in the address conversion operation mode, that is, in the emulation mode, since the operation mode signal j is "1", setting of the base address to the operand address register 6 is prohibited, and the setting of the base address from the arithmetic unit 7 is prohibited. Base address output is prohibited. That is, in the emulation mode, the base address of both address registers 5 and 6 is fixed, and only the displacement address is updated. Therefore, during the emulation mode, only the output signals of the displacement address portion of both the instruction address and operand address are connected to the displacement address bus h, and only the base address of the operand address register 6 is connected to the base address bus g. Connected. First, when reading an instruction,
A value indicating the address space area of the emulation machine to be selected from among multiple areas divided for each displacement address in the address space of the native machine, that is, the leading value conventionally set in the base address register. , is set in the base address portion of the operand address register 6 by the base address input signal j. and,
During emulation mode, the operation mode signal j
prevents storage to that part. Further, only the displacement address f is set in the program counter 5 and connected to the arithmetic unit 7. As for the calculation result by the calculator 7, only the displacement address is connected to the displacement address bus h, and the output of the base address is prohibited from being output to the bus g by the operation mode signal j.
Then, the base address is output from the operand address register 6 to the bus g.

Next, when reading the operand, the displacement address input signal f is set in the displacement address field of the operand address register 6, the beginning of the address space of the emulation machine is set in the base part, and the displacement address input signal f is set in the displacement address field of the operand address register 6. Address and base address are displaced address bus h and base address bus g
is output to main memory and used as an access address.

In this way, the access range to the main memory accompanying the instruction fetch operation and operand fetch operation during the address translation mode is indicated by the bit in the displacement part, starting from the address indicated by the base part of the operand address register 6. Specified within the range.

In this way, in this embodiment, the base address register 1 and selection circuit 8 that were conventionally required can be omitted, and the same address translation function can be realized.

〔Effect of the invention〕

As explained above, according to the present invention, only the address displacement part is updated, and the operand fetch and instruction fetch operations are defined within the area of the main memory indicated by the bits of the address displacement part. Therefore, there is no need for a conversion operation after an address is updated, and it is possible to reduce the hardware for address conversion and the operation time of the editing circuit after an address is updated, thereby improving the performance of the processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an address translation circuit showing an embodiment of the present invention, FIG. 2 is a flowchart showing the principle of the present invention, FIG. 3 is an explanatory diagram of a conventional address translation operation, and FIG. 4 is a conventional one. FIG. 2 is a block diagram showing an example of an address conversion circuit of FIG. 1: Base address register, 2, 5: Program counter, 3, 6: Operand address register, 4, 7: Arithmetic unit, 8: Selection circuit, c, g:
Base address bus, d, h: displacement address bus.

Claims (1)

[Claims] 1. In a main memory address control circuit equipped with a program counter indicating an instruction word address and an operand address register indicating the address of an operand necessary to execute the instruction word read by the program counter, each base portion It has a program counter and an operand address register that are divided into two fields, ie, a displacement part, and a displacement part.In emulation mode, the displacement part output of the program counter and the base part output of the operand address register are connected, and the instruction word address is An address conversion circuit characterized in that it accesses main memory as an operand address, and updates only a displaced portion of an operand address register as an operand address.