JPH0444968B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a data transmission device that primarily transmits data between systems that operate asynchronously. [Prior Art] Conventionally, a common method for transmitting data between asynchronous systems was to use FIFO (first-in, first-out) memory as a buffer between systems (interface
(See August 1984 issue, pages 268-270). for example,
When transmitting data between the A system and the B system that operate asynchronously, as shown in FIG. 3, a FIFO memory 3 is connected between the output of the A system 1 and the input of the B system 2. A system 1
A configuration is adopted to buffer the output of. Further, when data is transmitted between a plurality of asynchronous systems, a configuration is adopted in which FIFO memories 8 to 10 are connected between each of the asynchronous systems 4 to 7, as shown in FIG. By the way, in conventional data transmission devices, FIFO memory only has a data buffer function, so if such FIFO memory is used for data transmission between asynchronous systems, multiple asynchronous systems can only be connected in series. As a result, the overall system connected by FIFO memory consists of simply constructing a pipeline processing mechanism using cascade connections, which has an extremely low degree of freedom. In response to this, the applicant has developed and filed an application for a data transmission device that can provide greater flexibility when constructing overall data by connecting asynchronous systems (Japanese Patent Application No. 60-33035). , Tokugansho
60-33036). This uses asynchronous self-propelled shift registers to configure input data transmission paths, output data transmission paths, branch data transmission paths, and merge data transmission paths, and determines whether the data on the input data transmission path is data that should be branched. is judged by a branch judgment means, and if the data should be branched, the data is given from the input data transmission path to the branch data transmission path, and otherwise, the data on the input data transmission path is given to the output data transmission path. On the other hand, when there is an empty buffer on the input and output data transmission paths, it is applied to the data output data transmission path on the merged data transmission path, so that asynchronous systems can be connected not only in series but also in parallel. This is what I did. Here, FIGS. 5 and 6 show input data transmission paths,
An example of an asynchronous self-running shift register used for an output data transmission line and a branch data transmission line is shown.
In FIG. 5, 11 is a parallel data latch; 12 is a parallel data latch;
is 3-input NAND13, 2-input NAND14, 15
This is a transfer control circuit (hereinafter referred to as C element) which provides a rising edge trigger to the parallel data latch 11. An asynchronous self-running shift register is a register that automatically shifts input data in the output direction without using a shift clock, provided that the next register is empty, and it is a register that automatically shifts input data in the output direction without using a shift clock. It has a function. This asynchronous free-running shift register is composed of a parallel data latch 11 and a C element 12, and the C element 12 receives two inputs, P0 and P3.
It outputs two outputs P1 and P2, and the internal state of the C element 12 is determined by the states of these four signals PO to P3, and as shown in the table below, the 9 signals S ₀ to _{S 8}
take on two states. In the following description, it is assumed that logical values 0 and 1 correspond to low level and high level signal values, respectively.

[Means for solving problems]

The data transmission device according to the present invention transmits control signals for the preceding and subsequent C elements to the subsequent and preceding C elements at predetermined timings between two adjacent C elements, at least one of which is of a non-speed independent type. It is equipped with an interface to provide the information. [Operation] In this invention, since an interface is provided between C elements of different types and speeds, a control signal is input to the C element at a predetermined timing, and the C element
The device performs accurate operation. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 shows a data transmission device according to an embodiment of the present invention. In the figure, the same reference numerals as in FIGS. 5, 8, and 9 indicate the same elements as in the same figure, and 22 is an interface provided between the first and third type C elements 12 and 17, The interface 22 includes flip-flops 23 and 24 and a negative logic OR gate 25.
It is composed of. Next, the operation will be explained. It is assumed that the C elements 12, 17a, 17 and flip-flops 23, 24 have been reset in advance. The data input to the data transmission path is C
When reaching the stage of element 12, P2 of this C element 12
The output changes from 0 to 1, the clock input of the flip-flop 23 becomes 1, and its Q output also becomes 1, which is given to the next stage C element 17a as the P0 input.
Data is latched into the C element 17a stage. As the P2 output of the C element 17a becomes 1 and the P1 output becomes 0, the flip-flop 23 is reset and the Q output becomes 0. P2 of C element 17a
When the output becomes 1, the P0 input of the C element 17 becomes 1, and the P2 output becomes 1 and the P1 output becomes 0.
This P1 output of the C element 17 becomes 0, that is, the P3 input of the C element 17a becomes 0, and in response, the P1 output of the C element 17a becomes 1. This C element 17a
When the P1 output of the flip-flop 24 becomes 1, the flip-flop 24 outputs the P2 output of the C element 12 (currently still 1).
is latched, and the output becomes 0. When the output of flip-flop 24 enters the P3 input of C element 12, the P2 output of C element 12 becomes 0 and the P1 output becomes 1. When the P2 output of C element 12 becomes 0, flip-flop 24 is reset and the output of flip-flop 24 becomes 1. In the device of this embodiment as described above, an interface consisting of a flip-flop is provided between the speed dependent type 1 C element and the speed independent type 3 type C element, and the interface of the first or third type C element is provided. Since the control signal is given to the third or first type C element at a predetermined timing, control signals can be exchanged between the first type C element and the third type C element at a predetermined timing, and accurate Data transmission is possible. FIG. 2 shows another embodiment of the present invention, in which a third type C element 17 in the previous stage and a first type C element 17 in the next stage are shown.
An interface 22 is provided between the C-type element 12 and the C-type element 12. In the above embodiment, the first type C element and the third type C element
Although the case of connecting the elements has been described, the present invention can be similarly applied to the case of connecting the first type C element and the second type C element, or the second type C element and the third type C element. 1 type C element comrade or 2nd type C
The present invention can be similarly applied even when the operating speeds of the elements are different when connecting the elements. [Effects of the Invention] As described above, according to the data transmission device according to the present invention, there is a gap between two adjacent C elements, at least one of which is non-speed independent.
Since an interface is provided to provide control signals for the elements to the C elements in the subsequent stage and the preceding stage at predetermined timings, it is possible to guarantee accurate and reliable data transmission.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a data transmission device according to an embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the invention, and FIGS. 3 and 4 are diagrams of a conventional data transmission device. 5 and 6 are circuit configuration diagrams showing an example of an asynchronous free-running shift register used in the data transmission device of the present invention, and FIG. 7 explains the functions of this asynchronous free-running shift register. Figures 8 and 9 are for type 2 and type 3, respectively.
FIG. 3 is a circuit configuration diagram of a type C element. 12, 16...First and second type C elements (non-speed independent type C elements), 17... Third type C elements (speed independent type C elements), 22... Interface. In addition, in the figure,
The same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. Constructed using an asynchronous shift register consisting of a plurality of data storage means and a transfer control circuit in each stage that controls the data storage means in its own stage according to a control signal from a transfer control circuit in an adjacent stage. In a data transmission device that is equipped with a data transmission path and performs data transmission between systems using the data transmission path, there is a connection between two adjacent transfer control circuits, at least one of which is non-speed independent 1. A data transmission device comprising an interface circuit that provides a control signal of a transfer control circuit to a subsequent-stage transfer control circuit and a previous-stage transfer control circuit at predetermined timings. 2. The data transmission device according to claim 1, wherein the transfer control circuit is composed of a C element.