JPH0424736B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a data transmission device that transmits data between systems that mainly operate asynchronously, and particularly to the configuration of branching and merging sections thereof. [Prior Art] Conventionally, a common method for transmitting data between asynchronous systems has been to use a FIFO (first-in, first-out) memory as a buffer between systems. However, this
FIFO memory simply has a data buffer function, so if such FIFO memory is used for data transmission between asynchronous systems, multiple asynchronous systems can only be connected in series, and therefore FIFO The overall system connected to the memory merely constructs a pipeline processing mechanism using a simple cascade connection, and the problem is that the degree of freedom is extremely low. In response, the applicant has developed and applied for a data transmission device that can provide a large degree of freedom when constructing an entire system by connecting asynchronous systems (Japanese Patent Application No. 60-33035, Special request 1986
-Refer to No. 33036). This data transmission device will be explained below. FIG. 1 is a diagram showing the system of the data transmission device, in which 5 is a data transmission path, 2a to
2c is a branching part, 3a to 3c is a confluence part, 1a to 1c
is a processing element, and 4 is an interface. In such a device, packet data flowing from an external system via the interface 4 reaches any one of the processing elements 1a to 1c while circulating between the network elements 3a and 2a to 2c. After the distributed processing is performed by the network elements 1c, the processing results are collected by the network elements 3b and 3c, and sent again to the external system via the interface 4. 12 and 13 show the configurations of the branching section and merging section of the apparatus shown in FIG. 1 above. First, the twelfth
The branch shown in the figure is usually input data transmission line 1.
0 is applied to the output data transmission line 20 via the selective branch control section 40, while the branch judgment section
If it is determined that the input data is data to be branched at the main branch section, the input data is sent to the branch data transmission line 30 via the branch control section 40.
This will cause the branch to branch out. Further, the merging section shown in FIG. 13 normally supplies the data on the input data transmission path 10 to the output data transmission path 20 via the merging control section 60, while controlling the idle state of both the input and output data transmission paths. An empty buffer monitoring section 80 monitors the buffer, and when a predetermined empty buffer is detected on both transmission paths, the merging control section 60 causes the data on the merging data transmission path 70 to merge into the output data transmission path 20. It is. FIG. 14 is a schematic block diagram showing an example of an asynchronous self-running shift register used in each of the data transmission lines shown in FIGS. 12 and 13. This asynchronous self-running shift register is a register in which input data is automatically shifted in the output direction without using a shift clock, provided that the next register is empty. It has a buffer function. Each stage of this asynchronous self-running shift register is composed of a parallel data latch L and a transfer control circuit C (hereinafter referred to as a C element) which provides a rising edge trigger to the parallel data latch. Further, as shown in FIG. 15, for example, the C element is composed of a 3-input NAND circuit C11 and 2-input NAND circuits C12 and C13. In the figure, for initialization
The INIT signal is omitted. Here, the above C element receives two inputs, P0 and P3, and outputs two outputs to P1 and P2,
The internal state of the C element is determined by the states of these four signals, and takes nine states, _S0 to _S8 , as shown in Table 1 below. In the following explanation, the logical values "0" and "1" represent the low level and signal value, respectively.
Equivalent to high level.

[Problem that the invention seeks to solve]

However, in such a data transmission device, since data is transmitted asynchronously, it is not possible to know whether the data is being moved or not, and data may become clogged in the branch data transmission path connected to each processing module. In other words, it is unclear whether each processing module still has sufficient processing capacity. Therefore, in some cases, data is concentrated only in a certain processing module, resulting in a problem that the overall data processing speed becomes faster. Furthermore, in the above data transmission device, the free state of the input and output data transmission paths is monitored at the merging section to permit merging.
There was a problem that the circuit configuration of this part was complicated. The present invention has been made in view of the above points, and an object of the present invention is to provide a data transmission device that can perform branching control according to the state of the branch data transmission line and can simplify the circuit configuration of the merging section. It is said that [Means for Solving the Problems] A data transmission device according to the present invention is one in which each data transmission path is configured using a self-propelled shift register consisting of a data latch and a C element, and in a branch section, branch data transmission is performed. Branching control is performed by detecting whether the road is empty and whether data is moving, that is, whether data is clogged, and at merging points, the main road is controlled based on the assumption that data on the main road will not stop. The merging control is performed by monitoring the vacant state only behind the merging point on the line. [Operation] In the present invention, when performing branch control, branch control is performed by monitoring the free state of the branch data transmission path and the data clogged state, so that the load is distributed without data being concentrated on a certain processing module. Furthermore, when performing merging control, the merging is permitted by monitoring only the vacancy state at the rear, so a circuit for monitoring the vacancy state at the front, etc. is omitted, simplifying the circuit configuration. [Example] Hereinafter, an example of the present invention will be described with reference to the drawings.
The overall configuration of one embodiment of the present invention is similar to that shown in FIG. FIG. 2 is a block diagram of a branching section according to an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 12 indicate the same or corresponding parts. Reference numeral 75 denotes an empty buffer monitoring unit (transmission line empty detection unit) for monitoring the empty state of the branch data transmission line 30, and as shown in FIG. and wired OR their outputs.
When all the outputs of the C elements in the figure are "0", a blank detection output B (BLANK) of "1" is output. Reference numeral 85 denotes a data blockage detection unit for detecting data blockage in the branch data transmission line 30, and as shown in FIG.
It is configured by connecting C elements a to 85c and wired ORing their outputs, and when the output of each C element is all "1", that is, in this example, when 3 words of data are in the standby state. , a clogging detection output P of "1" is output. Reference numeral 15 denotes a coincidence circuit, which outputs control signals B and R (BRNRDY) when "1" is output from both the empty buffer monitoring section 75 and the data clog detection section 85.
This outputs the following. Further, 50 is a branch determination section, which, as shown in FIG. 5, is added to the circuit shown in FIG.
An AND gate 57 is added which receives the branch judgment result output from the NAND gate circuit 55 and the control signals B and R from the coincidence circuit 15 as two inputs. Note that the other circuit configurations (including the circuit configuration of the C element) are the same as those shown in the conventional example. FIG. 6 shows the block configuration of the confluence section. The configuration of the merging section of this embodiment is almost the same as that shown in FIG. This is what I decided to do. In other words, under the condition that data does not stop in the loop-shaped transmission line at the main confluence, if the area behind the confluence of the main lines at the confluence is monitored, the area in front of the confluence can be monitored. It is constructed on the basis that it is equivalent to As a specific circuit configuration, in the circuit shown in FIG.
It is possible to think of something equivalent to omitting d. Next, the operation will be explained. First, the operation of the branch section will be explained with reference to FIG. 2. When packet data is input to the input data transmission line 10, a branch determination is made in the same manner as explained in FIG. 17 above. Also, at the same time,
In the branch data transmission line 30, the empty state of the transmission line and the data clogged state are monitored by an empty buffer monitoring section 75 and a data clogged detection section 85, respectively, and the detection results of these two detection sections are sent to the matching circuit 15. It is sent to the branch determination unit 50 via.
Then, branch control is performed according to these detection results and the result of the above-mentioned branch judgment. That is, it is determined that the packet data on the input data transmission path 10 is data that should be branched at the main branch, and that there is a predetermined free buffer on the branch data transmission path 30 and that there is no data blockage. If so,
A C signal is applied from the branch determination section 50 to the branch control section 40, whereby the packet data on the input data transmission line 10 is branched to the branch data transmission line 30. Further, if any one of the above three conditions is not satisfied, the packet data is not branched and is provided to the output data transmission line 20. Note that the branch control unit 40
The detailed operation in is similar to the conventional operation. Next, the operation of the merging section will be explained with reference to FIG.
The operation of this embodiment is almost the same as the conventional merging operation, but in this embodiment, based on the premise that data on the data transmission path does not stop as described above, Only the free state on the input data transmission path 10 is monitored, and if there is a free buffer with a predetermined number of words or more on the input data transmission path 10, data will not be merged regardless of the state of the output data transmission path 20. Allowed. In the device of this embodiment, the branch control is performed by detecting the empty state of the branch data transmission line 30 and the clogged state of data at the branch section, so that, for example, data is concentrated in one processing module, If the amount of data exceeds the processing capacity of the module, the data can be supplied to another processing module for processing. Therefore, data is not intensively supplied to one processing module, and packet data can be branched smoothly and at high speed. Further, at the merging section, since the merging control is performed by monitoring the empty state only behind the merging section, the circuit configuration is simpler than that of the conventional device. FIG. 7 shows another embodiment of the branch control section 40, which differs from the above embodiment in the way the control signal is returned to the previous stage of the C element. This figure also shows a circuit for initialization. That is, in this embodiment, when returning control signals from the C element on the output data transmission line side and the C element on the branch data transmission line side to the C element on the input data transmission line side, both signals are passed through the negative logic input/output OR circuit 45. I'm trying to give it back. Further, 46 and 47 are a flip-flop and an inverter, respectively, for initializing the D-type latch 44, and in the initial state of the system.
The INIT signal is input, the gate of the D-type latch 44 is opened, and the C signal (“0”) is latched, so that in the initial state, the data on the input data transmission line is always given to the output data transmission line. It is for the purpose of 9 and 10 respectively show other configuration examples of the empty buffer monitoring section 75 and the data jam detection section 85 in the branch section, which have two stages of C elements provided between the data latches. This is an example of an applicable configuration. Such a configuration is effective when the transfer rate of control signals between C elements is faster than the data transfer rate between data latches, and an example of the circuit configuration of the C element in such an embodiment is as follows. As shown in FIG. 11a, it is desirable to use the output of the NAND gate C13 as the control signal P1 to the previous stage. Furthermore, various configurations can be considered as the configuration of the C element, for example, the first
As shown in Figure 1b, the two-input NAND gate C1
4, C15, C16, negative logic input OR gate C1
7. It may be configured by an inverter C18. The free buffer monitoring unit 76 shown in FIG.
It consists of open collector inverters 76a to 76f connected to element outputs, and outputs an empty detection output of "1" when all C element outputs in the figure are "0". Further, the data jam detection section 86 in FIG. 10 includes open collector inverters 86a to 86f connected to the outputs of each C element and open collector inverters 86g to 86l connected to the control signal output to the previous stage of the C element. The output of the C element is "0, 1,
0,1,0,1” or “1,0,1,0,1,
0'', a data blockage is detected, and a blockage output P is output as a result. FIG. 8 shows still another embodiment of the branch control section, which is applied to a data transmission path having two stages of C elements between data latches, as shown in FIGS. 9 and 10. It is something that will be done. In the figure, 7th
The same reference numerals as in the figure indicate the same thing, 48e, 48
g are NAND gates 48f and 48h that operate similarly to NAND gates 42e and 42g, respectively.
are open collector NAND gates that operate similarly to NAND gates 42f and 42h, and each open collector NAND gate 48
The outputs of f and 48h are wired OR connected to return a control signal to the C element in the previous stage. Therefore, in this embodiment, the number of logic gate delay stages is reduced by one stage compared to the embodiment shown in FIG. 7, and the data throughput of the branch section can be improved. In each of the above embodiments, the case where data is transmitted between asynchronous systems is explained, but the present invention can be similarly applied to the case where data is transmitted between synchronous systems. In this case, the C element is replaced with a synchronous type control element. And it is sufficient. [Effects of the Invention] As described above, according to the present invention, in a data transmission device in which each data transmission path is configured using a self-propelled shift register, the vacant state of the branch data transmission path and the data Since the blockage condition is detected and branching control is performed, and at the merging section, the merging control is performed by looking at the empty state only at the rear, so data is concentrated in one processing module and the data processing speed of the entire system is reduced. This has the effect of preventing delays and simplifying the circuit configuration of the merging section.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a data transmission device according to an embodiment of the present invention, FIG. 2 is a block diagram of a branch section thereof, and FIG. 3 is a diagram showing an example of the configuration of an empty buffer monitoring section of the branch section. FIG. 4 is a diagram showing an example of the configuration of the data jam detection section of the branch section, FIG. 5 is a diagram showing an example of the configuration of the branch judgment section of the branch section, and FIG. 6 is the merging section of the data transmission device. 7 and 8 are diagrams showing other configuration examples of the branch control section of the device, FIG. 9 is a diagram showing another configuration example of the free buffer monitoring section of the device, and FIG. 10 Figures 11a and 11b are diagrams showing other configuration examples of the data jam detection section of the device.
12 is a diagram showing another configuration example of the C element, FIGS. 12 to 18 are diagrams showing a data transmission device already developed by the applicant, FIG. 12 is a block diagram of its branching part, and FIG. is a block diagram of the confluence section, the first
Figure 4 is a block diagram showing an example of the configuration of an asynchronous free-running shift register constituting the transmission line, Figure 15 is a diagram showing a specific example of the circuit configuration of the C element, and Figure 16 is a diagram showing a specific example of the circuit configuration of the C element.
The figure shows the state transition of the C element.
18 is a diagram showing a specific example of the circuit configuration of the branching section shown in FIG. 2, and FIG. 18 is a diagram showing a specific example of the circuit configuration of the merging section shown in FIG. 13. 10... Input data transmission line, 20... Output data transmission line, 30... Branch data transmission line, 40...
Branch control unit, 50...branch determination unit, 60...merging control unit, 70...merging data transmission path, 75, 76
. . . Empty buffer monitoring unit (branch data transmission line vacancy detection means), 80 . Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of Claims] 1. The main data transmission line, the branch data transmission line, and the merged data transmission line operate their own data storage means in response to control signals from a plurality of data storage means and transfer control circuits of adjacent stages. A data transmission device configured using a shift register consisting of a transfer control circuit of each stage to be controlled, wherein the branch data transmission line is provided on the input side of the branch data transmission line to monitor the idle state of the input side. Transmission line vacancy detection means is provided on the output side of the vacancy detection means of the branch data transmission line and detects whether data is moving on the output side to detect data blockage in the branch data transmission line. input data branching means having a data clog detection means, and a branching determination means for branching the data on the main line to the branch data transmission line when it is detected by both means that there is an empty space and there is no data blockage; Data merging comprising main line data transmission path vacancy detection means for monitoring the vacancy state behind the merging point on the main line, and merging determination means for merging data on the merging data transmission path into the main line when vacancy is detected by the means. A data transmission device characterized by comprising: means. 2. The data transmission device according to claim 1, wherein the main data transmission line is configured in a loop shape. 3. The input data branching means includes selective branching determination means for selectively branching data on the main line according to its contents. Data transmission device as described in section.