JPH0444737U - - Google Patents

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Publication number
JPH0444737U
JPH0444737U JP6847190U JP6847190U JPH0444737U JP H0444737 U JPH0444737 U JP H0444737U JP 6847190 U JP6847190 U JP 6847190U JP 6847190 U JP6847190 U JP 6847190U JP H0444737 U JPH0444737 U JP H0444737U
Authority
JP
Japan
Prior art keywords
switching
controllable switch
circuit according
constant voltage
switching means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6847190U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6847190U priority Critical patent/JPH0444737U/ja
Publication of JPH0444737U publication Critical patent/JPH0444737U/ja
Pending legal-status Critical Current

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  • Electronic Switches (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の1実施例を示す回路図、第2
図〜第7図はそれぞれ従来のスイツチング回路を
示す回路図、第8図〜第10図はそれぞれ本考案
の1実施例を示す回路図、である。 符号の説明、20……サイリスタ(ゲート・タ
ーン・オフ型)、21……トランジスタ(ノーマ
リイ・オン型SIT)、t1〜t6……端子。
Figure 1 is a circuit diagram showing one embodiment of the present invention, Figure 2 is a circuit diagram showing one embodiment of the present invention.
7 to 7 are circuit diagrams showing conventional switching circuits, and FIGS. 8 to 10 are circuit diagrams showing one embodiment of the present invention, respectively. Explanation of symbols: 20... Thyristor (gate turn-off type), 21... Transistor (normally on type SIT), t1 to t6... terminals.

Claims (1)

【実用新案登録請求の範囲】 (1) 自己ターン・オフ機能を持つ第1のスイツ
チング手段があつて、その駆動信号入力用に対を
なすその制御端子、主端子を制御端子ct、主端
子mtaとしたときに、 前記主端子mta側に第1の非可制御スイツチ
が来る様に、しかも、第2のスイツチング手段と
前記第1のスイツチング手段で前記第1の非可制
御スイツチを挟む様に、これらを直流電圧源の両
電源端子間に直列接続し、 第2の非可制御スイツチを前記第1の非可制御
スイツチと前記第2のスイツチング手段の接続点
と前記制御端子ctの間に前記第1の非可制御ス
イツチと逆向きに接続し、 前記第1の非可制御スイツチと前記第2のスイ
ツチング手段の直列回路に通流手段を並列接続し
、前記第2のスイツチング手段と連係してオン、
オフする第3のスイツチング手段がオンのとき、
逆バイアス電圧供給手段が前記第3のスイツチン
グ手段と前記通流手段を介して前記制御端子ct
・主端子mta間に逆バイアス電圧を印加する閉
回路を形成し、 前記第2又は第3のスイツチング手段がオンの
とき、前記第1のスイツチング手段にオン信号を
出力しないオン信号出力手段を設けたことを特徴
とするスイツチング回路。 (2) 前記通流手段として、第3の非可制御スイ
ツチを用いたことを特徴とする請求項1記載のス
イツチング回路。 (3) 前記通流手段として、抵抗を用いたことを
特徴とする請求項1記載のスイツチング回路。 (4) 前記通流手段として、負荷を用いたことを
特徴とする請求項1記載のスイツチング回路。 (5) 前記第1の非可制御スイツチの代わりに、
2方向に対して定電圧作用がある第1の定電圧手
段を用いたことを特徴とする請求項1,2,3又
は4記載のスイツチング回路。 (6) 前記第1の定電圧手段として、ツエナー・
ダイオードを用いたことを特徴とする請求項5記
載のスイツチング回路。 (7) 前記第2の非可制御スイツチの代わりに、
2方向に対して定電圧作用がある第2の定電圧手
段を用いたことを特徴とする請求項1〜6のいず
れか1項に記載のスイツチ回路。 (8) 前記第2の定電圧手段として、ツエナー・
ダイオードを用いたことを特徴とする請求項7記
載のスイツチング回路。
[Claims for Utility Model Registration] (1) There is a first switching means having a self-turn-off function, and its control terminals and main terminals are connected to a control terminal ct and a main terminal mta, which form a pair for inputting drive signals. , the first non-controllable switch is placed on the main terminal mta side, and the first non-controllable switch is sandwiched between the second switching means and the first switching means. , these are connected in series between both power supply terminals of a DC voltage source, and a second non-controllable switch is connected between the connection point of the first non-controllable switch and the second switching means and the control terminal ct. connected in the opposite direction to the first non-controllable switch, connecting a current flow means in parallel to the series circuit of the first non-controllable switch and the second switching means, and coordinating with the second switching means; and turn on,
When the third switching means for turning off is on,
A reverse bias voltage supply means is connected to the control terminal ct via the third switching means and the communication means.
- Forming a closed circuit that applies a reverse bias voltage between the main terminals mta, and providing on-signal output means that does not output an on-signal to the first switching means when the second or third switching means is on. A switching circuit characterized by: (2) The switching circuit according to claim 1, wherein a third non-controllable switch is used as the flow means. (3) The switching circuit according to claim 1, wherein a resistor is used as the flow means. (4) The switching circuit according to claim 1, wherein a load is used as the flow means. (5) Instead of the first non-controllable switch,
5. The switching circuit according to claim 1, further comprising a first constant voltage means having a constant voltage effect in two directions. (6) As the first constant voltage means, Zener
6. The switching circuit according to claim 5, wherein a diode is used. (7) Instead of the second non-controllable switch,
7. The switch circuit according to claim 1, further comprising a second constant voltage means having a constant voltage effect in two directions. (8) As the second constant voltage means, Zener
8. The switching circuit according to claim 7, wherein a diode is used.
JP6847190U 1990-06-29 1990-06-29 Pending JPH0444737U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6847190U JPH0444737U (en) 1990-06-29 1990-06-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6847190U JPH0444737U (en) 1990-06-29 1990-06-29

Publications (1)

Publication Number Publication Date
JPH0444737U true JPH0444737U (en) 1992-04-16

Family

ID=31801079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6847190U Pending JPH0444737U (en) 1990-06-29 1990-06-29

Country Status (1)

Country Link
JP (1) JPH0444737U (en)

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