JPH0444242A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0444242A JPH0444242A JP2149095A JP14909590A JPH0444242A JP H0444242 A JPH0444242 A JP H0444242A JP 2149095 A JP2149095 A JP 2149095A JP 14909590 A JP14909590 A JP 14909590A JP H0444242 A JPH0444242 A JP H0444242A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- chip
- wire
- resin
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229920005989 resin Polymers 0.000 claims abstract description 19
- 239000011347 resin Substances 0.000 claims abstract description 19
- 239000004020 conductor Substances 0.000 claims abstract description 11
- 238000005266 casting Methods 0.000 claims abstract 2
- 238000001721 transfer moulding Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 3
- 238000007789 sealing Methods 0.000 abstract description 5
- 239000003822 epoxy resin Substances 0.000 abstract description 4
- 229920000647 polyepoxide Polymers 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えば制御用ＩＣのような電流容量の小さい
半導体素子とパワートランジスタのような電流容量の大
きい半導体素子とを同一リードフレームの別個のマウン
ト部にそれぞれ装着し、素子の電極とリードフレームの
ワイヤボンディング部とを導線によって接続したのち樹
脂によって封止する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is directed to separate semiconductor elements with a small current capacity, such as a control IC, and semiconductor elements with a large current capacity, such as a power transistor, on the same lead frame. The present invention relates to a method of manufacturing a semiconductor device, in which the semiconductor device is mounted on a mount portion of the device, the electrodes of the device and the wire bonding portion of the lead frame are connected by conductive wires, and then sealed with resin.
電力用素子とそれを制御するＩＣとを一つの半導体装置
として一体に樹脂封止するには、絶縁基板上に各素子を
固着し、素子の電極を絶縁基板上の配線と導線で接続し
たのち、絶縁基板と側壁からなる容器に樹脂を充填した
ものが知られている。In order to integrally resin-seal a power element and an IC that controls it as one semiconductor device, each element is fixed on an insulated substrate, and the electrodes of the element are connected to the wiring on the insulated substrate with a conductive wire. It is known that a container consisting of an insulating substrate and a side wall is filled with resin.
第２図はそのような半導体装置で、同図（Ｍｌに示すよ
うに絶縁性基板１０上に直接Ｉ＃ＩＩｌ用ＩＣのチップ
２１が、また基板ｌＯ上の導体部３１に電力用素子のチ
ップ２２が固着されており、各チップの電極を基板１０
上の配線３２とは導１ｉ４により接続されている。FIG. 2 shows such a semiconductor device, in which an IC chip 21 for I#IIl is directly mounted on an insulating substrate 10 as shown in Ml, and a power element chip 21 is mounted directly on a conductor portion 31 on a substrate IO. 22 is fixed, and the electrodes of each chip are connected to the substrate 10.
It is connected to the upper wiring 32 by a conductor 1i4.
同図（ｂｌに示すようにこのような絶縁性基板ｌＯと絶
縁性側壁１２とからなる容器に樹脂が注入され、配＆１
３２に接続された端子３３が容器外に露出している。As shown in FIG.
Terminal 33 connected to terminal 32 is exposed outside the container.
しかし、このような半導体装置の製造には、素子の固着
、ワイヤボンディング等に時間がかかり、量産に不向き
でコストが高いという問題がある。However, manufacturing such a semiconductor device has the problem that it takes time to fix elements, wire bonding, etc., making it unsuitable for mass production and high cost.
これに対し、同一リードフレームの別個のマウント部に
ｗＩ御用ＩＣ１電力用素子をそれぞれ装着し、そのリー
ドフレームのワイヤボンディング部と素子の電極とを導
線によって接続したのち、トランスファモールドにより
樹脂封止をする方法は、度に大量の半導体装置の製造が
可能で、コストが安くなる。On the other hand, each wI-approved IC1 power element is mounted on a separate mounting part of the same lead frame, and after connecting the wire bonding part of the lead frame and the electrode of the element with a conductive wire, resin sealing is performed using transfer molding. With this method, it is possible to manufacture a large number of semiconductor devices at a time, and the cost is low.
しかし、電流容量の小さい制御用ｒｃの接続に用いる導
線は直径１００ ｎ以下の細い線であるため、トランス
フ１モールドを行う際に樹脂に押されてリードフレーム
の他の部分あるいは他の導線に望ましくない接触をする
問題がある。However, since the conductor wire used to connect the control RC with a small current capacity is a thin wire with a diameter of 100 nm or less, it may be pressed by the resin during the transfer molding and may be undesirably attached to other parts of the lead frame or other conductor wires. There is no problem with making contact.
本発明の目的は、上述の問題を解決し、電流容量の小さ
い半導体素子とリードフレームのワイヤボンディング部
とを接続する細い導線をリードフレームの他の部分など
に望ましくない接触をさせることなくトランスファモー
ルドにより樹脂封止できる半導体装置のｔ！遣方法を提
供することにある。An object of the present invention is to solve the above-mentioned problems, and to transfer a thin conductive wire that connects a semiconductor element with a small current capacity to a wire bonding part of a lead frame without undesirably contacting other parts of the lead frame. t! of semiconductor devices that can be resin-sealed by The goal is to provide a way to send money.
上記の目的を達成するために、本発明は、一つのり一部
フレームの別個のマウント部にそれぞれ半導体素子を固
着し、各半導体素子の電極とリードフレームのワイヤボ
ンディング部とを導線にて接続したのち、先ず電流容量
の小さい素子との接続導線を滴下した樹脂により被覆し
、次いでトランスファモールドによりリードフレームの
大部分、前記素子を被覆する滴下樹脂および滴下樹脂に
被覆されない素子全体を注型樹脂にて封止するものとす
る。In order to achieve the above object, the present invention fixes semiconductor elements to separate mounting parts of a single frame, and connects the electrodes of each semiconductor element and the wire bonding part of a lead frame with conductive wires. After that, first, the connecting conductor to the element with a small current capacity is coated with the dropped resin, and then, by transfer molding, most of the lead frame, the dropped resin covering the element, and the entire element not covered by the dropped resin are covered with the cast resin. shall be sealed.
トランスファモールド時には、電流容量の小さい半導体
素子との細い接続Ｒ線は滴下された樹脂により被覆され
ているため、モールド樹脂により押し流されてリードフ
レームの他の部分あるいは他の導線に望ましくない接触
をすることがなくなる。During transfer molding, the thin connecting R wires with semiconductor elements with low current capacity are covered with dropped resin, so they may be swept away by the molding resin and come into undesirable contact with other parts of the lead frame or other conductive wires. Things will go away.
以下、本発明の一実施例の工程を第１図を引用して順次
説明する。第１図においては、第２図と共通の部分には
同一の符号が付されている。この工程ではリードフレー
ム１を用い、第１図価）に示すようにそのマウント部１
１に制御用ＩＣＣチップ１を、マウント部１２に電力用
トランジスタチップ２２をグイボンディングする。そし
てＩＣチフブ２１トランジスタチップ２２の上面の電極
とリードフレームのワイヤボンディング部とをＭ線４を
用いてのワイヤポンディングにより接続する。第１図（
ｂ）はその状態を側面図で示す、第１図ｔｅｌにおいて
は、流動性の高いエポキシ樹脂５を上から滴下し、ＩＣ
チップ２１およびその電極とリードフレーム１とを接続
するＭ線を被覆する。ＩＣチップ２１の接続導線は直径
５０ｎ、）ランジスタ２２の接続導線は直径２００−で
ある、第１図ｆｄ＋はその状態を側１ｉｌｉｒＸＪで示
す、こののち、電力用素子チップ２２およびすべての導
線４を含めた全体をエポキシ樹脂６のトランスファモー
ルドにより封止する。そして、第１図ｔｅｌに示すよう
にリードフレーム１の一部を露出させておく、このリー
ドフレームｌの露出部は連結部１３を切離すことにより
端子となる。トランスファモールド時にはＩＣチップ２
Ｉの接続導線４は樹脂５により包まれているので、細（
でも流れることがない。Hereinafter, the steps of an embodiment of the present invention will be sequentially explained with reference to FIG. In FIG. 1, parts common to those in FIG. 2 are given the same reference numerals. In this process, a lead frame 1 is used, and its mounting portion 1 is
The control ICC chip 1 is bonded to the mount portion 12, and the power transistor chip 22 is bonded to the mount portion 12. Then, the electrode on the upper surface of the IC chip 21 and the transistor chip 22 and the wire bonding portion of the lead frame are connected by wire bonding using the M wire 4. Figure 1 (
b) shows the state in side view. In Fig. 1 tel, highly fluid epoxy resin 5 is dropped from above and the IC
The M wire connecting the chip 21 and its electrodes to the lead frame 1 is covered. The connecting conductor of the IC chip 21 has a diameter of 50n, and the connecting conductor of the transistor 22 has a diameter of 200-n. FIG. The whole including the structure is sealed by transfer molding of epoxy resin 6. A part of the lead frame 1 is exposed as shown in FIG. IC chip 2 when transfer molding
Since the connecting conductor 4 of I is wrapped in resin 5, it is thin (
But it doesn't flow.
本発明によれば、電流容量の小さい素子との接続に用い
られた細い導線を予め滴下樹脂で被覆したのち、ｔｉ電
流容量大きい素子を含めてトランスファモールドで樹脂
封止することにより、トランスファモールドの際に細い
導線が押し流されて望ましくない接触をすることがなく
なり、短絡不良などの発生を防止できた。According to the present invention, after coating thin conductive wires used for connection with elements with small current capacity with dripped resin in advance, the transfer mold is used to seal the thin conductive wires, including the elements with large current capacity, with the resin. This prevents the thin conductive wires from being swept away and causing undesirable contact, thereby preventing the occurrence of short circuits and other defects.
【図面の簡単な説明】
第１図は本発明の一実施例の工程を（ａｌ〜Ｆｅ＋の順
に不し、 （ａｌ、 ｔｅｌ、 （ｓｌは平面図、（ｂ
ｌ、（ｄ＋は側面図、第２図は従来の半導体装置を示し
、＋ａ＋は封止前の平面図、（′ｂ）は封止後の側面図
である。
１：リードフレーム、１１．１２：マウント部、２１：
制御用ＩＣチップ、２２：電力用素子チップ、４：導線
、５：滴下樹脂、６：トランスフアモールド樹脂、
へへま人弁理士 山 口
巖
（Ｃ）
！
！
（ｄ）
（（Ｊ）
（ｂ）
第２図[Brief Description of the Drawings] Fig. 1 shows the steps of an embodiment of the present invention in the order of (al to Fe+), (al, tel, (sl is a plan view, (b
l, (d+ is a side view, Figure 2 shows a conventional semiconductor device, +a+ is a plan view before sealing, and ('b) is a side view after sealing. 1: Lead frame, 11.12 :Mount part, 21:
Control IC chip, 22: Power element chip, 4: Conductive wire, 5: Dropped resin, 6: Transfer mold resin,
Idiot patent attorney Iwao Yamaguchi (C)! ! (d) ((J) (b) Figure 2
Claims (1)
れ半導体素子を固着し、各半導体素子の電極とリードフ
レームのワイヤボンディング部とを導線にて接続したの
ち、先ず電流容量の小さい素子との接続導線を滴下した
樹脂により被覆し、次いでトランスファモールドにより
リードフレームの大部分、前記素子を被覆する滴下樹脂
および滴下樹脂に被覆されない素子全体を注型樹脂によ
り封止することを特徴とする半導体装置の製造方法。1) After fixing each semiconductor element to a separate mounting part of one lead frame and connecting the electrode of each semiconductor element and the wire bonding part of the lead frame with a conductor wire, first connect the conductor wire to the element with small current capacity. A manufacturing method of a semiconductor device characterized in that most of the lead frame, the dropped resin covering the element, and the entire element not covered by the dropped resin are sealed with a casting resin by transfer molding. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149095A JPH0444242A (en) | 1990-06-07 | 1990-06-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2149095A JPH0444242A (en) | 1990-06-07 | 1990-06-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0444242A true JPH0444242A (en) | 1992-02-14 |
Family
ID=15467588
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2149095A Pending JPH0444242A (en) | 1990-06-07 | 1990-06-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0444242A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5589709A (en) * | 1992-12-03 | 1996-12-31 | Linear Technology Inc. | Lead frame capacitor and capacitively-coupled isolator circuit using same |
-
1990
- 1990-06-07 JP JP2149095A patent/JPH0444242A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5589709A (en) * | 1992-12-03 | 1996-12-31 | Linear Technology Inc. | Lead frame capacitor and capacitively-coupled isolator circuit using same |
| US5650357A (en) * | 1992-12-03 | 1997-07-22 | Linear Technology Corporation | Process for manufacturing a lead frame capacitor and capacitively-coupled isolator circuit using same |
| US5926358A (en) * | 1992-12-03 | 1999-07-20 | Linear Technology Corporation | Lead frame capacitor and capacitively-coupled isolator circuit using same |
| US5945728A (en) * | 1992-12-03 | 1999-08-31 | Linear Technology Corporation | Lead frame capacitor and capacitively coupled isolator circuit |
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