JPH0444235A - Manufacture of high-speed bipolar transistor - Google Patents

Manufacture of high-speed bipolar transistor

Info

Publication number
JPH0444235A
JPH0444235A JP2148813A JP14881390A JPH0444235A JP H0444235 A JPH0444235 A JP H0444235A JP 2148813 A JP2148813 A JP 2148813A JP 14881390 A JP14881390 A JP 14881390A JP H0444235 A JPH0444235 A JP H0444235A
Authority
JP
Japan
Prior art keywords
base
layer
buried layer
impurities
diffusion coefficient
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2148813A
Other languages
Japanese (ja)
Inventor
Yoshimitsu Kuromaru
好光 黒丸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New Japan Radio Co Ltd
Original Assignee
New Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New Japan Radio Co Ltd filed Critical New Japan Radio Co Ltd
Priority to JP2148813A priority Critical patent/JPH0444235A/en
Publication of JPH0444235A publication Critical patent/JPH0444235A/en
Pending legal-status Critical Current

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  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To enable a narrower base width to be achieved by doping impurities whose diffusion coefficient is larger than that at other parts onto a part which is directly below a genuine base of a buried layer when forming a buried layer and by utilizing the plenomenon that the impurities with a larger diffusion coefficient are raised by later heat treatment. CONSTITUTION:When doping impurities of an N<+> buried layer 2a for a P sub strate 1, impurities with a larger diffusion coefficient than that at other parts are doped at a part which is directly below a genuine base and an epitaxial layer 4 is allowed to grow on it, thus forming a separation diffusion layer 3 for element separation. The impurities with a larger diffusion coefficient which are doped directly below the genuine base of the N<+> buried layer 2a is raised as shown in figure by later heat treatment, thus suppressing diffusion of boron ion at the genuine base part of a base diffusion layer 5 due to implanta tion of boron ion, enabling impurity distribution to be sharp, and helping to achieve a narrow base width.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高速バイポーラトランジスタの製造方法、特
に、より狭いベース拡散層を実現する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing high-speed bipolar transistors, and in particular to a method for realizing a narrower base diffusion layer.

〔従来の技術] 第2図は従来のバイポーラトランジスタの一例の構造を
示す。
[Prior Art] FIG. 2 shows the structure of an example of a conventional bipolar transistor.

図においてlはPサブストレート、2はN゛埋込層、3
は分離拡散層、4はエピタキシャル層、5はベース拡散
層、6はエミッタ拡散層、7はコレクタ拡散層である。
In the figure, l is the P substrate, 2 is the N buried layer, and 3
4 is an isolation diffusion layer, 4 is an epitaxial layer, 5 is a base diffusion layer, 6 is an emitter diffusion layer, and 7 is a collector diffusion layer.

バイポーラトランジスタの高速化には、ベース幅を狭く
することが絶対条件である。
Narrowing the base width is an absolute prerequisite for increasing the speed of bipolar transistors.

一方、高速バイポーラトランジスタのベース拡散層の形
成には、ボロンイオン注入法が用いられているが、チャ
ンネリングのため、 不純物分布がガウス分布からはず
れ、第3図のボロンプロファイルの一例に示すようにな
るため、急峻な分布が実現できず、これがベース幅をよ
り狭くするのに障害となってきた。
On the other hand, boron ion implantation is used to form the base diffusion layer of high-speed bipolar transistors, but due to channeling, the impurity distribution deviates from the Gaussian distribution, resulting in an impurity profile as shown in the example of the boron profile in Figure 3. As a result, a steep distribution cannot be achieved, and this has been an obstacle to narrowing the base width.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来、高速バイポーラトランジスタの製造において、上
記のように、チャンネリングのため、ベース拡散層の不
純物分布がガウス分布からはずれ急峻な不純物分布を実
現できなく、ベース幅を狭くする妨げになってきた。 
本発明は上記の問題を解消するためになされたもので、
より狭いベース幅を実現できる製造方法を提供すること
を目的とする。
Conventionally, in the manufacture of high-speed bipolar transistors, as described above, due to channeling, the impurity distribution in the base diffusion layer deviates from the Gaussian distribution, making it impossible to realize a steep impurity distribution, which has been an obstacle to narrowing the base width.
The present invention was made to solve the above problems.
It is an object of the present invention to provide a manufacturing method that can realize a narrower base width.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の製造方法は、埋込層形成時に該埋込層の真性ベ
ース直下の部分に他の部分より拡散係数の大きい不純物
をドーピングし、後の熱処理で拡散係数の大きい不純物
がセリ上がることを利用して、不純物分布が急峻で、狭
いベース拡散層を実現するものである。
In the manufacturing method of the present invention, when forming a buried layer, a portion of the buried layer directly below the intrinsic base is doped with an impurity having a higher diffusion coefficient than other portions, and it is possible to prevent the impurity having a high diffusion coefficient from rising during subsequent heat treatment. By utilizing this, a narrow base diffusion layer with a steep impurity distribution can be realized.

〔実施例〕〔Example〕

第1図は本発明の製造方法による高速バイポーラトラン
ジスタの一例の構造を示す。
FIG. 1 shows the structure of an example of a high-speed bipolar transistor produced by the manufacturing method of the present invention.

図において1,3,4.5.6.7は第2図の同一符号
と同一または相当する部分を示し、2aる。
In the figure, 1, 3, 4, 5, 6, 7 indicate the same or corresponding parts as the same reference numerals in FIG. 2, and 2a.

Pサブストレート1に対しN゛埋込層の不純物をドーピ
ングする際、真性ベース直下の部分に他の部分より拡散
係数の大きい不純物をドーピングし、その上にエピタキ
シャル層4を成長させ、素子分離のための分離拡散層3
を形成する。
When doping the P substrate 1 with impurities for the N buried layer, the part directly below the intrinsic base is doped with an impurity that has a higher diffusion coefficient than other parts, and the epitaxial layer 4 is grown on top of it to form an element isolation layer. Separation diffusion layer 3 for
form.

N゛埋込層2の真性ベース直下にドーピングした拡散係
数の大きな不純物は、その後熱処理により、図に示すよ
うにせり上がり、ボロンイオン注入によるベース拡散層
5の真性ベース部分のボロンイオンの拡散を抑え、不純
物分布を急峻にし、狭いベース幅の実現を助ける働きを
する。
The impurity with a large diffusion coefficient doped directly under the intrinsic base of the N buried layer 2 rises up as shown in the figure by heat treatment, and prevents the diffusion of boron ions in the intrinsic base portion of the base diffusion layer 5 due to boron ion implantation. It works to suppress impurity distribution, steepen the impurity distribution, and help realize a narrow base width.

以下のエミッタ拡散層6、コレクタ拡散層7、電極配線
の形成などは、従来の方法による。
The following formation of the emitter diffusion layer 6, collector diffusion layer 7, electrode wiring, etc. is performed by conventional methods.

C発明の効果〕 以上説明したように、本発明によれば、より狭いベース
幅を実現することができることとなり、バイポーラトラ
ンジスタのより高速化が計れるという効果がある。
C. Effects of the Invention] As explained above, according to the present invention, it is possible to realize a narrower base width, and there is an effect that the speed of the bipolar transistor can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の製造方法による高速バイポーラトラン
ジスタの一例の構造を示す断面図、第2図は従来のバイ
ポーラトランジスタの一例の構造を示す断面図、第3図
はボロンプロファイルの一例を示す説明図である。 1・・・Pサブストレート、2a・・・N゛埋込層、3
・・・分離拡散層、4・・・エピタキシャル層、5・・
・ベース拡散層、6・・・エミッタ拡散層、7・・・コ
レクタ拡散層 なお図中同一符号は同一または相当するi示す。 特許出願人 新日本無線株式会社 −xJ(u) 表面深さ 第3図
FIG. 1 is a cross-sectional view showing the structure of an example of a high-speed bipolar transistor manufactured by the manufacturing method of the present invention, FIG. 2 is a cross-sectional view showing the structure of an example of a conventional bipolar transistor, and FIG. 3 is an explanation showing an example of a boron profile. It is a diagram. 1...P substrate, 2a...N buried layer, 3
... Separation diffusion layer, 4... Epitaxial layer, 5...
- Base diffusion layer, 6... Emitter diffusion layer, 7... Collector diffusion layer Note that the same reference numerals in the drawings indicate the same or corresponding i. Patent applicant: New Japan Radio Co., Ltd.-xJ(u) Surface depth Figure 3

Claims (1)

【特許請求の範囲】[Claims]  埋込層形成時に該埋込層の真性ベース直下の部分に他
の部分より拡散係数の大きい不純物をドーピングし、該
埋込層の上記拡散係数の大きい不純物のせり上がりを利
用して不純物分布が急峻で狭いベース拡散層を形成する
ことを特徴とする高速バイポーラトランジスタの製造方
法。
When forming the buried layer, the portion directly below the intrinsic base of the buried layer is doped with an impurity having a higher diffusion coefficient than other portions, and the impurity distribution is adjusted by utilizing the rise of the impurity having a large diffusion coefficient in the buried layer. A method for manufacturing a high-speed bipolar transistor characterized by forming a steep and narrow base diffusion layer.
JP2148813A 1990-06-08 1990-06-08 Manufacture of high-speed bipolar transistor Pending JPH0444235A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2148813A JPH0444235A (en) 1990-06-08 1990-06-08 Manufacture of high-speed bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2148813A JPH0444235A (en) 1990-06-08 1990-06-08 Manufacture of high-speed bipolar transistor

Publications (1)

Publication Number Publication Date
JPH0444235A true JPH0444235A (en) 1992-02-14

Family

ID=15461290

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2148813A Pending JPH0444235A (en) 1990-06-08 1990-06-08 Manufacture of high-speed bipolar transistor

Country Status (1)

Country Link
JP (1) JPH0444235A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9675593B2 (en) 2012-10-02 2017-06-13 Intermune, Inc. Anti-fibrotic pyridinones

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9675593B2 (en) 2012-10-02 2017-06-13 Intermune, Inc. Anti-fibrotic pyridinones

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