JPH0443917Y2 - - Google Patents

Description

[Detailed explanation of the invention] (1) A plurality of performance operators for inputting pitch information and note length information of musical tones to be generated, and sequentially storing pitch and note length information input by the performance operators. a memory means; a plurality of operators provided respectively corresponding to a plurality of types of volume data; and a controller for sequentially reading pitch information stored in the memory means for each operation of any one of the plurality of operators. a musical sound generation instructing means for instructing the generation of a musical sound based on the pitch data read from the first reading means and the volume data corresponding to the operator operated for reading; storage control means for re-storing the pitch data together with the volume data and volume data in the original storage location of the storage means; and generating the musical tone by reading the pitch information, length information and volume information stored in the storage means. An electronic musical instrument comprising: second reading means that supplies the read pitch and volume information to the instruction means and repeats the operation of reading out the next information every time corresponding to the note length information. .

(2) The electronic musical instrument according to claim 1, wherein the plurality of operating elements are constituted by a part of the plurality of performance operating elements.

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an electronic musical instrument that is capable of writing and reading musical tone information to and from a memory.

[Prior art]

Conventionally, electronic musical instruments have been proposed in which pitch and length information of musical notes as musical tone information can be sequentially written into a memory in advance and read out later. Then, the volume of this musical tone information is set by an external switch etc. when reading out, or for example,
As shown in the figure, the settings are made by storing touch data representing volume information in a memory corresponding to each pronunciation information.

[Problems with conventional technology]

However, with the method of setting the volume using an external switch, etc. when reading out, the volume of the musical tone information that is read out sequentially is fixed to the set value, which results in poor performance expression compared to an actual performance where the volume differs for each musical tone. Become. Also, although the method of storing touch data as volume information for each musical tone and reading it out does not have the drawbacks mentioned above, it is still necessary to control the touch strength when inputting each musical tone information. It is very difficult for beginners to obtain the desired volume.

[Purpose of the invention] The present invention was made against the background of the above-mentioned circumstances, and its purpose is to provide an electronic musical instrument that can set the volume of each musical tone read out without requiring skilled operations. be.

[Key points of the idea]

In order to achieve the above object, the present invention includes a plurality of performance operators for inputting pitch information and note length information of musical tones to be generated, and sequential storage of the pitch and note length information input by the performance operators. a plurality of controls provided respectively corresponding to plural types of volume data; and a plurality of controls for sequentially reading pitch information stored in the storage unit for each operation of any one of the plurality of controls. a first reading means; a musical sound generation instructing means for instructing the generation of a musical sound based on the pitch data read from the first reading means and the volume data corresponding to the operator operated for reading; , storage control means for re-storing the pitch data together with the volume data and volume data in the original storage location of the storage means; and a storage control means for reading out the pitch information, length information and volume information stored in the storage means to produce the musical tone. A second readout means that supplies the read pitch and volume information to the generation instruction means and repeats the operation of reading out the next information every time corresponding to the note length information. It is.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a part of the keyboard 1 of an electronic musical instrument, of which 13 black keys are used to specify the volume generated during automatic performance or to write volume information, and are used to select the scale F# ₄ ,
G# ₄ and A# ₄ are pp (pianissimo) designated key 2...
C# ₅ , D# ₅ , p (piano) designated key 3..., F# ₅ ,
G# ₅ , A# ₅ is n (normal) designated key 4..., C# ₆ ,
D# ₆ is f (Forte) specified key 5..., F# ₆ , G# ₆ ,
A# ₆ is ff (fortetsusimo) specified key 6...

A mode designation key (not shown) is provided above the keyboard 1 to designate each mode such as normal manual performance, automatic performance, musical tone information writing, on-length off-length information writing, and volume information writing. The mode designation key and operation signals from the keyboard 1 . . . are converted into key codes and input to the control section 7 in FIG. 2.

The control section 7 includes a control ROM (read only memory) 8, an address decoder 9, an internal RAM (random access memory) 10, an arithmetic section 11, and a time control section 12.

Among these, the control ROM 8 stores flows to be described later, and each time one process is performed, the address decoder 9 is incremented, and the flow processes are performed one after another. In addition, in the calculation section 11, the above-mentioned control
Arithmetic processing is performed based on the flow read from ROM8, and intermediate data etc. in that case are stored internally.
Temporarily stored in RAM10. Further, the time control section 12 controls the length of the musical tones to be produced, such as the on-length and off-length.

Then, under the control of this control unit 7, the sub ROM 1
3 is read and the external RAM 14 is accessed. Of these, data determining the envelope waveform, such as the attack peak level, is read out from the ROM 13, inputted to the internal RAM 10, and then given to the envelope generator 15.
In addition, data such as pitch, tone length, on length, off length, etc. are written to the external RAM 14 by the control unit 7, and are read out under the control of the control unit 7, and are used to control the frequency generator 16 and envelope generator. 15.

The frequency generator 16 has a latch 17, a counter 18, and a waveform ROM 19 for forming frequency information according to the pitch of a musical tone.
Waveform data is read out from 9 under the control of the counter 18 and input to the multiplier 20 .

The envelope generator 15 also includes a latch 21, an up-down counter 22, and a ladder 2, which form envelope information according to the set tone of the musical tone.
3, an attack waveform is formed when the up-down counter 22 counts up, a sustain waveform is formed when the up-down is stopped, and a release waveform is formed when the up-down counter 22 counts down, and each envelope data is input to the multiplier 20.

The multiplier 20 multiplies the waveform data and envelope data and outputs the result as musical tone data, thereby generating and emitting musical tones.

FIG. 3 is a detailed circuit diagram of the main part of FIG. , RAM addressing circuit 33, main gate 34, and black key decoder 35, and these circuits 32, 33, 34, 35
are driven according to each mode. In addition, the operation signal for each key from the keyboard 1 is sent to a decoder 31.
is converted into a key code, and the above external code shown in Figure 4 is converted to a key code.
Pitch area 14a of each address of RAM 14...
or the frequency generator 1
6 is input.

Furthermore, the above volume specified black keys 2..., 3..., 4
The operation signals of ..., 5..., 6... are also sent to the decoder 31.
After being converted into a key code by the black key decoder 35, the code is further converted into a volume designation code and inputted to the ROM address designation circuit 36, or the volume area 14b of each address of the external RAM 14 shown in FIG. It is written sequentially to black keys 2, 3...
When the sound volume is not designated by..., the black key decoder 35 automatically outputs the n (normal) volume designation code.

Further, the operation signals of each key from the keyboard 1 are input as they are to the time control section 12, which is composed of an on/off determination circuit 37, an on length timer 38, and an off length timer 39. There is. The operation signal of each key is input to the on/off determination circuit 37, which determines whether each key is pressed or released.The a terminal of this circuit 37 outputs "1" (binary value) for a certain period of time after the key is pressed. Similarly, from the b terminal, the a terminal outputs "1" and during the key press until the key is released, "1" is output, and from the c terminal, "1" is output for a certain period of time after the key is released. is output. Outputs from terminals a, b, and c are applied to the ROM address designation circuit 36, and outputs from terminals a and c are input to on-length timer 38 and off-length timer 39, respectively.

This on-length timer 38 counts the time from key depression to key release, and this count value, that is, on-length data, is given to the selection circuit 40, or the on-length timer of each address of the external RAM 14 shown in FIG. The data is sequentially written into areas 14c...
In addition, the off length timer 39 counts the time from key release to next key press, and this count value, that is, off length data is stored in the external RAM shown in FIG.
The off-length areas 14d of each of the 14 addresses are sequentially written. At the end of the song, an end mark is written by operating a predetermined key.

The external RAM 14 receives the read command signal R and write command signal W from the R/W control circuit 32 and the address signal from the address designation circuit 33.
Data is accessed to each of the areas 14a, 14b, . . . . And pitch area 14a
The key code, that is, the pitch data read out from .
It is applied to the ROM address designation circuit 36. This sub-gate 41 is controlled to open and close by a gate signal from the main gate 34. Further, the on-length data read from the on-length areas 14c... is given to the selection circuit 40 and inputted to the adder 42, and the off-length data read from the off-length areas 14d... is also fed to the adder 42. 42.

This adder 42 performs addition of on-length data and off-length data, and the added data is provided to a matching circuit 43. This coincidence circuit 43 is also given the output of a timer 44 which is reset and started by the coincidence output of the coincidence circuit 43, and the coincidence output of this coincidence circuit 43 is input to the RAM address designation circuit 33 to control the address increment. will be done.

On the other hand, the address signal of the ROM address designating circuit 36 is applied to the sub ROM 13 to designate each area, and this area is divided into the attack time area 13a and the release clock area 13.
b. Five attack peak level areas 13c~
The weight is 13g. The attack time area 13a stores attack time data AT of the envelope waveform, and the release clock area 13a stores attack time data AT of the envelope waveform.
Clock cycle data RC for decrementing an envelope counter that determines the slope of release of the envelope waveform is stored in b. There are also five attack peak level areas 13c to 13.
In g, the peak level data APL of the attack envelope is set in five levels, each with volume levels pp (pianissimo), p (piano), and n.
(normal), f (fuorte), ff (fuortetsusimo)
It corresponds to

Of these areas, the attack timer area 13a and the attack peak level areas 13c to 13g are controlled by the on/off determination circuit 37.
Of the signals given to the ROM address designation circuit 36, it is designated when the a terminal output becomes "1",
Similarly, the release clock area 13b is designated when the output from the c terminal becomes "1". this sub
Each data read from the ROM 13 is stored in the attack time register 10 in the internal RAM 10.
a, written to attack peak level register 10b and release clock register 10c.

In the selection circuit 40, either the on-length timer 38 or the on-length data from the on-length area 14c of the external RAM 14 is selectively outputted by the selection signal from the main gate 34, and is given to the sustain time calculation circuit 45. This sustain time calculation circuit 45 is connected to a sub-assembly via a latch 46.
The attack time data AT from the attack time area 13a of the ROM 13 is also given, and sustain time data ST is calculated by subtracting the attack time data from the above-mentioned on-length data.
It is written to the sustain time register 10d of the RAM 10. Alternatively, an envelope count data register 10e is also provided in the internal RAM 10, and envelope count data ECD from an envelope counter 53, which will be described later, is sequentially written.

Further, the internal RAM 10 is also provided with a mode register 10f and a key status register 10g. Of these, the mode register 10f is supplied with eight types of designated mode data from the decoder 31, from the first to the eighth designated by the mode designating key. Also, key stator register 10g
a, from the on/off determination circuit 37,
At the start of key-on based on each terminal output of b and c,
Data for four states are sequentially written: during key-on, at the start of key-off, and during key-off.

Attack time register 1 of this internal RAM 10
Each data read from the attack peak level register 10b and the attack peak level register 10b is input to the arithmetic circuit 47, and the value obtained by dividing the attack time data AT by the attack peak level data APL, that is, the attack clock cycle data, is calculated. Envelope generator 15 is provided. Also, internal
Release clock cycle data RC from the release clock level 10c of the RAM 10 is also given to the envelope generator 15. The envelope generator 15 is made up of a latch 21, a counter 22, and a ladder 23 in FIG. 2, but more specifically, as shown in FIG.
8, 50, selection circuit 49, clock generator 51,
Timer 52, envelope counter 53, latch 54, peak level matching circuit 55, sustain timer 56, sustain matching circuit 57, and ladder 2
It consists of 3.

The attack clock cycle data from the arithmetic circuit 47 is applied to the selection circuit 49 via the latch 48, and the release clock cycle data from the release clock register 10c is also applied to the selection circuit 49 via the latch 50. It will be done. The selection circuit 49 selects and outputs either the attack or release clock cycle, depending on the presence or absence of a selection signal b from a sustain matching circuit 57, which will be described later, and supplies it to the clock generator 51. This clock generator 51 is also given the output of a timer 52 which is reset and started by the output of the clock generator 51, and one pulse is generated every time the output value of this timer 52 and the clock cycle from the selection circuit 49 match. is given to the envelope counter 53.

The incrementing envelope data of the envelope counter 53 is input to the multiplier 20 via the latch 54 and the ladder 23, and is sequentially written into the envelope count data register 10e in the internal RAM 10. Envelope count data from this envelope count data register 10e
The ECD and the attack peak level data APL are applied to a peak level matching circuit 55, and when the envelope count data ECD becomes equal to the attack peak level data APL, a matching signal is output and the clock output of the clock generator 51 is turned on. At the same time, the sustain timer 56 is reset and started.

The output of the sustain timer 56 is given to the sustain match circuit 57, and the sustain match circuit 57 is also given the sustain time data ST from the sustain time area 10d of the internal RAM 10, so that the output data of the sustain timer 56 becomes the sustain time data ST. When they become equal, a match signal is output, the sustain timer 56 is stopped, the selection output of the selection circuit 49 is selectively switched to the release clock cycle data RC, the clock generator 51 is restarted, and the envelope counter is started. 53 is decremented.

Next, the operation of this embodiment will be explained with reference to FIG.

First, when the power is turned on, the address decoder 9 of the control ROM 8 is initialized (step S ₁ ), and the contents of the internal RAM 10 are also cleared.
Now, if the first mode of normal manual performance only is designated using a mode designation key (not shown), the first mode data is set in the mode register 10f of the internal RAM 10, and when the first mode data is read, the first mode is 1 mode is determined (step S ₂ ), the key input signal of the mode designation key is converted into a key code by the decoder 31 and given to the main gate 34, and the main gate 34 sends a selection signal to the selection circuit 40. a is given.

Next, when a key press is detected by key sampling and the key input signal is given to the on/off determination circuit 37, the a terminal output becomes "1", and this "1" signal is sent to the on-length timer 38. is input to start time control, and the internal RAM
Data indicating that it is now time to start key-on is written into the key stator register 10g of No. 10 (steps S ₃ , S ₅ , S ₆ ). In this case, since it is manual performance, the write operation in step _S4 is not performed.

Then, the contents of the key status register 10g are read out to determine whether the key has just been turned on (step _S7 ), and the data at the start of the key-on is read out, so the process returns to step _S2 again.
The mode is determined, and time control, key sampling, and key status determination are performed again (steps S ₂ , S ₃ to S ₇ ), but this time the contents of the key status register 10g are changed after the key-on start time. Because the data indicates that the key is on,
The process advances to step _S8 , key code set processing.

That is, the key code from the decoder 31 is input to the frequency generator 16, and the waveform data is input to the multiplier 2.
0 (steps S ₈ and S ₉ ).

At the same time, the n (normal) volume designation code is automatically output from the black key decoder 35.
The attack peak level data APL of n is applied to the ROM address designation circuit 36 (step _S10 ).
and attack time data AT are read out from the attack peak level area 13e and attack time area 13a of the sub ROM 13, and are stored in the internal RAM 1.
At the same time, the attack time data AT is written to the attack peak level register 10b and the attack time register 10a of 0, and is applied to the sustain time calculation circuit 45 via the latch 46.

Next, the attack time register 10a and attack peak level register 10b of the internal RAM 10 are
Performance circuit 4 based on the data AT and APL from
7 sets the attack clock cycle data (AT/
APL) is calculated, the latch 48 and the selection circuit 49
Each time the count of the timer 52 becomes equal to the attack clock period data (AT/APL), one pulse is given to the envelope counter 53 and incremented, and the envelope count data is
The ECD is sequentially sent to the multiplier 20 via the latch 54 and the ladder 23 (step S ₁₁ ), and is also sequentially written into the envelope count data register 10e of the internal RAM 10. In this manner, the multiplication section 20 multiplies the above-mentioned waveform data and envelope count data, and begins to generate and emit musical tones.

Then, when the envelope count data ECD becomes equal to the attack peak level data APL, a match signal is output from the peak level matching circuit 55, the output of the clock generator 51 is stopped, and the sustain timer 56 starts time counting. The counter 53 also maintains a count value equal to the attack peak level data APL, and the envelope musical sound waveform transitions from the attack state to the sustain state.

Next, when key 1 is released, the c terminal output of the on/off determination circuit 37 becomes "1", this "1" signal is input to the on-length timer 38, and the on-length timer 38 outputs the "1" signal. outputs on-length data and is applied to a sustain time calculation circuit 45 via a selection circuit 40 to which a selection signal a is applied,
The sustain time calculation circuit 45 calculates the sustain time data ST by calculating (on length data) - (attack time data AT).
It is written to the sustain time register 10d of the RAM 10.

Next, the sustain time data ST from the sustain time register 10d is given to the sustain matching circuit 57, and the above-mentioned sustain timer 5
When the output of the sustain timer 56 becomes equal to the sustain time data ST, a match signal is output and the sustain timer 56
The selection circuit 49 stops the time count of
is switched to b selection, the clock generator 51 is restarted, and the envelope counter 53 is switched to decrement.

At this time, since the c terminal output "1" of the on/off determination circuit 37 is also given to the ROM address designation circuit 36, the release clock cycle data RC is often outputted from the release clock area 13b of the sub ROM 13. The release clock cycle data RC is written into the release clock register 10c of the internal RAM 10, and the release clock cycle data RC is applied from this register 10c to the selection circuit 49 via the latch 50.

Therefore, by switching the selection of the selection circuit 49,
The clock generator 51 is given release clock cycle data RC, and the envelope counter 53 starts decrementing at the cycle of this cycle data RC, causing the envelope musical sound waveform to transition from the sustain state to the release state.

In this way, the sound for one musical note is emitted, and each time the operating keys are switched one after another, time control, key sampling, key status setting, key-on start determination, mode determination (steps S ₃ , S ₅ to S ₇ , _S2 )
processing is performed, and musical tones are generated and emitted (steps S ₈ ~
S ₁₁ ) is repeated. In this case, since it is still a manual performance, the automatic performance control operation of step _S12 is not performed.

Next, when the mode designation key is switched to the second mode for writing the pitch, on length, and off length, the second mode data is set in the mode register 10f of the internal RAM 10, and the key input for this mode designation is The signal is converted into a key code by a decoder 31 and given to an R/W control circuit 32, a RAM address designation circuit 33, and a main gate 34. Then, a write command signal W is given from the R/W control circuit 32 to the external RAM 14, and the RAM address designation circuit 33 sends a write command signal W to the external RAM 14 for each subsequent key operation.
14 addresses are incremented by 1, and the main gate 34 supplies a selection signal a to the selection circuit 40.

Next, when a key is pressed, the a terminal output of the on/off determination circuit 37 becomes "1", the on-length timer 38 is driven, time control is started, and key sampling is started in the same way as in the first mode described above. data indicating the key-on start time is written to the key status register 10g (step _S3 ,
_S5 , _S6 ). Here, a determination is made as to when to start key-on (step _S7 ), and since it is now time to start key-on,
A mode determination is made (step _S2 ).

Next, the decoder 31 decodes the key input signal from the key operation into a key code, and the black key decoder 35 automatically outputs the n (normal) volume designation code. The data is written in the area 14a and the volume area 14b (steps _S13 , _S14 ).

Then, the on-length area 14 of the external RAM 14
c. After the off-length area 14d is addressed (step _S15 ), the above-mentioned time control, key sampling, and key status setting are repeated (steps _S3 , _S5 , _S8 ), but this time the key status is Since the contents of the register 10g are the data during key-on, the key code is input to the frequency generator 16 in the same way as in the first mode described above.
The waveform mode is sequentially sent to the multiplier 20, and the attack time data AT,
Attack peak level data of n (normal)
The APL is written, envelope data is created and sent to the multiplier 20, and generation and emission of musical tones is started (steps S ₈ and S ₁₁ ). In this case, since data writing control is being performed, automatic performance control in step _S12 is not performed.

Thereafter, the operations from steps _S3 to _S11 are repeated, and when the operation key is released, the c terminal output of the on/off determination circuit 37 becomes "1" and the time count of the on length timer 38 starts. is completed, and the on-length data is stored in the on-length area 1 of the external RAM 14.
4c, at the same time the off length timer 39 starts counting, and the selection circuit 4
0 to the sustain time calculation circuit 45, and in the same manner as in the first mode, the envelope waveform sustain and release are also formed and the sound is emitted.

Next, when the next key is operated, the a terminal output of the on/off determination circuit 37 becomes "1", the time count of the off length timer 39 ends, and the off length data is stored in the off length area 14d of the external RAM 14.
At the same time, the on-length timer 38 starts counting (steps S ₃ and S ₄ ).

Then, key sampling, key status setting, and determination of when to start key-on are made again (steps _S5 to _S7 ), and now it is time to start key-on.
The mode is determined again (step S ₂ ), a new key code for the operation key, and a volume designation code for n (normal) are written (steps S ₁₃ , S ₁₄ ).
In the same way, each data writing of the ON length and OFF length of the new operation key and the generation and emission of musical tones are repeated (steps _S15 , _S3 to _S11 ), and the same operation is performed every time the key is operated thereafter. It's repeated.

Next, change the mode specification key to the second
When you switch to the third mode, which reads the pitch data and volume data written in the mode and plays them (one-key play) with each predetermined key press, the internal
The third mode data is set in the mode register 10f of the RAM 10, and the key input signal specifying this mode is converted into a key code by the decoder 31 and sent to the R/W control circuit 32, RAM address designation circuit 33, and main gate 34. Given. Then, the read command signal R is given from the R/W control circuit 32 to the external RAM 14, the RAM address designation circuit 33 is incremented for each one-key play, and the main gate 34 in turn gives a selection signal b to the selection circuit 40. The sub-gate 41 is opened.

Then, when the one-key key operation starts,
Key sampling is performed in the same manner as in the second mode described above, and data at the start of key-on is written to the key status register 10g (step _S5 ,
_S6 ). In this third mode, the internal RAM is already
Since the on-length and off-length data are determined by the on-length data and off-length data written in step 14, the time control and writing of on-length data and off-length data in steps _S3 and _S4 are not performed.

Then, based on the contents of the key status register 10g, a determination is made as to when to start key-on (step
S ₇ ), since it is now the key-on start time, the mode is determined (step S ₂ ).

Next, a key code based on the one-key play operation is output from the decoder 31, the RAM address designation circuit 33 is stepped, and the key code, that is, volume data is output from the pitch area 14a of the external RAM 14, and the volume designation code, that is, the volume data is output from the volume area 14b. Each data is read out (step
_S16 , _S17 ). Next, the mode is determined based on the contents of the mode register 10f (step _S18 ), and now the third
mode, key sampling, key status setting, and key-on start determination are performed again (steps _S5 to _S7 ), but this time the contents of the key status register 10g are rewritten from the key-on start to during the key-on. The read pitch data is sent to the frequency setter 16 to form a musical waveform (steps S ₈ and S ₉ ), and the volume data is sent to the ROM address designation circuit 36 via the subgate 41 (step S 8 and S 9 ). _S10 ), attack peak level data according to this volume data
APL is read from sub ROM13 and internal
Written to RAM10. Also, sub ROM1
3, attack time data AT is read out and written into the internal RAM 10, and is also given to the sustain time calculation circuit 45.The sustain time calculation circuit 45 uses this attack time data
Sustain time data is determined by AT and on-length data from the external RAM 14 via the selection circuit 40.
ST is calculated and written to internal RAM 10.
Furthermore, release clock cycle data RC is also read out from the sub ROM 13 and written into the internal RAM 10. In this way, each data written in the internal RAM 10 is applied to the envelope generator 15 to form an envelope waveform (step S ₁₁ ).

Thereafter, the operations from steps _S5 to _S11 are repeated in the same way, musical tones are generated and emitted, and when one key is operated anew, it is determined at step _S7 that it is time to start key-on. The mode is determined (step _S2 ), the pitch data and pitch data are read out again (steps _S16 , _S17 ), and musical tones are generated and emitted (steps _S18 , _S5 to _S11 ). .
In this case, the automatic performance control process in step _S12 is not performed.

Next, the pitch data, volume data, etc. written in the second mode are read out and played for each one-key play operation, and the on-length data and off-length data are rewritten into on-length and off-length data by one-key operation. The case of switching to 4 mode will be described.

In this fourth mode, almost the same processing as in the third mode described above is performed, but the selection signal of the main gate 34 becomes a, and the ON length is changed to the timing of the actual one-key operation after the mode determination in step _S18 . Count, off length count is done (step S ₁₅ ,
_S3 ), whose on-length data and off-length data are external
While being written to RAM14 (step
S ₄ ), the only difference is that a corresponding envelope waveform is formed.

Next, the pitch data written in the second mode etc.
A case will be described in which a switch is made to the fifth mode in which the volume data and the like are read out and played while specifying the volume by operating the black keys 2, 3, . . . .

By switching the mode designation key to the fifth mode, the fifth mode data is set in the mode register 10f of the internal RAM 10, and this mode designation key input signal is converted into a key code by the decoder 31 and R/W control is performed. The signal is applied to a circuit 32, a RAM addressing circuit 33, and a main gate 34. Then, from the R/W control circuit 32 to the external RAM
14 is given a read command signal R, the RAM address designation circuit 33 is incremented every time the black keys 2, 3, . . . are operated, and the main gate 34 is given a selection signal b to the selection circuit 40.

Next, depending on the desired sound output volume, pp (pianissimo) specified key 2..., p (piano) specified key 3...,
The n (normal) designated key 4 . Then, key sampling is performed, and the key-on start data is stored in the key status register 10.
g (steps S ₅ , S ₆ ). This fifth
In the case of mode, the on length and off length are determined by the on length data and off length data already written in the internal RAM 14, so steps S ₃ and S ₄
time control and writing processing of on-length data and off-length data are not performed.

Then, based on the contents of the key status register 10g, a determination is made as to when to start key-on (step _S7 ), and since it is now time to start key-on, a mode determination is made (step _S2 ).

Next, the black key decoder 35 decodes each black key 2, 3.
The volume designation code from pp to ff, that is, the volume data, is output (step _S19 ), and
The RAM addressing circuit 33 is incremented and the external
The key code, that is, the volume data is read out from the RAM 14 (step _S20 ). Next, a mode is determined based on the contents of the mode register 10f (step _S21 ), and since the mode is now in the fifth mode, key sampling, key status setting, and key-on start determination are performed again (steps _S5 to _S7) . ), since the contents of the key status register 10g have been rewritten from the time the key was turned on until the key was turned on, the pitch data read above is stored in the frequency generator 1.
6 to form a musical sound waveform (step _S8 ,
S ₉ ) as well as pp to ff from the black key decoder 35
The volume data up to the ROM address designation circuit 36
(Step S ₁₀ ), and the attack peak level data corresponding to the volume data from pp to ff is
APL corresponds to area 13c of sub ROM 13~
13g and written to the attack peak level register 10b of the internal RAM 10.
Also, attack time data from sub ROM13
AT is read out and written to the internal RAM 10, and is also given to the sustain time calculation circuit 45, where the sustain time calculation circuit calculates the sustain time based on this attack time data AT and the on-length data from the external RAM 14 via the selection circuit 40. Data ST is calculated and written to internal RAM 10. Furthermore, the release clock cycle data RC is also read out from the sub ROM 13 and internally
Written to RAM10. Thus, inside
Each data written in the RAM 10 is applied to the envelope generator 15 to form an envelope waveform (step S ₁₁ ).

In this case, the amplitude of the envelope waveform also changes as shown in Figure 6 due to the five levels of data written in the attack peak level register 10b of the internal RAM 10, from pp to ff, depending on the volume, and eventually the pp specified key is changed. By operating any key from 2... to ff designated key 6..., the sound output volume is also controlled in five levels.

From then on, repeat steps S ₅ to S ₁₁ .
The above operations are repeated, musical tones are generated and emitted, and when black keys 2, 3, etc. are operated anew, it is determined in step _S7 that it is time to start key-on, and the mode is determined ( Step _S2 ), the black key decoder reads the pitch data again (Steps _S19 , _S20 ), and generates and emits musical tones at volumes corresponding to the operated black keys 2, 3, etc. (Steps _S18 , S20). S ₅
~ _S11 ). In this case, the automatic performance control process in step _S12 is not performed.

Next, the pitch data written in the second mode etc.
While specifying the volume by operating black keys 2, 3, etc., the volume data etc. are read out and played,
A case will be described in which the mode is switched to the sixth mode in which data regarding the specified volume is newly written.

This sixth mode and the seventh mode described below are the most important functions of the present invention.

This sixth mode performs almost the same processing as the fifth mode described above, but differs in the following points. That is, in the fifth mode, the black key decoder (step
In the _sixth mode, after the mode determination in step _S21 , the external RAM is
The volume designation code is written in the volume area 14b of 14 (step _S22 ).

Next, write the volume data in the 6th mode,
A case will be described in which the pitch data, on length data, and off length data written in the second mode etc. are read out by a predetermined key operation and switched to the seventh mode where automatic performance is performed.

In this seventh mode, unlike the third to sixth modes in which musical tones are emitted every time a key is operated, all musical tones written in a predetermined key operation are automatically played to the end.

By switching the mode designation key to the seventh mode, the seventh mode data is set in the mode register 10f of the internal RAM 10, and this mode designation key input signal is converted into a key code by the decoder 31 and R/W control is performed. The signal is applied to a circuit 32, a RAM addressing circuit 33, and a main gate 34. Then, from the R/W control circuit 32 to the external RAM
14 is given a read command signal R, the RAM address designation circuit 33 is sequentially stepped by automatic performance control to be described later, and the main gate 34 gives a selection signal b to the selection circuit 40 and opens the sub-gate 41.

Next, when a predetermined key operation for automatic performance is performed, key sampling is performed and key-on start data is written to the key status register 10g (steps _S5 , _S6 ). In the case of this seventh mode as well, since the on length and off length are determined by the on length data and off length data already written in the internal RAM 14, the time control in steps S ₃ and S ₄ , the on length data and the off length data are determined. No long data write processing is performed.

Then, based on the contents of the key status register 10g, a determination is made as to when to start key-on (step _S7 ), and since it is now time to start key-on, a mode determination is made (step _S2 ).

Next, pitch data, volume data, ON length data, and OFF length data are read from the external RAM 14 (step _S23 ), and from then on, key sampling, key status setting, and key-on start time are performed in the same manner as in the third mode. A determination is made (steps _S5 to _S7 ), and a musical tone is generated and emitted (steps _S8 to S7).
_S11 ).

However, in this case, the volume data corresponding to the volume from pp to ff read from the internal RAM 14 is sent to the ROM address designation circuit 3 via the subgate 41.
6, an envelope waveform whose volume changes in five steps from pp to ff as shown in FIG. 6 is output in the same manner as in the fifth mode.

In this way, the sound volume also changes internally as the automatic performance progresses.
Automatically controlled based on volume data from RAM14.

Then, when one address of the internal RAM is read out, the adder 42 adds the on-length data and the off-length data, and the added data is given to the matching circuit 43, so the time count value of the timer 44 is set to this value. It becomes equal to the addition data, and the matching circuit 43
The RAM addressing circuit 33 is incremented by one step, and thereafter steps _S5 to _S11 are repeated.
Even if there is no key-on, the address of the external RAM 14 is automatically incremented (automatic performance control) (step _S12 ), and musical tones are sequentially generated and emitted.

Next, if other key operations such as tone specification or rhythm specification are performed, key sampling (step
S ₅ ), the 8th
The mode data is set (step _S6 ), the moment of key-on is determined (step _S7 ),
After mode determination (step _S2 ), processing such as tone color setting and rhythm setting is performed according to the key (step _S24 ). In this case, the other steps S ₃ , S ₄ ,
Processing from S ₈ to S ₁₂ is not performed.

Further, even if one-key play is performed by switching to the third or fourth mode after writing the volume data to the internal RAM 14 in the sixth mode, the sound is emitted at the sound volume based on the written volume data.

Furthermore, if only constant volume data n (normal) is written in the second mode and then switched to the seventh mode, automatic performance will be performed with the volume constant.

[Effect of idea]

As described above, the present invention stores musical tone information consisting of pitch and length information in advance using a plurality of performance operators, and sequentially reads out this musical tone information by operating any of the performance operators. By adding the volume data corresponding to the operator and re-memorizing it when the music is played, the volume can be set individually for each piece of musical tone information, thereby enriching the performance expression. Moreover, since the volume value that is set is determined by which controller is operated, it is possible to set the volume to the performer's intended volume, and even beginners can easily set it without the need for skilled operation as in the past. This has the effect of allowing you to set the volume.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention, and FIG. 1 shows a keyboard 1 showing black keys 2, 3, etc. for specifying volume.
Figure 2 is a schematic block circuit diagram inside the electronic musical instrument, Figure 3 is a detailed circuit diagram of a part of Figure 2, Figure 4 is a diagram showing the contents of the external RAM 14, Figure 5 is a volume diagram. Data writing such as data (volume specification code),
A flowchart diagram showing the process of reading out and generating and emitting musical sounds, Figure 6 shows pp (pianissimo), p (piano),
It is a figure which shows the envelope waveform corresponding to each volume of n (normal), f (fuorte), and ff (fuortetsusimo). 1...keyboard, 2...pp specified key, 3...p specified key, 4...n specified key, 5...f specified key, 6...ff
Designated key, 7...Control unit, 10...Internal RAM, 1
0b...Attack peak level register, 13c
~13g...Attack peak level area, 13
...Sub ROM, 14...External RAM, 14b...
...Volume area.