JPH0443677A - Semiconductor device - Google Patents

Abstract

PURPOSE:To easily manufacture this device and to enhance the integration density of elements by a method wherein the shape of a trench hole is formed to be an inverted truncated pyramid whose cross section is square and whose cross-sectional area becomes smaller as the hole becomes deeper. CONSTITUTION:A silicon oxide film 2 is formed on a P-type silicon semiconductor substrate 1; a resist pattern is formed on the oxide film 2; a reactive ion etching (RIE) operation is executed by making use of the silicon oxide film 2 or the resist pattern as a mask; a plurality of vertical trench holes 3 are formed; insulating oxide films 4 of such as, e.g., SiO2 are deposited in the holes 3; the oxide film 2 is etched and removed. Then, trench holes 5 whose cross section is square and whose shape is an inverted truncated pyramid are formed between the insulating oxide films 4 for element isolation use by using, e.g., an RIE operation or the like.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object 1-1 of the Invention] (Field of Industrial Application) The present invention relates to a trench structure of a semiconductor device.

(Conventional technology) Higher density of semiconductor devices such as IC and LSI.

As the degree of integration increases, it is becoming increasingly difficult for conventional planar semiconductor devices to adequately support semiconductor devices, and there are growing expectations for miniaturization technology that utilizes vertical trenches. For example, trench capacitors have made it possible to increase the size of the device without increasing the device area, and trenches have been used for cable isolation] - Trench capacitors are expected to contribute to future miniaturization technology. has been done. Further, the use of trench holes for transistors 1 to 1 in an inverter is also being considered. An inverter is a basic circuit of a semi-semiconductor collector circuit, and is used in MOS circuits, but basically the circuit is constructed using two transistors.

The basic circuit of the inverter is shown in FIG. [The transistor Tr+ is a substitute for a load resistor, and transistors 1 to T and □ are switching transistors that are turned on and off by input.

Conventionally, the transistors used in the basic circuit of the MOS inverter as described above have been planar type. Since the inverter circuit using the Brainer type 1-transistor has a planar shape, it is possible to have a free pattern layout, but with the current trend toward higher integration, it has become difficult to use in terms of miniaturization.

Therefore, it has been considered to use a trench structure, but the manufacturing process is complicated, so there is no way to put it into practical use.
This will be explained using a capacitor as an example. FIG. 25 is a cross-sectional view of a conventional trench capacitor. First, a silicon oxide film 104 is formed in the element region, and n- regions 103 are formed in necessary parts. Using this oxide film as a mask, trench holes 101 are formed in the intended element isolation region of the silicon substrate 100 by RIE.
form.

Next, As impurities are thermally diffused from the inner surface of the trench hole 101 to form an n- layer 103 on the side walls and bottom thereof.

Next, the inside of the trench hole is further etched by RIE to remove the n-Jl at the bottom of the trench. Next, the bottom of the hole is doped with B (boron) by ion implantation to form a ρ-layer 102.

Furthermore, capacitor insulation 11 is applied to the inner surface of the trench by thermal oxidation. After forming a105, polysilicon 106
is deposited on the entire surface and P (phosphorus) is diffused. Oxide film 10
The polysilicon formed on 4 is removed by etching. Vertical techniques such as trenching are extremely difficult to control. L-wrench is 1-reactive ion etching (
However, it is difficult to form the n-layer vertically, and it is very difficult to form the n-layer along the sidewalls by ion implantation.

(Problems to be Solved by the Invention) As described above, integrated circuits using conventional Brenna type elements cannot support the above-mentioned high integration, and control is difficult with the conventional one-wrench technology. There were many problems to be solved. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that can sufficiently cope with high integration by employing a trench having a novel structure.

[Structure of the invention]

(Means for Solving the Problems) The present invention relates to a semiconductor device, such as a MOS inverter, which is provided with at least one trench hole, and the trench hole has a rectangular cross section; The trench is characterized by an inverted truncated pyramid shape in which the cross section +fii product decreases as it gets deeper.9 (Function) Because the trench structure is an inverted truncated pyramid shape, the side walls of the trench are not vertical but are inclined. Similar to the Zolena type formation means, etching and formation of an impurity layer are facilitated.

(Example 1) Hereinafter, an example of the present invention will be described with reference to the drawings. 1 to 12 show the manufacturing of the semiconductor device shown in Example 1.
- It is a sectional view explaining process. First, the surface of the 1) type silicon semiconductor substrate 1 is thermally oxidized to form a silicon oxide film (Sin2) 2 having a thickness of several thousand nanometers. Next, a photoresist 1- is applied onto the oxide film 2, and photoresist 1- is etched to form a resist pattern covering the area where the element is to be formed. Next, reactive ion etching (RIE) is performed using the silicon oxide film 2 or the resist pattern as a mask, and the silicon substrate 1 is etched to a depth of, for example, several thousand to 3 μs to form a plurality of vertical trench holes 3. (Fig. 1). An insulating oxide film 4 such as 5i02 is deposited in the hole 3 by CVD or the like to serve as an element isolation oxide film. The oxide film 2 is removed by etching (21st step j).

Next, an inverted truncated pyramid-shaped l.
The wrench hole 5 is formed such that, for example, 1<I E (Fig. -λ (a)). A perspective view of this trench hole 5 is shown in FIG. 3(b). At this time, the angle of inclination of the slope of the hole F3 is 60° for the human body. This inclination angle □ is not particularly limited to this angle.

0 is 1-i7 capable of selecting a wide range of O"<0<90". Finally, a trench? L 5 Caucasian i
At f+j, a film of 50 to 300 g of oxide is formed by thermal oxidation (FIG. 4). Next, 13 ions are injected into the silicon substrate i through the trench hole 5 to form an oxide film on the gate 1 (underneath the p- layer 7 which will become the channel part).
(Figure 5). Then, a polysilicon film 8 of about 3,000 to 4,000 layers is formed on the entire surface of the silicon substrate 1 using the CV l'D method (Fig. 6).
An unnecessary portion of the polysilicon film 8 is etched away by RIE or the like using EP, and a gate electrode 9 is formed at the bottom of the trench hole 5 (FIG. 7). Next, As ions are implanted under the oxide film 6 through the 1- trench hole 5 to change the P- layer on the side wall portion of the trench hole 5 to an n+ layer, and these portions are used as the source region 10 and the drain region 11 ( Figure 8). Next, an interlayer insulating film 12 is formed.

Silicon oxidation (Sin,
) Deposit the film 12 uniformly (FIG. 9). This silicon oxide film 12 is etched by RIE to form a contact hole in the trench hole 5'' and to form a contact hole in the drain region 11.
, the source region 10 is partially abandoned. Next, the interlayer insulating oxide film 12 on the element isolation oxide film 4 is partially etched by a photoetching process (PEI) or an etching back process, and this part is removed, and at the same time, the corners of the element isolation oxide film are shaved. The same slope as the side wall of the trench hole 5 is formed. This slope and element isolation oxide film.

An electrode metal film 13 made of AQ or the like including a barrier metal is uniformly formed on the silicon substrate 1 including an interlayer insulating oxide film etc. by a deposition technique such as sputtering.
Figure 11). After that, using a resist pattern formed by PEP etc. as a mask, RIE etc.
The element is completed by forming the electrode 14 consisting of fi (first
Figure 2) Figures 13 (a), (b), and (C) are plan views of one transistor formed through six or more manufacturing steps, and the AA' cross-sectional view of Figure 13 (a) is shown in Figure 13 (a), (b), and (C). This is shown in Figure 13(d).

13(,) shows a plan view of the source and train electrodes, FIG. 13(b) shows a plan view of the source and drain regions, FIG. 13(e) shows a plan view of the gate region, and FIG. Figure 13(d) shows these cross-sectional views.

The two MOS transistors are used to form the inverter shown in FIGS. 14 and 15.

FIG. 14(a) shows the pattern layout of an N-channel E/E type inverter on a silicon substrate.
b) shows its equivalent circuit. The source of N-channel enhancement type transistor N1 and the drain of N-channel enhancement type transistor N2 are connected, and the gate and drain of No are connected. FIG. 15 shows an N-channel depletion type transistor N (
D) and N-channel enhanced men i-type! - Silicon substrate of inverter combined with transistor N (E)] ilZ with second pattern layout
They are a top view ((a) figure) and its equivalent circuit ((b) figure).

In the step of forming the electrode 14, the metal film 13 is formed on the silicon substrate. In the example of 2L, the element isolation oxide film 4
”The second interlayer insulating oxide film is eliminated. In this way, the element surface is flattened and the metal IPJI 3 is also flattened, making it easier to process fine electrode wiring. However, the second part of P E I) or etchback is added.
2゜However, the process becomes complicated (see Figure 11).
It is possible to proceed with the subsequent steps without performing this step. That is, as shown in FIG. 16, the element Ml! li
An AQ film 13 is deposited with the interlayer insulating oxide film 12 of the I oxide film 4-[- kept as it is, and this is patterned to form the 17th
AQ electrode wiring 14 as shown in the figure can be formed.

As in the previous example, when the interlayer insulating film of element isolation oxide PIA 7 is removed, the adjacent diffusion layer (
In the case of an N-channel transistor, the n+ layer and the n middle layer,
In the case of CMO5, for example, the field inversion voltage between the N+ layer and P+ layer may decrease, but this can be easily controlled by adjusting the thickness of the element isolation oxide film. . Additionally, the structure of the present invention has a better feel I--1 pressure than the Brehner type structure.

(Embodiment 2) Embodiment 2 shows an example in which the present invention is applied to a CMO5 logic circuit. Up to FIG. 3, proceed as in Example 1] and then, for example, as shown in FIG. Then, for example, p or As ions are implanted into the other side to form an N-well region (FIG. 13). On the silicon substrate treated in this way, interlayer insulation oxidation 1 12, ^g, electrode 1
A gate oxide film 6, an N layer, a P layer, and a gate electrode 9 are formed for each element region to form a complementary pair of elements (FIG. 19). , p
Although a type silicon substrate is used, if an n type silicon substrate is used, 13 ions or the like are implanted into the substrate 1 to form a P-well (FIG. 20). Then, as shown in FIG. 21, an n-channel device and a pair of devices including the n-channel device are formed (FIG. 21). Using this element, C
Examples of MOS inverter configurations are shown in Figures 22 (a) to (c).
). Figures (a) and (b) are examples of inverter pattern layouts formed on silicon substrates.
c) The figure shows its equivalent circuit.

The trench hole used in the present invention has a minimum size as shown in FIG. 23 (minimum size), and the size of the transistor is considered to be an extension of current brainer technology. That is, the gate length is at least 0
．． 5. A of the source and drain, which can be
The distance between the ρ electrode end and the gate end is approximately 0.2-.

Furthermore, the length of the AQ electrode inside the trench hole is approximately 0.6
/ffi. Furthermore, the width of the AQ electrode is approximately 0
．． 5 μs, of which the length inside the trench hole is approximately 0.3111 m. Therefore, the size of the trench hole [1] is approximately 1.5 mm on one side. becomes a rectangle.

The present invention can be considered as a lateral compression of current planar semiconductor devices. That is, as shown in FIG. 24, the substrate surface around the gate electrode, which was horizontal in the case of the planar type, rises up around the gate electrode. In Figure 0, all processing steps can be performed from above the silicon wafer, in other words, planar technology can be applied, making the process easier.
Let a be the minimum necessary contact and gate fringe margin for a Brainer type transistor, and let b be the contact distance between the contact and the diffusion layer. If a and b are maintained and the substrate plane is raised to form an inverted truncated pyramid shape, it becomes possible to increase the degree of integration by 20 minutes.

In addition, in the planar type, the interlayer insulating film is thick, so as shown in FIG. 26 (in the present invention, as shown in FIG. ), the AQ film has large undulations and the margin for patterning during PEP is small; however, by using the inverted pyramidal truncated trench hole of the present invention, the AQ film surface becomes flat and PEP processability improves. Furthermore, it contributes to improving the degree of integration.

Polysilicon for the gate electrode material is also Mo5iz.
+SuSi2. Of course, silicone 1- such as TiSi2+ Ta5j2 can also be used. Further, the present invention is not limited in application to the transistors of the inverter shown in the embodiments, but can be applied to any semiconductor device that can be used by forming a trench, such as a capacitor or an isolation device.

〔Effect of the invention〕

According to the present invention, with the above-described configuration, the manufacturing technology of a planar structure having a planar structure can be applied to the manufacturing of a semiconductor device having a trench structure, thereby facilitating manufacturing and improving the degree of integration of elements. .

[Brief explanation of the drawing]

Figure 1, Figure 2, Figure 3 (a), Figure 4, Figure 5, Figure 6
7, FIG. 8, FIG. 9, FIG. 10, FIG. 11, and FIG. ) is a perspective view of a trench hole in the present invention, FIG. 13(a). (b) and (c) are plan views of one transistor in the semiconductor device of the present invention, and (d) is a plan view of one transistor in the semiconductor device of the present invention.
), FIG. 14(a) is a plan view of the semiconductor device of Example 1, FIG. 14(b) is its equivalent circuit diagram, and FIG. 15(a) is the semiconductor device of Example 1. T-side view of another semiconductor device,
The same figure (b) is the equivalent circuit diagram, FIGS. 16 and 17.
The figure is a sectional view showing another semiconductor device manufacturing process P, 1 of Example 1, and FIGS. 18, 19, 20, and 21 are
Manufacture of semiconductor device of Example 2] - Cross-sectional view showing process, second
Figures 2 (, 1) and (b) show q of the semiconductor device of Example 2.
FIG. 23 is a sectional view of the 1-wrench hole of the present invention, FIG. 24 is an explanatory diagram of the reason for increasing the degree of integration of the present invention, and FIG. 26 is a cross-sectional view of a conventional semiconductor device having a trench capacitor, FIG. 26 is a cross-sectional view of a manufacturing process of a conventional planar semiconductor device, and FIG. 27 is a diagram showing the basic circuit of a MOS inverter. . 1. Silicon substrate, 2. Silicon oxide film for mask. 3...[-trench hole, 4 element isolation oxide film, 5... truncated pyramidal trench hole, 6... gate oxide film,
7... P- layer, 8... Polysilicon film, 9... Gate electrode, 10... Source region (n+ layer), 11... Train region (n+ layer), 12... Interlayer insulation membrane, 13...AQ membrane, 14...AQ electrode.

Claims (1)

[Claims] In a semiconductor device including at least one trench hole, the structure of the trench hole is square in cross section;
A semiconductor device characterized in that the hole has an inverted truncated pyramid shape in which the deeper the hole, the smaller the cross-sectional area becomes.