JPH0443454A - Multi-processor type electronic computer - Google Patents

Abstract

PURPOSE:To execute the task of a test program without giving an adverse influence to the regular execution of the task by designating operation controllers permitting the execution of the task concerned for respective tasks. CONSTITUTION:The operation controllers which can execute respective tasks are stored in an operation controller designation memory 10. When a task execution request is generated, the task concerned is executed only in the operation controller designated by the task concerned. For executing the tasks of plural test programs, only one operation controller 2a is designated in the operation controller designation memory 10. Thus, the tasks of the test programs are prevented from being simultaneously executed in two operation controllers even if the other operation controllers 2b - 2d are in an idle state. Thus, the task of the test program can be executed without giving adverse influence to the regular execution of the task while a function for efficiently executing respective tasks is held.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a multiprocessor type electronic computer in which a plurality of arithmetic and control units are connected in parallel via a bus line, and in particular, This paper relates to a multiprocessor type electronic computer with improved execution control method.

(Prior Art) Generally, electronic computers having a plurality of arithmetic and control units can be roughly divided into two types. One is a serial type electronic computer, which is composed of a main arithmetic and control unit (main processor) and a slave arithmetic and control unit (slave processor). For example, a main program is assigned to the main arithmetic and control unit, and a subprogram is assigned to the slave arithmetic and control unit.

Usually, a main program is started in the main processing and control unit, and subprograms are started during the execution process of the main program. The subprogram is executed by the slave arithmetic and control unit, and the calculation result and completion information are notified to the main arithmetic and control unit. That is, the operation of the slave arithmetic and control device is completely controlled by the main arithmetic and control device.

The other electronic computer is a so-called multiprocessor type electronic computer, and each arithmetic and control unit has the same function.

Each program can be executed in parallel by a plurality of arithmetic and control units. In a system in which each arithmetic and control unit accesses the same main memory, one main memory cannot be accessed at the same time, so an adjustment circuit is used to adjust access rights between the arithmetic and control units. Also,
When rewriting the contents of the main memory, the contents of the cache memory in each arithmetic and control unit are also rewritten at the same time, so that the same calculation result can be obtained no matter which arithmetic and control unit executes multiple programs. has been done.

Further, a unit in which a program is executed by each arithmetic control unit is called a task, and the execution of this task is performed by a task execution control program that is the core of an operation system (O8) program that is always included in a computer.

According to this task execution control program, a task to be executed at that time is determined based on pre-registered priorities among a plurality of tasks for which execution requests have been made, and a program for that task is executed. For example, when a request is made to execute a certain task at a certain time, the priority of the requested task is compared with the priority of the task currently being executed, and the priority of the requested task is determined to be higher. If the value is higher, the currently executing task is temporarily suspended and the currently requested task is executed. And this task execution control program is
Usually a request to execute a task, a request to delay.

It is automatically activated when an event such as completion of execution or completion of input/output occurs.

In a multiprocessor electronic computer in which a plurality of arithmetic and control units are provided in parallel, the task execution control program is provided in each arithmetic and control unit. Furthermore, a CPU queue is formed in the main memory section for storing tasks that have been requested to be executed but have not yet been executed. When each arithmetic and control unit receives a task execution request, each arithmetic and control unit controls the execution of the above-described task by itself.

That is, the CPU checks the CPU queue for information about the task that has been requested to be executed, and determines whether or not to immediately execute the task.

Note that checking, deletion, etc. of the CPU queue is executed by each arithmetic and control unit, or by using an exclusive mechanism so that each arithmetic and control unit does not perform the same at the same time.

In a multiprocessor electronic computer that performs such task execution control, each task may be executed in any arithmetic control device. That is, at the time a task execution request is issued, it is assigned to an arithmetic and control unit that is not executing a task. As a result, each arithmetic and control device executes different types of tasks in parallel, so each arithmetic and control device can be used efficiently, and the processing efficiency of the computer as a whole can be improved.

However, even in multiprocessor electronic computers in which the execution of each task is controlled using the method described above, there are still problems to be improved as described below.

For example, a multiprocessor type computer that executes online business has the processing ability to execute a plurality of business tasks whenever necessary or after a short waiting time has elapsed.

In such electronic computers, when it becomes necessary to develop a new program and run an experiment on the system in which the program is to be actually operated, the task of this test program can be performed on a floppy disk drive (FDD) ) etc. from the auxiliary storage section to the main storage section to generate an execution request, the task will be executed in a vacant arithmetic and control unit under the same conditions as the above-mentioned normal business task.

However, since this test program is just a test program, it may contain errors in the design of the progera, grammatical errors, etc.

Therefore, if this test program contains, for example, an infinite loop, the program processing will not end, and the arithmetic and control unit executing this test program will continue to be occupied by this task. Therefore, when multiple programs with such infinite loops are executed, a large number of arithmetic and control units are occupied.
Normal online operations will be disrupted.

Especially if these test programs are given a higher priority than other business programs, the damage can be severe.

(Problem to be Solved by the Invention) As described above, in conventional multiprocessor type electronic computers, each task is executed under exactly the same conditions for each arithmetic control unit, so when a test program is executed, the original There is a concern that online operations may be disrupted.

The present invention was made in view of these circumstances, and
By specifying the arithmetic control unit that is permitted to execute the task for each task, it is possible to limit the arithmetic control unit that executes a specific task such as a test program, and for normal business programs, the arithmetic control unit is not limited. This enables the test program to execute tasks without adversely affecting normal task execution while retaining the conventional functions that allow each task to be executed efficiently, thereby improving reliability and processing efficiency at the same time. The purpose is to provide a multiprocessor electronic computer that can perform

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention connects a storage unit and a plurality of arithmetic control devices to a bus line, and executes each program as a task which is its execution form. In a multiprocessor electronic computer, each task is stored in a storage unit and each arithmetic control reads and executes the task stored in the storage unit in response to a task execution request. A plurality of arithmetic and control unit designated memories are provided for storing arithmetic and control units, and each arithmetic and control unit is configured to include itself in the arithmetic and control unit of the corresponding task in the arithmetic and control unit designated memory in response to a task execution request. The system is equipped with a task execution control means that executes the corresponding task only when the task is executed.

(Function) In the multiprocessor type electronic computer configured in this manner, arithmetic control units capable of executing each task are stored in an arithmetic control unit designation memory. Therefore, when a task execution request occurs, the corresponding task is executed only by the arithmetic and control unit designated for the corresponding task.

Therefore, when executing tasks for multiple test programs, you can specify only one arithmetic and control unit in the arithmetic and control unit specification memory, even if the other arithmetic and control units are free. , the tasks of the test program are never executed by two arithmetic and control units at the same time.

Therefore, even if there is a large error in the test program, other operations will not be adversely affected.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing an outline of a microprocessor type electronic computer. Bus line 1. Four arithmetic and control units 2a, 2b, 2c, and 2d are connected to the controller. Also,
The main memory unit 4 is connected to the bus line 1 via the system control unit 3.
and a plurality of auxiliary storage units 5 are connected.

Each of the arithmetic and control units 2a to 2d has the same specifications and has a function of executing each task under the same conditions. Each of the arithmetic and control units 2a to 2d can access the main storage unit 4 in common.

Further, each of the arithmetic and control units 2a to 2d is provided with a task execution control program in its own O8 (operation system) to control the execution of each task. moreover,
A cache memory is provided for storing frequently accessed data in the main memory section 4.

The main storage unit 4 is composed of, for example, a RAM, and the main storage unit 4 includes a CPU queue 6 shown in FIG. 2 and a CPU queue 6 shown in FIG. Task control information 7 for each task shown in is stored.

Further, each auxiliary storage section is constituted by, for example, a floppy disk drive device (FDD), a magnetic disk recording device, etc., and programs for each task to be executed by this multiprocessor type electronic computer are recorded. This auxiliary storage unit 5 stores a newly developed test program in addition to normal business programs. Note that each program stored in this auxiliary storage section 5 is created by a program creation device (not shown separately) and written into this auxiliary storage section 5.

In the CPU queue 6, means for executing various processes such as transferring a program to which the task belongs from the auxiliary storage unit 5 to the main storage unit 4 is secured for each task for which an execution request has been made. Later, for each task for which an execution request has been issued, the task name and the priority registered in the task control information 7 are stored in the order of the priority. In the embodiment shown in FIG. 2, there are three tasks, A, B, and C, for which execution requests have been issued, and the registered priorities are in the order of A, B, and C. The task execution control program in O8 of each arithmetic and control unit 28 to 2d refers to this CPU queue 6 and reads out a task to be executed.

As shown in FIG. 3, the task control information 7 for each task includes the task name 8. Priority 9. Arithmetic control unit specified memory 1
0. Program information 11. Intermediate execution result storage area 12.
It consists of a queue creation area 13 and the like.

Priority 9 is a numerical value that indicates how much priority the own task is given among all tasks including other tasks.For example, priority [1] is a number that indicates how much priority the task is given to be executed among all tasks including other tasks. will be executed with top priority. In this case, if the priority of the task whose execution was requested later is higher than the priority of the task that is being executed, the task that is being executed is interrupted and the task that is requested to be executed later is executed first.

In the arithmetic and control device specification memory 10, the arithmetic and control devices 2a to 2d that are permitted to execute the corresponding task are set to [1] or [0].
is stored as bit information.

The bit data [10101 shown in FIG. 3 indicates that permission has been given to the first arithmetic and control unit 2a and the third arithmetic and control unit 2d to execute the corresponding task. Therefore, if the task of a normal business program can be executed by any of the arithmetic and control units 2a to 2d, [1111]
bit data is set. Further, when the arithmetic and control unit to be executed, such as a task of a test program, is limited to one specific arithmetic and control unit, such as the fourth arithmetic and control unit 2d, bit data of [0001] is set.

In addition, the execution result storage area 12 is used to store the execution result of a corresponding task being interrupted when a request for execution of a task with a higher priority than this task occurs during the execution of the corresponding task in any of the arithmetic and control units 28 to 2d. However, this area is used to save the mid-execution results of this task and, when the task becomes executable again, to use these mid-execution results to restart execution of the task from the interrupted position.

Further, the queue creation area 13 is an area for writing task names and priorities in the CPU queue 6 shown in FIG. 2 in order of priority.

The system control unit 3 also controls each arithmetic and control device 28 to 2d.
When the data stored in the main storage unit 3 is rewritten, a copy of this data is sent to each arithmetic and control unit 2.
It performs control such as writing into the cache memory of a to 2d. In addition, a plurality of arithmetic and control devices 2a to 2a are stored simultaneously in the main storage unit 3.
When access occurs from 2d, access rights are adjusted.

When a task execution request is generated, the task execution control program O8 in each arithmetic and control unit 2a to 2d starts the program for the corresponding task according to the flowchart of FIG. 4.

When a task execution request occurs, the task name and priority of the task are read from the first row of the CPU queue 6. Then, at P (program step) 1, it is checked whether there is a currently suspended task. Note that if a new task execution request occurs while a task is being executed, the execution of the currently executing task is interrupted. If there is a suspended task in Pl, the priority 9 of the task control information 7 of the task currently being executed in the main memory 4 and the priority 9 of the task control information 7 of the task for which the current execution request has been made are Make a comparison.

Then, in P2, if the priority level 9 of the current execution request is high, proceed to P3, read the 4-digit bit data in the arithmetic control unit specification memory 10 of the task control information 7 of the task of the current execution request, If the bit in the bit data indicating the own arithmetic control unit is set to [1], it is necessary to execute this task and the process advances to P4. At P4, the mid-execution result of the currently suspended task is stored in the mid-execution result storage area 12 of the task control information 7 of the task. Next, the task name and priority of the interrupted task are registered in the CPU queue 6. Specifically, if other tasks are registered in this CPU queue 6, their priority is compared with the current priority, and each task is arranged in the CPU queue 6 in order of priority. stores the task name and priority of this task.

Next, at P6, if there is an execution intermediate result in the execution intermediate result storage area 12 of the task control information 7 of the task for which the execution request has occurred this time, this execution intermediate result is stored in the own arithmetic control unit 2.
Restore to registers 8-2d. At Pl, program control is transferred to the program of this execution request task. Thus, the program of the task for which the execution request has been made starts to be executed. Note that if there is an intermediate execution result, program processing is restarted from the program position of the intermediate execution result.

In addition, at P3, if the bit indicating the own arithmetic control unit in the bit data of the arithmetic control unit specification memory 1o corresponding to the task of the execution request is cleared to [0], this task is executed by the own arithmetic control unit. Since it is necessary to execute it with another arithmetic and control unit other than the above, proceed to P8.

At P8, it is checked whether the task for which the execution request has been requested is registered in the CPU queue 6 in the main memory section 4. If it is registered, the first task, that is, the task with the highest priority is read out and the process returns to Pl.

In a multiprocessor type computer configured in this manner, when this computer executes an online business using each task of a normal completed business program, the task control information 7 of each task in the main memory 4 is If the bit data in the arithmetic and control device specification memory 10 is set to [1111], which indicates that it can be executed on all arithmetic and control units, each task will be executed on an available arithmetic and control unit according to its priority when an execution request is generated. It will be executed.

In addition, if you want to execute a task of a newly created test program during the process of executing such online work, the task control information 7 of this test task
In the bit data of the arithmetic and control unit specification memory 10, set only the bit of the arithmetic and control unit that you want to execute this test task to [1], and set each remaining bit to [0].
You can set it to . For example, the fourth arithmetic and control unit 4d
If you want to run it only with [00011
Set to . By setting the bit data in this way, when a test task execution request occurs, it will be executed in these arithmetic and control units 2a to 2C even if the other arithmetic and control units 28 to 2C are idle. Without a doubt,
This test task is executed when the execution conditions are met in consideration of priority and the like in the arithmetic and control unit 2d designated for the test task.

In this way, by limiting the arithmetic and control units that execute test tasks to a specific arithmetic and control unit, even if multiple test task execution requests are generated, multiple arithmetic and control units will not be able to execute the tasks at the same time. It will never be executed. Therefore, even if the test task program is a defective program that includes an infinite loop or the like, it will not interfere with the execution of other normal business programs that are executing online business. Therefore, a test program can be executed using a multiprocessor electronic computer that is currently executing online operations without interfering with other normal operations.

Furthermore, it is possible not only to specify an arithmetic and control unit that is permitted to execute a test task, but also to specify an arithmetic and control unit that executes a task of a specific business. Among each business task, there are functions that are completely unrelated to general business, such as functions that are executed at very short time intervals, and tasks that are specialized for external input/output. By fixing the arithmetic and control unit that executes these special tasks, there is no need to consider that the execution of these tasks will conflict with the execution of other general tasks, which is extremely convenient for computer system construction. It is effective for

[Effects of the Invention] As explained above, according to the multiprocessor electronic computer of the present invention, an arithmetic control unit that is permitted to execute the task is specified for each task, and a test program, for example, is specified. The arithmetic and control units that perform these tasks are limited. Therefore, by not limiting the arithmetic and control unit in a normal program, the tasks of the test program can be executed without adversely affecting normal task execution while retaining the conventional functions that allow efficient execution of each task. , it is possible to simultaneously improve reliability and processing efficiency.

[Brief explanation of the drawing]

The figures show a multiprocessor electronic computer according to an embodiment of the present invention, in which Fig. 1 is a block diagram showing the overall configuration, Fig. 2 is a diagram showing a CPU queue, and Fig. 3 is a diagram showing task control information. FIG. 4 is a flowchart showing the operation. 1... Bus line, 2a, 2b, 2c, 2d...
... Arithmetic control unit, 3... System control section, 4.
... Seed storage unit, 5... Auxiliary storage unit, 6... CPU queue, 7... Task control information, 10... Arithmetic control unit specification memory. Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 2

Claims (1)

[Scope of Claims] A storage unit and a plurality of arithmetic and control devices are connected to a bus line, each program is stored in the storage unit as a task which is an execution form of the program, and each of the arithmetic and control units is configured to: A multiprocessor type electronic computer that reads and executes tasks stored in the storage unit, comprising: a plurality of arithmetic and control device designation memories that store arithmetic and control devices that are permitted to execute the task for each of the tasks; a task execution control means provided in each of the arithmetic control units and configured to execute the task in response to the task execution request only when the arithmetic and control unit is included in the arithmetic and control unit of the task in the arithmetic and control unit designated memory; A multiprocessor electronic computer equipped with