JP2517859B2 - Parallel process management method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process management method in a system for distributing processes to spare processors in a memory sharing type parallel computer system. A spare processor is a processor for which there is no process to be executed in the pending process table for each processor.

[0002]

2. Description of the Related Art Conventionally, regarding a process distribution method in a memory sharing parallel computer system, Nakagawa et al., "Slit check mechanism for speeding up software interrupt processing between processors" (IPSJ Research Report 89-A).
RC-77, 1989 P17).

In the above-mentioned prior art, when distributing a process to another processor, each processor distributes the execution waiting process registered at the head of the execution waiting process table for that processor.

[0004]

Generally, as a human tendency to write programs, it is known that processes having high interdependence are written close to each other. Moreover, there is a tendency to write the writing process for shared data just before the reading process of the data. Therefore, in order to avoid useless waiting of data, it is general to register so as to execute in the order of description.

Now, suppose process a is 10 in the shared memory.
Write the first data at address 0 and process this data as process b
Is read, process b writes the second data at address 200, and process c reads this data.

At this time, by registering these processes in the execution-waiting process table of the same processor in this order, useless waiting can be avoided in the execution by a single processor.

In this case, if each processor has a cache of store-in type, the following problems occur.

[0008] Here, the store-in type cache, when write No write data in its cache writes the data into the cache belonging to its own processor but not transferred to the main memory that is shared, later, of the other When a processor requests to read the data, the data is transferred from the cache to the cache in the requesting processor.

In the above-mentioned conventional technique, each processor, when distributing a process to another processor, distributes the execution waiting process registered at the head of the process table for that processor. For example, as a result of the execution of the process a, when the process writes a certain data in the cache of the processor PE1 that is executing the process, and then a process distribution request is issued from another processor PE3, the next process b is distributed. . When this distribution occurs, the process b used by the data generated by the process a is executed by a processor different from the process a. Therefore, there is a problem in that it is necessary to transfer data from the cache belonging to the processor PE1 to the cache belonging to the processor PE3.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide a parallel process management method capable of reducing data transfer between caches.

[0011]

In order to achieve the above object, according to the present invention, an execution waiting process for registering an execution waiting process is performed.
Share the above process table for each processor
Provided in the memory, waiting for the first execution of the waiting processes
The first process waiting to be specified, which specifies the process.
From the process to the final pending process
The first pointer to
Specifies the pending process, the final execution
Specify from the waiting process to the first waiting process
A second pointer that is changed sequentially is set for each processor.
Out of each processor, in the pending process table
The processor with the registered pending process is the first
The first waiting process by referring to the pointer
Processors that issue and execute and request process distribution
Refer to second pointer if present and distributable
And take out the final pending process,
Waiting for its final execution for processors requesting distribution
Distributing the process of.

[0012]

Operation: Processes a, b, and
When c is registered, the execution by the self processor is performed in the same order as a and b as the execution by the single processor, and the process is distributed to other processors by first targeting c. As a result, since the process b is executed by the same processor as the process a, data transfer between caches does not occur with respect to the data generated by the process a and used by the process b.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1A is a configuration diagram of an embodiment of the present invention. A shared memory multiprocessor including three processors PE1 to PE3 is connected by a shared memory 1.

In the present embodiment, for the sake of simplicity, a memory shared multiprocessor consisting of three processors PE1 to PE3 will be described as an example. However, when the number of processors increases, a distributed process address storage corresponding to the processors described later will be given. It suffices to increase the areas 141 to 143. Each processor PE
1, PE2 or PE3 can be realized by a microcomputer having a plurality of registers.

In the shared memory 1, a shared process distribution request processor number area 13 and distributed process address areas 141 to 141 provided corresponding to one processor, respectively.
143, and execution waiting process tables 161 to 163 respectively provided corresponding to one processor.
Each execution-waiting process table is composed of a queue of process execution environment records (hereinafter, simply referred to as records) for representing processes waiting for execution. In this embodiment, each record 151 is, as shown in FIG.
It consists of four data. That is, the next record address indicating the address of the next record, the previous record address indicating the address of the previous record, and the program (not shown) stored in the shared memory 1 for executing the process of the corresponding process. It is composed of an instruction code address representing the address of the leading instruction and an argument list address representing the leading address of a list of arguments (not shown) stored in the shared memory 1 and used in the program.

Respective processors PE1, PE2, P
E3 includes caches 41 to 43 for storing address / data pairs, registers 21 to 23 for storing the first record address of the process table (also referred to as a first pointer).
Call the first record pointer) , and registers 31 to 31 for storing the last record address of the process table.
33 (also called the second pointer,
(Representing data) .

Each processor performs processing according to the process control flow 100 of FIG.

(1) In the process determination processing c1, each processor, for example PE1, determines whether the address held in the corresponding register 21 is 0 or not, and thereby determines whether or not there is an executable process. . In this embodiment,
If no records registered in the process table 161, i.e. when there is no execution-waiting process to PE1,
The address in the register 21 is set to 0. The same applies to the other registers 22 and 23.

Now, suppose that PE1 has three records 151.
Suppose we have a, 151b, 151c. At this time, the registers 21 and 31 have records 151a and 15a, respectively.
It holds an address of 1 c .

(2) As a result of the assumption, in the process determination processing c1, it is determined that there is a process waiting for execution in PE1. Retrieve the first record of . That is,
This record is removed from this table and stored in the work area (not shown) for PE1 in the shared memory 1. At this time, the address in the register 21 is changed to the address of the record 151b. Further, by changing the previous record address in the record 151b to 0, this record
It should be understood that the code 151b is the first record.

(3) Next, in the process execution process c3, the process corresponding to the retrieved record 151a is executed. That is, the processing of the corresponding process is executed using the instruction code address and the argument list address in this record.

(4) Next, the PE1 executes the process distribution control processing c4.

In this process, as shown in FIG.
In step b0, the process distribution request processor number 13 in the shared memory 1 is read and it is determined whether the value is "0". As will be described later, when there is a processor requesting distribution of a process in this number 13, that processor stores the number here. Therefore, by determining whether or not the value of the process distribution request processor number 13 is "0", it is possible to determine whether or not a process distribution request is issued from another processor.

Now, assuming that the value of this number 13 is "3", it is determined in step b0 that there is a processor requesting process distribution.

In this case, in step b1, it is determined whether there is at least one process that can be distributed. In this embodiment, when there are two or more processes registered in the corresponding process table 161, it is assumed that there are processes that can be distributed.

Now, according to the assumption, since PE1 has two records 151b and 151c, it is judged that the process can be distributed.

In the next step b2, the value of the process distribution request processor number 13 (this is "3" by the present assumption).
The process address 14 to PE3
3, the address in the register 31 which is the last record pointer of the pending process table 161 (in the present example, this value is the last record 1 of this table 161).
(Which is the address of 51c). This gives P
This means that the process 151c is distributed to E3. Further, with the distribution of the final record 151c, the address in the register 31 is changed to the address of the preceding record 151b. Further, by changing the next record address in the record 151b to 0, it is shown that this record is the final record.

Further, in step b3, the original process distribution request is cleared by writing the value "0" into the process distribution request processor number 13.

If either of the conditions determined in steps b0 and b1 is not satisfied, the process is not distributed.

As described above, the process distribution control process c
Finish 4

(4) As a result of the judgment in step c2, if there is no process waiting for execution in the processor, the process distribution request control process c5 and the process reception process c6 are executed.

The contents of these processes will be described taking the case where the PE 3 executes these processes as an example.

When the process determination processing c2 is executed first, the PE 3 executes the process distribution request control processing c4 when there is no process waiting for execution in the processor.
In the process distribution request processor number 13, the number of the processor, in the present example, the value "3" is written. Accordingly, the addresses in the corresponding registers 23 and 33 are set to zero.

(5) Next, in the process reception process c6, the PE 3 distributes the process address 143 to its own processor.
Is read and it is determined whether the address is 0 or not. If the address is not 0, the process waiting for execution is P
Since it has been distributed to E3, the read address is stored in the registers 23 and 33 corresponding to PE3. In this way, the record 151c distributed from PE1
Is registered in the pending process table 163 corresponding to PE3.

In the above processing, the reading and writing of the data 13, 141 to 143, which may cause a write conflict, are performed in order to avoid erroneous operation due to collision of execution times of a plurality of processors. IB
M System / 370 Extended Arch
issue PrinciplesofOpera
ation SA22-7085-0 page A14 ″, compare and swap (Com
It is assumed that the data "0" is written after the data is read by using the pare and Swap procedure.

The effects of this embodiment will be described with reference to FIGS.

In the prior art, each processor distributes the process at the head of the record in the process table at the time of process distribution. In the case of the process described in the above embodiment, PE1 distributes process 151b to PE3.

Now, tentatively, the process corresponding to the record 151a (which may be hereinafter referred to as process 151a) writes the first data at address 100 of the shared memory 1 and records this data in the record 151b. Process corresponding to (this may be referred to as process 151b below)
The process 151b writes the second data at the address 200, and the process corresponding to the record 151c (hereinafter sometimes referred to as process 151c) reads the data.

FIG. 4 describes the processing of PE1 and PE3 according to the prior art in such a case with time.

That is, although the write data to the address 100 by the execution of the process 151a is stored in the cache 41 in the processor PE1, since this cache is a store-in type, this data is immediately transferred to the shared memory 1. Not done. The reading of address 100 by the process 151b is performed in the cache 43 in the processor PE3. At this time, when the cache 43 determines that this data is data that does not exist in the cache 43 by a known method, it requests the main memory 1 to transfer this data to the cache 43. The main memory 1 first inquires of the other caches 41 and 42 by a known method whether or not the data at this address has been updated. Since the cache 41 responds to this by a known method, the caches 41 to 4 can be accessed via the main memory 1.
The data written by the process 151a to 3 is transferred. Similarly, for the data at address 200, data transfer also occurs between the cache 43 written by the process 151c and the cache 41 read by the process 151c, and the transfer time of two times in total is shown by the bold line in FIG. So it happens.

FIG. 5 describes the processing of PE1 and PE3 according to the present embodiment with respect to two data having the same relationship as the above, in chronological order.

In the present embodiment, since the process 151c is distributed to the PE3, the write data to the address 100 in the execution of the process 151a is performed in the cache 41, and further the data at the address 100 is read by the process 151b in the cache 41. Since this is done, no data transfer between caches associated with this data will occur. After all, the data transfer between the caches is only for the data at address 100 transferred between the processes 151b and 151c. Therefore, in this embodiment, the data transfer between the caches can be reduced as compared with the conventional technique.

In this embodiment, the number of data to be transferred between processes and the number of data that can be stored in the cache are each one, but generally, in a system having a cache that can store a large number of data, even greater performance is achieved. It is clear that it makes a difference.

Further, the process distribution request and the process distribution are detected by the value 13 of the fixed address data 13 and 141 to 143 on the shared memory 1 not being 0 as described above. With such a communication register, the detection processing can be further speeded up.

[0045]

According to the present invention, in a parallel computer system including a plurality of processors each having a cache, it is possible to reduce the number of times of data transfer between caches and realize high-speed processing.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram of a process control flow.

3 is a schematic flowchart of a process distribution control process (c5) in FIG.

FIG. 4 is a time chart showing a time course of process execution according to a conventional technique.

FIG. 5 is a time chart showing the elapsed time of process execution according to an embodiment of the present invention.

[Explanation of symbols]

1 ... Shared memory, 13 ... Process distribution request processor number, 141, 142, 143 ... Distribution process address,
151a, 151b, 151c ... Record of PE1 execution waiting process, 161, 162, 163 ... Execution waiting process table, 21, 22, 23 ... First record pointer register of execution waiting process table, 31, 3
2, 33 ... Final record pointer register of the pending process table.

Claims (1)

(57) [Claims] 1. An execution waiting process comprising a plurality of processors each having a cache and sharing a shared memory.
Each process has a pending process table for registering processes.
In the shared memory corresponding to the server, the first waiting process among the waiting processes
The first waiting process to be specified
The first to sequentially change the designation to the final pending process
Pointer and the last execution wait of the above waiting process
The last process to wait
The specification is changed sequentially from the process to the first pending process.
A second pointer to be further provided is provided for each processor, and the execution-waiting process table among the processors is provided.
The processor with the registered pending process is
Refer to the first pointer to find the first pending process.
There is a processor that takes and executes, and requests the distribution of the process, and the distribution
If possible, refer to the second pointer above and
Request the process distribution by extracting the pending process
The last pending process for the processor
A parallel process management method characterized by distributing the processes.