JPH0442609A - Automatic clear circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by connecting the output of a clock generating means to 1st and 2nd current transfer means, transferring the current of a 1st level to the 1st current transfer means by the detection of the signal of the clock generating means, and transferring the current of a 2nd level to the 2nd current transfer means by the detection of the same signal of the clock generating means. CONSTITUTION:The difference of a current transfer circuit 3 from the current transfer circuit of a conventional circuit resides in that an NMOS is eliminated from the conventional circuit but an NMOS 31 and a PMOS 32 are added instead. Moreover, the gate of the NMOS 31 is connected to the output terminal of a clock generating circuit 2, the source is connected to, a ground level poser supply Vss and the gate of the PMOS 32 is connected to the output terminal of the clock generating circuit 2 and the source is connected to the drain of the NMOS 31 and the drain is connected to the source of the NMOS 33. When the NMOS 31 and the PMOS 32 are in an energized state and also the NMOS 33 is energized, a through-current flows to a line A shown in figure. then a charge is stored in a capacitor 41 by the through-current. Thus, the automatic clear circuit acted similarly to the conventional circuit is realized regardless of the reduced circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an auto-clear circuit used for detecting a clock signal when power is turned on in an electric circuit.

[Conventional technology]

Figure 4 is a circuit diagram showing the configuration of a conventional auto clear circuit.
The gate of aυ (referred to as MOB) is connected to the ground potential Vss, the source is connected to the power supply potential Vdd, and the capacitor α
One pole of 2 is connected to ground potential Vss, and the other pole is connected to p
It is connected to the drain of MO8 (111). (7) is a pulse generation circuit, and this pulse generation circuit (TE) is connected in series with the inverter (5) and the inverter's delay circuit (□□□). A series connection circuit and an inverter are connected in parallel, and the output end of the delay circuit (2) and the output end of the inverter l?→ are connected to a NOR gate (2). (2) is a clock generation circuit. The output terminal of this clock generation circuit (2) is connected to the inverter (2) and the inverter (2).
) is connected to the input end of the tB> is a current transfer circuit, and this current transfer circuit tB') is connected to the power supply shaping circuit (1) and the pulse generation circuit (TE). This current transfer circuit IQ)
The gate of NMO8@) is connected to the output terminal of the NOR gate (G), the source is connected to the ground potential V8S, and NM
The gate of 33 in O8 is connected to the drain of PMOEt (connected to the common connection point between 111 and the other pole of the capacitor (17J, and the source is NMO8Q!l). (4) is a charge storage circuit, and a current transfer circuit tB"). This charge storage circuit (4) has one pole of the capacitor (b) connected to N.
It is connected to the drain of MOS (2), the other pole is connected to power supply potential VDD, one end of the resistor (to) is connected to the drain of NMO8, and the other end is connected to power supply potential VDD. (6) is a waveform shaping circuit, and charge storage circuit (4)K
Can be connected. This waveform shaping circuit (6) has an inverter and an inverter connected in series, and the input terminal of the inverter (9) is common to the drain of NMO8@, one pole of the capacitor (9), and one end of the resistor (A). Connected to a connection point.

(6) is a reset circuit, and the input terminal of this reset circuit is connected to the output terminal of the inverter. The primary operation will be explained using the potential waveform diagrams of FIGS. 4 and 5. When power supply a is turned on, PMO8σD of power supply shaping circuit (1)
and the time constant of capacitor α2, the potential (in Fig. 5)
The waveform becomes And the potential is N M OS (33)
The threshold voltage FE V? 1133 f exceeds N M
Current begins to flow through O8 (33). Further, when the clock signal from the clock generation circuit (2) is input to the pulse generation circuit (7), the potential f is applied to the fifth pulse generation circuit (73) by the delay circuit (73).
The potential g becomes the waveform shown in Fig. 5(g) by the inverter (74).Then, the potential f2g
When both are "L", the output potential of the NOR gate (75) becomes 1B", and NMO8 (81) becomes conductive. Hereinafter, by repeating pulse generation in the pulse transmission circuit (γ), N M O8 (8
The conductive state of 1) is repeated. When NMOS (81) and NMOS (33) are conductive at the same time, the capacitor (41) of the charge storage circuit (4) becomes rechargeable and the potential d decreases. Then, when the potential d falls below the threshold potential V'r HISl of the inverter (51), the output potential of the waveform shaping circuit (6) changes from "B" to L. This signal is sent to the reset circuit (6). transmitted to.

For example, power supply potential VDD: 5V, ground potential Vas =
OV tN M OS (33) (7) Threshold potential V? 1i33 = l V, Ia Herme (51)
Assuming that the threshold potential VTMI%l==2.5 V, when the potential d becomes 2.5 V or less, the output potential e of the waveform shaping circuit (6) changes from 5 V to 0.

[Problem to be solved by the invention]

Since the conventional auto clear circuit was configured as described above, the pulse generation circuit +S) is connected to the inverter (71) to
(74) and NOR game) (75) is required, which increases the circuit scale.

This invention was made to solve the above-mentioned problems, and aims to provide an auto-clear circuit that operates in the same manner as the conventional example even if the circuit scale is reduced.

[Means to solve the problem]

The auto clear circuit according to the present invention includes power supply shaping means for shaping a power supply voltage, clock generation means for generating a clock signal, and is connected to the power supply shaping means and the clock generation means, and detects a signal from the clock generation means. a first current transmission means for transmitting a first level current having a certain relationship with the signal level; and a first current transmission means connected to the clock generation means to detect a homogeneous signal of the clock generation means and generate a second current transmitting means for transmitting a second level of current having a different fixed relationship with the signal level; and a third current transmitting means connected to the power supply shaping means to detect the level of the signal of the power supply shaping means. a current transmitting means including a third current transmitting means for transmitting a current of a certain level; a charge accumulating means including a capacitor connected to the current transmitting means; The waveform shaping means detects whether the signal is larger or smaller than the level and converts it into a binary value, and the reset means is connected to the waveform shaping means and generates a reset signal.

[Effect]

The first current transmitting means of the current transmitting means in this invention transmits the level current of wcl by detecting the signal of the clock generating means, and the second current transmitting means transmits the level current of wcl by detecting the same signal of the clock generating means. transmits a level of current.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. Note that the explanation of parts that overlap with the explanation of the conventional one will be omitted as appropriate. FIG. 1 is a circuit diagram of an auto clear circuit which is an embodiment of the present invention.

In the figure, the symbols (1), (2) j(4), 1
5! , (a) is equivalent to the conventional one. (8
) is a current transfer circuit, and the difference between this current transfer circuit (8) and the conventional current transfer circuit (8) is that N M
OS (81) is removed and N M OS (31
) and P M OB (32).

In addition, the gate of NMO8 (31) is the clock generation circuit (
The PMOS (32) has a gate connected to the output terminal of the clock generation circuit (2), and a source connected to the output terminal of the clock generation circuit (2), and a source connected to the ground potential VSS.
1), and the drain is connected to the drain of NMO8 (33
) source.

Next, the operation will be explained using the circuit diagram of FIG. 1, the potential waveform diagram of FIG. 2, and the current characteristic diagram of FIG. 3.

The process from when the power is turned on until the conduction current begins to flow through the NMOS (33) is the same as that of the conventional system.

When a clock signal is generated from the clock generation circuit (2), a signal 101 in FIG. 2 is outputted to the potential O at the output end of the clock generation circuit (2). NMO8 (31) and PMOS
(32) has an inverter configuration, and when the potential O is 1'' or @L'', NMOB (31) and P
When one of M08 (32) is in a non-conducting state, no current flows in FIG. 1A, as shown in FIG. 3.

However, at the instant when the signal of the clock generation circuit (2) changes from 1'' to ``S'' and from m@L'' to @E'', the potential O assumes an intermediate potential as shown in FIG. 2 (01).

For example, the signal of the clock generation circuit (2) changes from "L" to 1.
When changing to "B", the intermediate potential of 01 in Figure 2 (0) is transiently taken. Among these intermediate potentials, when the threshold potential of NMO8 (31) is higher than ■Ml1, PMOS (32) When the threshold potential V'rgp or less, that is, the potential 0 is set as Vc, VTMN (Vc (Vyhp
・・・・・・・・・・・・・・・・When (1) holds true, N M OS (31) and P M O8 (
32) becomes conductive transiently, and N M O8 (31
) and PMOS (32) are in a conductive state and N M O8
When (33) is in a conductive state, a normal current At as shown in FIG. 3 flows in FIG. 1A. And this common current person 1
As a result, charge is stored in the capacitor (41). below,
When the potential O satisfies the relationship of equation (1) above, the common current A1
flows, and charge accumulation in the capacitor (41) is repeated. When charge is accumulated in the capacitor (41), the potential d
decreases. Then, this potential d is applied to the inverter (51)
When the threshold voltage VTRI% becomes less than 1, the potential e at the output terminal of the inverter (52) changes from 1 "to:L".

This signal is transmitted to the reset circuit (6).

For example, power supply potential Voo = 5V s ground potential Vss =
OV y NM O8 (31) threshold potential, V
'ram = lV, threshold potential of PMOS (32) VTgp = 4V, (:/bar p (5
1) (7) L I value potential VT) IF+1 ==
Assuming that the voltage is 2.5 V, the potential C is 1 V (Vc (4
When the condition of V is satisfied, the normal current flow A1 flows. When the potential d becomes 2.5v or less due to this common current AiK, the output potential e of the waveform shaping circuit (5) changes from 5v to O.
V K1ff1 waru.

In the above embodiment, the case is shown in which a signal changing from 1H''' to 1H''' is transmitted to the reset circuit. Reverse and convert N M O8 (31) to PM
Even if a signal changing from "L" to "1" is transmitted to the reset circuit by setting the PMOS (32) to NMO8 in the OS, the same effect as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, since the output of the clock generation means is connected to the first and second current transmission means, there is an effect that the circuit scale can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an auto clear circuit which is an embodiment of the present invention, Fig. 2 is a potential waveform diagram for explaining the operation of the auto clear circuit of Fig. 1, and Fig. 3 is a circuit diagram of an auto clear circuit of Fig. 1. A current characteristic diagram to explain the operation of the clear circuit, Fig. 4 is a circuit diagram of a conventional auto clear circuit, and Fig. 5 is a potential waveform diagram to explain the operation of the conventional auto clear circuit shown in Fig. 4. It is. In the figure, (1) is a power supply shaping circuit, (2) is a clock generation circuit, (8) is a current transfer circuit, (4) is a charge storage circuit, (6) is a waveform shaping circuit, and (6) is a reset circuit. show. In addition, the same symbols in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] a power supply shaping means for shaping a power supply voltage; a clock generation means for generating a clock signal; and a power supply shaping means connected to the power supply shaping means and the clock generation means to detect a signal of the clock generation means and to adjust the level of the signal to a certain level. a first current transmission means for transmitting a current of a first level having a relationship of a second current transmission means for transmitting a second level of current having a relationship of a current transmission means including the current means of No. 3; a charge storage means including a capacitor connected to the current transmission means; What is claimed is: 1. An auto clear circuit comprising: a waveform shaping means that detects and binarizes a signal, and a reset means that is connected to the waveform shaping means and generates a reset signal.