JPH0441629Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an improvement of a programmable delay circuit having uniform characteristics over a wide frequency range.

[Conventional technology]

FIG. 5 shows the configuration of a conventional programmable delay circuit. Conventionally, an input signal _S1 is applied to a variable delay line A having a large number of taps, and a selection circuit B switches the position of the taps of the variable delay line A to obtain an output signal _S0 . The variable delay line A generally has a structure in which inductances are provided between each tap, and the amount of delay increases as the number of inductances passing through increases. That is, the amount of delay in the signal taken out from tap tp ₂ is greater than that of the signal taken out from tap tp ₁ . The signal at which tap is selected can be controlled by a control signal.

[Problem that the invention attempts to solve]

However, the above-mentioned means have the following problems. Generally, when input signal S ₁ is repeatedly applied to variable delay line A, if the amount of delay is larger than the repetition period of input signal S ₁ , the amount of delay will fluctuate due to changes in the period of input signal S ₁ . . In other words, since the delay amount of a variable delay line generally has a frequency characteristic (the delay amount changes as the period of the input signal S ₁ changes), a programmable delay circuit like the one shown in Figure 5 can produce a large delay. There is a problem that it is not possible to measure the amount accurately.

An object of the present invention is to provide a programmable delay circuit that is not affected by the amount of delay even when input signals _S1 of different periods are applied, that is, has excellent frequency characteristics.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention includes variable delay means 1a and 1b which introduce an input signal with a pulse width _ΔT and delay it by an integral multiple n of the resolution τ, and the introduced input signal circulates with a period _t0 . A first _oscillation means that oscillates so that
a second oscillation means that oscillates in a circular manner; and a gate means that introduces output signal pulses of the first oscillation means and the second oscillation means and outputs a pulse signal when the phases of these two signals match. 8, and means 6 and 7 for introducing the output signal pulses of the first oscillation means and the second oscillation means and stopping the oscillation of the two oscillation means when the phases of these two signals match. It is prepared.

[Effect]

The present invention is equipped with two oscillators whose oscillation periods differ by τ, and input pulses are given to these two oscillators with a time difference nτ, and when the phases of the output pulses of the two oscillators match, the delayed output signal pulse is output. I'm trying to take it out.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a diagram showing an embodiment of a programmable delay circuit according to the present invention. In the figure, 1a is a variable delay line, 1b is a selection circuit, and has the configuration as explained in FIG. 5, for example. That is, the input signal S1 applied to the variable delay line _1a by the control signal S _B is taken out from the selection circuit 1b as a delayed signal S _D. Here, it is assumed that the resolution of the delay amount of the variable delay line 1a is τ, and the control signal
Suppose that the delay amount of nτ can be set arbitrarily by S _B. Note that n=1, 2, . . . , m. However, the amount of delay of the variable delay line 1a used in the present invention is much smaller than the amount of delay obtained with the variable delay line A shown in FIG.

The input signal _S1 with a pulse width _ΔT applied to the input terminal _P1 is applied to one input terminal of the OR gate 4, and is also applied to one input terminal of the OR gate 5 via the variable delay line 1a and the selection circuit 1b. added to the input terminal.

The output of the gate 4 is fed back via the fixed delay line 2 and the AND gate 6 to the other input terminal of the gate 4 itself. Here, the delay amount of the fixed delay line 2 is selected to be t ₀ . A loop circuit consisting of this gate 4, fixed delay line 2, and gate 6 constitutes a first oscillator. This oscillator is connected to the input signal introduced into gate 4.
S ₁ oscillates around this loop with period t ₀ .

The output of the gate 5 is fed back via the fixed delay line 3 and the AND gate 7 to the other input terminal of the gate 5 itself. Here, the delay amount of fixed delay line 3 is (t ₀
−τ). A loop circuit consisting of this gate 5, fixed delay line 3, and gate 7 constitutes a second oscillator. This oscillator oscillates so that the signal S _D introduced into the gate 5 circulates through this loop with a period (t ₀ −τ).

The output of gate 4 which has passed through fixed delay line 2 is applied to the other input terminal of gate 7 and also to one input terminal of AND gate 8.

The output of gate 5 which has passed through fixed delay line 3 is applied to the other input terminal of gate 6 and also to the other input terminal of AND gate 8.

As the output of the gate 8, an output signal S ₀ having a delay amount nt ₀ is obtained.

FIG. 2 is a time chart of signals from various parts in FIG. 1, and the operation of the apparatus shown in FIG. 1 will be explained with reference to this diagram.

The present invention includes a first oscillator consisting of a gate 4, a fixed delay line 2, and a gate 6, and a second oscillator consisting of a gate 5, a fixed delay line 3, and a gate 7. When an input signal S ₁ with a pulse width _ΔT as shown in FIG. 1 is applied to the gate 4 constituting the first oscillator (the output S ₆ of the gate 6 is set to low),
This input signal S ₁ instantaneously passes through gate 4 and is applied to fixed delay line 2 . The signal is then output from the fixed delay line 2 with a delay of time t ₀ (see FIG. 2, 3) and applied to one input terminal of the gate 6. here,
If a “low” level signal is applied from the fixed delay line 3 to the other input terminal of gate 6 (the circles attached to the inputs of gates 6 and 7 indicate the “high” level of the signal)
Fixed delay line 2 (which has the effect of inverting “low” and “low”)
The output of passes instantaneously through the gate 6 and is applied to the gate 4 again at a time t ₀ after the input signal S ₁ has been applied (see FIG. 2). Since the same operation is repeated thereafter, the input signal S ₁ oscillates so as to circulate with a period t ₀ .

On the other hand, the second oscillator consisting of gate 5, fixed delay line 3, and gate 7 also operates in a similar manner, and oscillates so that the signal S _D introduced from selection circuit 1b circulates at a period (t ₀ −τ).

Thus the first and second oscillators generate signals S ₁ and S _D
When input, it oscillates with period t ₀ and (t ₀ - τ). Since there is a difference of τ between the delay times of fixed delay lines 2 and 3, fixed delay lines 2 and 3 are
The phases of the output pulses S ₂ and S ₃ are in a relationship where they change by τ. The pulse S ₅ applied to the fixed delay line 3 is changed in advance by the variable delay line 1a and the selection circuit 1b to the pulse S ₄ applied to the fixed delay line 2 by nτ.
Fixed delay lines 2 and 3
The phases of the outputs S ₂ and S ₃ coincide at the n-th oscillation.

When the phases of the pulses output from the fixed delay lines 2 and 3 match, the oscillation stops. This is because the output of fixed delay line 2 is applied to one input terminal of gate 7 and the output of fixed delay line 3 is applied to one input terminal of gate 6. That is, when the outputs of fixed delay lines 2 and 3 become "high" at the same time, gates 6 and 7 are closed at the same time, so that the pulses necessary to continue oscillation are no longer applied to gates 4 and 5. This is because

Pulses output from fixed delay lines 2 and 3 above
A match between S ₂ and S ₃ is detected by an AND gate 8 to obtain an output pulse S ₀ . That is, from the gate 8, an output pulse S ₀ having a delay time n·t ₀ with respect to the input signal S ₁ is obtained.

FIG. 2 depicts an example where n=4 and t ₀ =Mτ=10·τ.

Note that the present invention is configured to obtain the following relationship: Δ _T <τ (1) (m+1) τ≦t ₀ (2) (m is the maximum value of n).

Let me explain the reason.

If Δ _T >τ, unnecessary pulses will be output even when the delay time setting value n is set to (n-1) or (n+1), resulting in malfunction.

Also, when setting n such that (n+1)τ< _{t 0} , the delay time of (n-m-
1) This is because a pulse is generated at the delay time of _t0 .

Although the principle operation of the invention has been explained above under the assumption of an ideal state, in an actual circuit, the output S _b of the selection circuit 1b is changed to the input signal S ₁ as shown in FIG.
It is difficult to delay the delay by exactly nτ as shown in FIG. That is, in an actual circuit, the time difference between the first pulses applied to fixed delay lines 2 and 3 is (nτ+δ ₁ ), and the phase difference shifted each time the two oscillators complete one round is (τ+δ ₂ ). Furthermore, if there is a slight error in the pulse widths of the two pulses S ₂ and S ₃ output from the fixed delay lines 2 and 3, the two oscillators will not stop oscillating.

Therefore, in order to compensate for δ ₁ and δ ₂ , as shown in FIG. A delay line 12 is provided for this purpose. Furthermore, when the phases of pulses S ₂ and S ₃ match, even if there is a slight error in the pulse width of the two pulses S ₂ and S ₃ output from the fixed delay lines 2 and 3, oscillation is ensured. In order to stop the comparator 9, as shown in Figure 3,
10 is provided at one input terminal of the gates 6 and 7. By providing the comparators 9 and 10, the signals S ₉ and S ₁₀ that control the opening and closing of the gates 6 and 7
The pulse width is widened. That is, as shown in FIG. 4, the inputs S ₂ and S ₃ (fourth
Figure 1), the comparator level is shown in Figure 4 (Figure 1).
If it is taken as shown in FIG. 4, the outputs of the comparators 9 and 10 will be as shown in FIG. 4, and the equivalent pulse width will be expanded as shown by the dotted line in FIG. In this way, since the pulse width of the signals S ₉ and S ₁₀ that control the opening and closing of the gates 6 and 7 is made wider than the pulse width of the signals S ₂ and S ₃ that pass through the gates 6 and 7, the pulse width of the signals S ₂ and S In a state where it can be considered that ₃ match, oscillation can be reliably stopped.

[Effects of this invention]

As described above, according to the present invention, the following effects can be obtained.

Generally, the frequency characteristics of a delay line (including a variable delay line) with a small amount of delay are better than the frequency characteristics of a delay line (including a variable delay line) with a large amount of delay. Furthermore, it can be said that a delay line with a fixed amount of delay has better frequency characteristics than a variable delay line.

In the conventional device, in order to obtain a delay of n·t ₀ , a delay line of n·t ₀ is actually required.

On the other hand, according to the present invention, a small delay time (t ₀ )
Since the delay line is obtained by multiplying the fixed delay line by n (which has good frequency characteristics), the frequency characteristics are extremely excellent compared to conventional means. That is, a programmable delay circuit with a large delay time can be realized with the same frequency characteristics as a fixed delay line with a small delay time.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a configuration example of a programmable delay circuit according to the present invention, Fig. 2 is a time chart of signals of each part in Fig. 1, and Fig. 3 is another configuration example of a programmable delay circuit according to the present invention. FIG. 4 is a diagram for explaining the operation of the comparator, and FIG. 5 is a diagram showing an example of the configuration of a conventional programmable delay circuit. 1a...variable delay line, 1b...selection circuit, 2,
3... Fixed delay line, 4, 5... OR gate,
6, 7, 8... logical AND gate.

Claims (1)

[Claims for Utility Model Registration] Variable delay means 1a and 1b that introduce an input signal with a pulse width _ΔT and delay it by an integral multiple n of the resolution τ, and oscillate the introduced input signal so that it circulates with a period _t0 . A signal delayed by the variable delay means 1a and 1b is introduced, and the delayed signal has a period (t ₀ −τ).
a second oscillation means that oscillates in a circular manner; and a gate means that introduces output signal pulses of the first oscillation means and the second oscillation means and outputs a pulse signal when the phases of these two signals match. 8, and means 6 and 7 for introducing the output signal pulses of the first oscillation means and the second oscillation means and stopping the oscillation of the two oscillation means when the phases of these two signals match. A programmable delay circuit characterized by: