JPH0441513B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a static induction transistor (SIT), particularly a vertical type static induction transistor (SIT) in which a source and a drain are respectively disposed on two opposite main surfaces of a substrate.
This relates to a method for manufacturing SIT.

It is a type of junction field effect transistor (FET) in the broad sense of SIT, but it is a type of junction field effect transistor (FET) in the broad sense of the word.
Different from FET. Therefore, even in a normal state where no bias is applied, a depletion layer is formed and the channel is pinched off, resulting in a normally off state. Additionally, the source-drain current (I _DS ) exhibits non-saturation characteristics with respect to the source-drain voltage (V _DS ).

A depletion layer is formed in the channel region due to the diffusion potential difference between the gate region and the channel region, causing the channel to pinch off, and this pinch-off point is the so-called "true gate." Looking at the potential distribution near the true gate, a so-called "potential well" is formed with the true gate as the bottom, and the shape and level of this potential distribution greatly depend on the diffusion potential difference.
Therefore, in order to pinch off the channel sufficiently, that is, to improve the controllability of the channel by the gate, it is necessary that the depletion layer is formed deep in the thickness direction in the channel region. It is advantageous for the gate region to be relatively deep in the region compared to the source region.

When realizing SIT as an integrated circuit, it is desirable to have less variation between each element. For example, it is desirable to minimize variations in mechanical dimensions in the arrangement direction of each element on one chip, and to form channels of uniform width.

The gate region is formed, for example, by heavily doping the n _- (v) region with an acceptor such as boron (B). With current ion implantation technology, even if boron is implanted with an acceleration energy of about 400 kV, it is only possible to implant boron to a depth of about 1 μm at most. Even if thermal diffusion treatment is performed after ion implantation, thermal diffusion is isotropic, so the implanted boron diffuses not only in the vertical direction, ie, the depth direction, but also in the lateral direction, ie, in the element arrangement direction. Therefore, the dimensions of the gate region must be designed to allow ion implantation to take into account the spread caused by this thermal diffusion, but since thermal diffusion is poorly controllable, it is necessary to design the dimensions of the gate region with high dimensional accuracy for a large number of devices. Manufacturing SIT is very difficult.

The present invention solves these drawbacks of the prior art,
A specific impurity region can be formed deep in the depth direction.
Therefore, it is an object of the present invention to provide a method for manufacturing a vertical SIT with high dimensional accuracy in the lateral direction.

According to the present invention, a method for manufacturing an SIT in which a gate region is formed in a semiconductor layer including a channel region includes an implantation step of implanting an impurity element to form the gate region from the surface of the semiconductor layer, and an implantation step of implanting the impurity element into the gate region. An implantation process in which a light element is implanted from the surface of the semiconductor layer so that its concentration shows multiple distributions in the depth direction of the semiconductor layer, and annealing of these implantation processes and the semiconductor layer subjected to the implantation process at a relatively low temperature. annealing steps to form a gate region in the semiconductor layer.

Next, with reference to the attached drawings, a vertical SIT according to the present invention will be explained.
The manufacturing method will be explained in detail.

Figure 1 shows one unit of vertical SIT. this
In SIT, the gate area is a control gate (CG)
This is a so-called non-divided gate type SIT that is not separated into a shielding gate (SG) and a shielding gate (SG).

Basically, non-split gate type SIT uses n ₊ Si substrate 1
epitaxially grown on one main surface of 0.
An n ⁺ region 14 and a p ⁺ region 20 are formed near the surface of the n ^- (v) type or intrinsic (i) layer 12, with the former serving as a drain region and the latter serving as a gate region. An electrode layer 52 is formed on the other main surface of substrate 10, and serves as a source electrode.

A SiO ₂ film 24 is formed on the surface of the epitaxial layer 12.
A drain electrode 36 is formed through the opening above the drain region 14, and a gate electrode 7 is formed above the gate region 20 through the opening.

With such a structure, the channel formed in the channel region 12 between the source 14 and the drain 10 is pinched off by the depletion layer formed by the diffusion potential of the gate 20, and the source-drain current I _DS functions as a normally-off switching element that exhibits non-saturation characteristics with respect to the source-drain voltage V _DS . In this example, the n ⁺ region 14 is the drain and the n ⁺ substrate 10 is the source, but the n ⁺ region 14 may be the source and the n ⁺ substrate 10 may be the drain.

Figure 2 shows a so-called split gate type SIT in which the control gate and shielding gate are separated. In this case, two gate regions 16 and 18 are provided in place of the gate region 20 in FIG. 1, the former being a control gate for storing and reading carriers, and the latter providing isolation from other SIT units and a reference potential. It is a shielding gate for. In each of the following figures, the same components as in FIG. 1 are indicated by the same reference numerals. Note that even in the split gate type SIT, the source and drain can be replaced with each other.

FIG. 3 shows another example of the split-gate type SIT shown in FIG. As a result, a large number of carriers can be accumulated. Further, the shielding gate region 18 is formed deeper than the control gate region 16, and the element isolation effect is improved.

Figures 1 to 3 show examples of so-called surface-gate SITs in which the gate is located near the surface of the device, but in Figure 4, the gate is located relatively deep in the n ^-epitaxial layer. This shows a so-called buried gate type SIT that is buried in the area.

The groove body 92 shown in FIG. 4 has two n ^- epitaxial layers 12a and 12b, which contain acceptors of the same element and at the same impurity concentration. both
A p ⁺ region 21 is formed in a mesh shape near the boundary between the n ^- layers 12a and 12b, spanning both layers, and serves as a buried gate. The buried gate 21 can be electrically connected to an external circuit via a gate electrode 60.

n ⁺ near the surface of the n ^- epitaxial layer 12b
A region 14 is formed, which becomes the source. This source 14 is connected to a source electrode 36 through an opening in the SiO ₂ layer 24. In addition, in the case of this buried gate type SIT, the source 14 and drain 1
0 are electrically interchangeable with each other.

Next, a specific example in which the SIT manufacturing method according to the present invention is applied to a surface gate type SIT will be described with reference to FIGS. 5A to 5M. These figures are cross-sectional views showing one unit of SIT, and the dimensional relationship of each part is exaggerated to make the process easier to understand, and is not proportional to the actual device.

First, an n ^- layer 12 is epitaxially grown on one main surface of an n ⁺ Si substrate 10 heavily doped with Sb, for example, about 10 ¹⁸ cm ^-3 , and a SiO ₂ layer 24 is formed thereon. do. The n ^- layer 12 is doped with As, for example, to have a carrier concentration of 10 ¹² to 10 ¹⁵ cm ^-3
The layer is approximately 5 to 10 μm thick.

The _SiO2 layer 24 on top of the n ^- layer 12 forms the gate region 1
Portions 26 corresponding to 9 and 18 or 20 are partially removed by wet etching to make them thinner. between gate regions 16 and 18, or 20
The spacing distance between each other is 3-10 μm.

Next, an impurity as an acceptor, for example, a group element such as B, Al or Ga, is added to the portions corresponding to the gate regions 16 and 18 or 20 in a thin layer.
The n ^- layer 12 is doped through a portion 26 of the SiO ₂ layer (FIG. 5A). This is shown as p ⁺ region 28 in FIG. 5A. Advantageously, the method of doping is ion implantation or thermal diffusion. For example B ⁺ or
For implantation of B ⁺⁺ ions, the acceleration energy is 10~
It is 400kV. Also, the dose is 10 ¹² to 10 ¹⁵ cm ^-2
It is. After ion implantation, activation annealing is performed at a low temperature, for example, about 700° C., in order to stabilize the implanted impurity atoms at crystal lattice positions.

Next, an implanted impurity such as B or a lighter element is ion-implanted into the portions corresponding to the gate regions 16 and 18 or 20 (No. 5B).
figure). H or He is used as these light elements. For the implantation of H ⁺ ions, the acceleration energy is
10 to 200 kV, and the dose is 10 ¹⁴ to 10 ¹⁷ cm ^-2 .
At that time, it is preferable to carry out the process at a temperature from room temperature to about 700°C.

The light element is implanted multiple times by changing the implantation depth (x _j ) of the light element ions so that the concentration profile after implantation becomes a desired gate region depth. The shallowest of the multiple implants is the one at the peak of the concentration profile.
The position in the x _j direction substantially coincides with the position of the peak of the concentration profile of the dopant doped in the impurity doping step. Further, regarding multiple implantations, it is advantageous for the concentration of implanted ions to be approximately the same each time. The depth of implantation is controlled by varying the acceleration energy and/or type of implanted ions.

For example, H ⁺ ions are implanted at three implantation depths, as shown in the concentration profile shown in FIG. 6A. Dotted lines 100a, 100b and 100
Indicated by c. There are no restrictions on the order of typing. Further, it is advantageous for the concentration peaks to substantially match. In this example, a profile 100a indicated by a dotted line 100a in the three stages of implantation has a concentration peak approximately coincident with the profile 102 of impurity ions (for example, B) implanted in the previous step in the x _j direction.

In FIG. 5B, the light element ions implanted by the light element ion stream 30 are schematically indicated by X marks 32, but actually have the profile shown in FIG. 6A.

The entire light element implanted structure is then annealed at a low temperature, and the dopant is thermally diffused deeply in the x _{and j} directions and dispersed as shown in the profile 104 shown in FIG. 6B. This state is schematically shown in FIG. 5C.
If these p ⁺ regions are used, for example, in a split-gate SIT
In FIG. 2, they are a control gate 16 and a shielding gate 18. Non-split gate type
The same applies to the case of SIT (FIG. 1), and the p ⁺ region thus formed becomes the gate 20.

The annealing temperature is a relatively low temperature of 500 to 1200°C, preferably 700 to 900°C. 1000℃
At higher temperatures, rearrangement of lattice defects occurs, so a lower temperature of 900° C. or lower is required. Annealing time is 30 minutes to 1 hour. As aforementioned,
When the separation distance between the gate regions is 3-10 μm, the depth of the p ⁺ region thus formed is 0.5-10 μm.
5.0μm, preferably 1-3μm, optimally about
It is 2.5 μm.

When light element ions are implanted, the n ^-layer 1 of the matrix
Many defects or vacancies are formed in the crystal lattice of 2, but when annealing at a relatively low temperature as mentioned above, these lattice defects are transported by diffusion, and at that time, the lattice defects doped in the previous step are transferred. It moves along with impurity elements such as B. Also, H or He
At this temperature, the implanted light elements, such as, will dissipate into the atmosphere from the structure surface. Therefore, the impurity element diffuses anisotropically in the direction in which the lattice defects are distributed, and a deep p ⁺ region is formed only in the depth direction (x _j ). For example, in a 111-plane epitaxial layer, many impurity elements diffuse in the <111> direction,
There is almost no diffusion in the <110> direction.

In other words, such anisotropic diffusion according to the present invention can be achieved by implanting an element lighter than the impurity element to be doped in multiple stages by ion implantation to a depth close to the desired impurity doping depth, and then annealing. This method thermally diffuses the impurity element doped in a shallow position only in the depth direction.
As a result, impurity elements that cannot be deeply implanted using normal ion implantation or thermal diffusion techniques can be anisotropically distributed in the depth direction to a desired depth.

Although an example has been described in which the light element is implanted after the impurity element is implanted, this order may be reversed, and the light element may be implanted before the impurity element is implanted, and annealing may be performed. Furthermore, impurity ions may be implanted between or in parallel with multiple light element ion implantations. Furthermore, SiO ₂ is used as a mask for light element implantation;
Other silicon compounds such as Si ₃ N ₄ may be used instead, or negative or positive photoresists such as polyimide may be used.

Example For example, as shown in FIG. 7, the separation distance W ₁ + W ₂ + W ₃ between the control gate 16 and the shielding gate 18 is 4 μm, and W ₁ and W ₃ are
For a single pixel cell with 1μm and _W2 of 2μm, B ⁺⁺ was ion-implanted at a dose of 5×10 ¹³ cm ^-2 at an acceleration voltage of 200kV, and the acceleration voltage was 40kV, 100kV and
H ⁺ ions were implanted in three steps at 200 kV, each at a dose of 1×10 ¹⁵ cm ⁻² , followed by annealing at about 700° C. for about 1 hour. This creates p ⁺ regions 16 and 18 with an acceptor concentration of B of 10 ¹⁷ cm _-3 to a depth of approximately
It was formed in the depth direction to a depth of 2.5 μm.

By the way, the structure 9 that was annealed at low temperature like this
2 is then transferred to a step of forming a source (or drain) region 14 (FIG. 5D). Here, SiO ₂ corresponding to the source region 14 is removed by wet etching and, for example, As is diffused to form an n ⁺ region 14 in the n ^- layer 12. Note that, in order to avoid complication of the drawings, FIGS. 5D and subsequent figures are illustrated with different dimensions in the vertical direction, that is, the depth direction, from those in FIGS. 5A to 5C.

Next, a doped polycrystalline silicon (DOPOS) layer 34 is formed on the entire surface by CVD (chemical vapor deposition) (FIG. 5E), leaving DOPOS in the portion corresponding to the source region 14, and the rest is covered with plasma. It is selectively removed by etching to form a source electrode 36 (FIG. 5F).

Next, a PSG (phosphosilicate glass) layer 38 is formed on the surface of this structure 92 by the CVD method (Fig. 5G), and a portion corresponding to the control gate region 16 is selected by wet etching together with the SiO ₂ layer 24 below. Then, an interlayer insulating layer 38 is formed (FIG. 5H).

Therefore, the DOPOS layer 41 is deposited on the surface of the structure 92 by the CVD method (FIG. 5I). Next, the portion of the DOPOS corresponding to the control gate region 16 is left and the rest is selectively removed by plasma etching to form the control gate electrode 7 (fifth
Figure J).

Corresponding to shielding gate area 18
The PSG and SiO ₂ portions 48 are selectively removed by plasma etching (Figure 5K).

Next, an Al layer 50 is deposited thereon by electron beam sputtering and resistance heating (5th L).
5), the remaining portions except for the portion corresponding to the shielding gate region 18 are selectively removed by etching to form a shielding gate electrode 54 (FIG. 5M). Further, the other main surface of the substrate 10 is made of aluminum.
A film 52 is deposited to form a drain (D) electrode. In this way, a split gate type SIT (for example, FIG. 2) is completed. Non-split gate type SIT (first
In the case of FIG. 1, the manufacturing process is similar except that a single gate region 20 is formed in place of the control gate region 16 and the shielding gate region 18.

Note that a large number of SITs shown in FIG. 5M may be arranged two-dimensionally on a single chip to form an XY array. In this example, the gate electrode 7 and the source electrode 3
Since the electrodes 6 are separated by an insulating layer 38, a switching matrix is realized between the two electrodes 7 and 36 that allows XY addressing.

Next, a specific example in which the SIT manufacturing method according to the present invention is applied to a buried gate type SIT will be described with reference to FIGS. 8A to 8H. The manufacturing process from FIG. 8A to FIG. 8C is the same as that explained for FIGS. 5A to 5C, but the region 21 in which the impurity element is diffused is the control gate region 16 and the shielding region in FIG. 5C. In place of the gate region 18 is used as a buried gate region, and in place of the SiO ₂ layer 24 that will be present in the finished device in FIGS. 5A-5C.
The two steps differ slightly in that in FIGS. 8A-8C, a SiO ₂ layer 25 is used which will be removed later.

Next, after removing the SiO ₂ layer 25 on the surface of the structure,
An n ^- epitaxial layer 12b, identical to n ^- layer 12a, is epitaxially grown thereon and heated (FIG. 8D). At this time, a suitable process is added to form the gate electrode 60 (FIG. 4).

A SiO ₂ layer 24 is deposited on the surface of the n ^- layer 12b,
Portions 62 corresponding between the gate regions 21 are removed by etching (FIG. 8F). Then this SiO ₂
Using the layer 24 as a mask, the n ^- layer 12b is doped with an acceptor impurity such as As through the opening 62, and then heated to form the source region 14 (FIG. 8F).

Thereafter, the source electrode 36 is formed through the opening 62 (FIG. 8G), and Al is vapor-deposited on the other main surface of the substrate 10 to form the drain electrode 52, thereby completing the buried gate type SIT as an integrated circuit ( Figure 8H).

According to the present invention, by ion-implanting an element lighter than the impurity element to be doped at a plurality of different implantation depths and annealing it, it is possible to thermally diffuse the impurity with anisotropy in the depth direction. .
This makes it possible to manufacture a vertical SIT in which the gate region is formed deeply in the vertical direction, that is, in the thickness direction of the structure. Further, when designing a device, there is no need to set the inter-gate spacing in advance with lateral heat diffusion in mind, and a uniform element can be provided.

Since the present invention has such characteristics, it can be advantageously applied to a region to be formed particularly deeply, such as a shielding gate region. By forming this deeply, the SIT can achieve good isolation between elements as mentioned above.
is provided. Therefore, the deep region forming process according to the present invention may be applied only to the control gate region.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view conceptually showing the structure of a non-split gate type SIT as an example, Figures 2 and 3 are cross-sectional views conceptually showing the structure of a split gate type SIT as an example, and Figure 4 is a cross-sectional view conceptually showing the structure of a non-split gate type SIT. FIGS. 5A to 5M are cross-sectional views conceptually showing the structure of a gate type SIT as an example.
6A and 6B are graphs showing an example of implanted ion concentration profile used to explain the process of forming a deep impurity region according to the present invention; FIG. is a cross-sectional view showing an example of a deep impurity region formed according to the present invention, and FIGS. 8A to 8H are explanatory cross-sectional views showing step-by-step an example of a process in which the manufacturing method according to the present invention is applied to a buried gate type SIT. It is. 10...n ⁺ substrate, 12... n ^- epitaxial layer, 14... source (drain) region, 16...
Control gate region, 18... Shielding gate region, 20... Gate region, 21... Buried gate, 32... Light element ion.

Claims (1)

[Claims] 1. A method for manufacturing an SIT (static induction transistor) in which a gate region is formed in a semiconductor layer including a channel region, which method includes the steps of: an implantation step of implanting from the surface, and implanting ions of an inert element lighter than the impurity element into the gate region at different implantation depths so that the concentration of the lighter inert element ions shows a plurality of distributions in the depth direction of the semiconductor layer. implantation is performed a plurality of times, the peak of the distribution of the shallowest implantation among the plurality of implantations substantially coincides with the peak of the distribution of the active impurity element ions, and the dose amount of each of the plurality of implantations is equal to the concentration of the active impurity element ions. an implantation step in which impurity element ions are implanted from the surface of the semiconductor layer at a dose higher than that of the implantation so that lattice defects are basically generated only in the depth direction; and a semiconductor layer subjected to the implantation and implantation steps. annealing at a relatively low temperature of 900° C. or lower to diffuse the implanted active impurity element ions anisotropically in the depth direction, thereby forming the gate region into the semiconductor. A method for manufacturing a static induction transistor, characterized in that the layer is formed with anisotropy that is deep in the depth direction from the surface and shallow in the lateral direction perpendicular to the depth direction. 2. In the method described in claim 1,
A manufacturing method characterized in that the injection step precedes the implantation step. 3. In the method described in claim 1,
A manufacturing method characterized in that the implanting step precedes the implanting step. 4. In the method described in claim 1,
A manufacturing method characterized in that the implantation step includes a step of heating the semiconductor layer at a relatively low temperature after implanting the impurity element. 5. In the method described in claim 1,
The semiconductor layer is an epitaxially grown layer with a relatively low impurity concentration formed on a semiconductor substrate,
A manufacturing method characterized in that the impurity element includes at least one element selected from the group consisting of B, Al, and Ga. 6. In the method described in claim 5,
A manufacturing method characterized in that the light element includes at least one of H and He. 7 In the method described in claim 5,
A manufacturing method characterized in that the relatively low temperature is in the range of 500°C to 900°C. 8. In the method described in claim 6,
A manufacturing method, wherein the plurality of distributions include three distributions. 9. In the method described in claim 1,
A manufacturing method characterized in that the SIT includes a surface gate type SIT. 10. The manufacturing method according to claim 1, wherein the SIT includes a buried gate type SIT.