JPH0439949A - Test jig for semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate test without raising troubles such as terminal deformation in a semiconductor device progressed in shrink by providing the second group of electrodes for test probe contact. CONSTITUTION:In a test action of a semiconductor device 2 using a test jig A, raising a probe support plate 17 located below the jig A makes an elastic press-contact of probe contactors 19 with the bottom of the second electrode 13. Each contactor 19 is connected to a test head 25 via a signal line 20, a spring probe 24 and the like with the result that the electric measurement of the device 2 is made from a predetermined test program via the contactors 19. Indirect contact of terminals of the device 2 with test probes via electrodes 13 allows even a semiconductor device of small terminal pitch to make electric continuity with test probes simply and exactly and to prevent troubles in handling.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test jig used when testing the electrical characteristics of semiconductor devices such as ICs.

[Conventional technology]

Fig. 6 shows the overall appearance of a conventional test tray configured to carry a plurality of semiconductor devices in a lined manner for testing, and Fig. 7 shows a cross section of the main parts showing the test form. In the example shown in FIG. 0, a surface-mount QFP (QuadFlat Package) type semiconductor device is taken as an example.

In these figures, 31 is a test tray made of heat-resistant plastic, and on the top surface of the test tray 31,
Partition walls 34 having a substantially rectangular shape in plan view are arranged vertically and horizontally at predetermined pitches, and in the center of each of these partition walls 34 is formed a support 32 on which the semiconductor device 2 is mounted. A circumferential groove 33 that surrounds the support base 32 is formed in the inner peripheral portion of the partition wall 34 . In this test tray 31, the package part of the semiconductor device 2 is positioned on the stand 32, and at the same time, in this state, the group of 8 terminals provided on the semiconductor device 2 faces the circumferential groove 33. ing.

As shown in FIG. 7, the test device for testing the electrical characteristics of the semiconductor device 2 is one in which the holder of the test tray 31 is placed above the semiconductor device 2 mounted in a predetermined attitude on a stand 32. A probe contactor 35 consisting of a large number of leaf springs arranged corresponding to each of the 8 groups of terminals of the semiconductor device 2 is connected to the support plate 3 via a pair of upper and lower insulators 36.
7, each probe contactor 35 is connected to the test head 42 via the socket 38, relay board 39, test board 40, spring probe 41, etc.
The test head 4 is configured to be electrically connected to the test head 4.
2 and a test circuit section (not shown) are connected by wiring.

By the way, regarding the test, please use the test tray 3 mentioned above.
A plurality of test trays 31 are stacked one on top of the other and set in a part of the loader, and the test trays 31 are taken out one by one from this Rogue part and transported to the position where the above-mentioned test device is located. The test trays 31 are processed.

When the test tray 31 is transported to a position directly below the test device and positioned, the probe contactor 35 of the test device is inserted into one partition wall 3 on the test tray 31.
Lower the test device so that it faces inside the test tray 3.
The first receiver is a vertical through hole 43 formed in the center of the stand 32.
By inserting the push-up pin 44 from below and pushing up the semiconductor device 2, the groups of terminals 8 of the semiconductor device 2 are brought into contact with the corresponding probe contacts 35, respectively. In this state, the test circuit unit measures electricity at each terminal 8 based on a predetermined program and collects test information.

When the test of one semiconductor device 2 is completed, the push-up pin 44 is lowered, the test tray 1 is transported at a fixed pitch, and the next semiconductor device 2 is tested. All semiconductor devices 2 are tested.

When the test on one test tray 31 is completed, this test tray 31 is transported and the next test tray 3 is
1 from the rogue part and repeat the above process.

[Problem to be solved by the invention]

In the above-mentioned conventional test equipment, since the probe contactor 35 is brought into direct contact with the terminal 8 of the semiconductor device 2, it is difficult to detect the presence of the semiconductor device. If the pitch of the 8 groups of terminals of lt2 is relatively large, for example 1.27 mm, there will be no interference with the probe contacts 35 arranged at the same pitch, but if the pitch is 0.8 mm, 0.65 mmQ, 5 mm, etc. In cases where the pitch dimension has been shrinked,
Unless the relative alignment between the group of probe contacts 35 and the group of terminals 8 of the semiconductor device 2 is performed with extremely high precision, it will be difficult to bring the corresponding ones into contact with each other accurately, and the probe contacts 35 and the semiconductor device 2 that do not correspond will be difficult to contact. There is a risk that the test may become impossible due to interference with the terminal 8 of the terminal 8.

By the way, in order to test the semiconductor device 2 which has been highly shrinked, the semiconductor device 2 is individually taken out from the test tray 31 and mounted in a dedicated test socket (not shown). It is necessary to handle the terminals 2 one by one, and there is a great risk of deforming the terminals 8 of the semiconductor device 2 at that time.

The present invention was devised in view of these circumstances, and provides a test treatment that allows easy testing of semiconductor devices that are highly shrinkable without causing problems such as deformation of terminals. The purpose is to provide tools.

[Means to solve the problem]

In order to achieve the above object, the present invention has the following configuration.

The test jig for a semiconductor device of the present invention includes a holding part in which a semiconductor device having a large number of terminals arranged in parallel on its outer periphery is positioned and held in a fixed posture, and a holding part in which the semiconductor device is held in the holding part. a first electrode group provided on the holding portion so as to contact each terminal of the holding portion; and a second electrode for contacting a test probe that is electrically connected to each of the first electrode groups and provided around the holding portion. group, and the second electrode group is arranged at a pitch larger than the pitch of the first electrode group.

[Effect]

In the configuration of the present invention, the terminals of the semiconductor device are not brought into direct contact with the test probes, but the test probes are brought into contact with the second electrodes, which are made larger than the arrangement pitch of the terminals of the semiconductor device. Because the terminals are brought into indirect contact with the terminals of the semiconductor device, it is possible to properly conduct the semiconductor device and the test equipment even if the semiconductor device is shrinking, without having to perform particularly high-precision alignment. It becomes possible.

〔Example〕

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

An embodiment of the present invention is shown in FIGS. 1 to 5.

Figure 1 is a longitudinal cross-sectional view of the test jig, Figure 2 is its plan view,
Figure 3 is a perspective view of the test tray, Figure 4 is a perspective view of the test tray,
FIG. 5 is a partially cutaway side view showing the test configuration.

Here, as shown in FIG. 4, an example is given in which a test tray is constructed by equipping a plurality of test jigs A arranged vertically and horizontally at a predetermined pitch on the upper surface of a substrate 1 made of heat-resistant plastic. .

As shown in FIGS. 1 to 3, each test jig A includes an insulating base 3, a rectangular cylindrical frame 11, a first electrode 9,
It consists of a second electrode 13.

The insulating base 3 has a rectangular cylindrical support wall 4 extending upward, and a circumferential groove 4a is formed on the upper end surface of the support wall 4 to engage and hold the puff cage portion of the semiconductor device 2 in a fixed posture. A floating plate 6 supported by a spring 5 is installed in a recess surrounded by a support wall 4 so as to be movable up and down. A large number of vertical partitions 7 are arranged in parallel on the outer peripheral surface of the insulating base 3, and between each vertical partition 7, a first electrode 9 formed of a spring material so as to be elastically bendable up and down. is interposed.

With the semiconductor device 2 supported by the support wall 4, each terminal 8 of the semiconductor device 2 is inserted between each vertical partition 7 and faces the upper end surface of the first electrode 9 without contacting it. It has become. This circumferential groove 4a corresponds to a holding portion described in the claims.

Further, the frame 11 has a flange extending radially outward on the outer peripheral portion of its lower end, and is screwed to the substrate 1 constituting the test tray via this flange. This frame 1
An insulating plate 10 is attached to the lower opening of 1, and the insulating base 3 is fixed to this insulating plate 10, and the first electrode 9 is implanted therein. Moreover, cylindrical conductive bottles 12 are embedded in several places in the circumferential direction of this frame 11 so as to penetrate vertically, and cylindrical second electrodes 13 with flanges are fitted and attached to the upper and lower ends of the conductive bottles 12, respectively. has been done. The first and second electrodes 9.13 are provided in the same number as the terminals 8 of the semiconductor device 2, and the arrangement pitch of the first electrodes 9 is set to be approximately the same as the pitch P1 of the terminals 8 of the semiconductor device 2. , the arrangement pitch P8 of the second electrodes 13 is set larger than the pitch P of the terminals 8 of the semiconductor device 2.

The first electrode 9 is connected to the second electrode 13 via a conductive bottle 12 and a conductive wire.

Next, a test operation of the semiconductor device 2 using the test jig A described above will be explained based on FIG.

The semiconductor devices W2 to be tested are mounted in loft units on a test jig A on a test tray shown in FIG. 4, and a test process is carried out.

In the test process, a plurality of test trays are stacked on a portion of a loader of a test device (not shown) and sent. The lowest one of the stacked test trays is taken out and conveyed by a fixed pitch conveyance mechanism (not shown), and the first test jig A to be tested is set at the test position.

When the test tray stops, the cylinder 14 placed above the test jig A is lowered, the urethane rubber 15 provided at its lower end presses the package part of the semiconductor device 2 from above, and the floating plate 6 is moved by the spring 5. By sinking against the pressure, each terminal 8 slightly elastically bends the corresponding first electrode 9 and comes into contact with it.

In this state, the probe support plate 17 located below the test jig A is raised by the lifting plate 16. As a result, the probe contact l9, which is vertically slidably supported through the probe support plate 17 and is biased upward by the spring 18, is elastically attached to the lower surface of the lower second electrode 13 provided in the test jig A. is pressed against.

Each probe contactor 19 is connected to a test head 25 via a signal line 20, a socket 21, a relay board 22, a test board 23, a spring probe 24, etc. Electrical measurements are performed based on a predetermined test program provided on the test tray 25.

When the collection of test information for each semiconductor device 2 is completed in this way, the probe support plate 17 is lowered and the cylinder 14 is raised, and then the test tray is transported at a fixed pitch to the second test jig. Set A to the predetermined test position.

Thereafter, the above process is repeated to perform a test for each test tray. It should be noted that when the test of - test trays is completed, each test tray is classified according to the collected and stored quality data of each semiconductor device 2.

In the above embodiment, the probe contactor 19 is made to act on the lower second electrode 13 of the test jig A, but it can also be made to act on the upper second electrode 13. Further, each test jig A may be provided with a lid that closes the upper opening of the frame 11, and this lid may function as a substitute for the cylinder 14 described above.This lid is used to protect the semiconductor device W2. Helpful.

〔Effect of the invention〕

As explained above, in the present invention, the test probe is not brought into direct contact with the terminal of the semiconductor device as in the conventional method.
The terminals of the semiconductor device and the test probe are brought into indirect contact via a second electrode provided near the semiconductor device holding portion in the test jig. In this way, the arrangement pitch of the second electrodes can be set larger than the terminal pitch of the semiconductor device, so even semiconductor devices with a small terminal pitch can be easily and accurately electrically connected to the test probe. At the same time, it does not cause handling problems like the conventional one.

[Brief explanation of the drawing]

Figures 1 to 5 relate to an embodiment of the present invention, in which Figure 1 is a longitudinal sectional view of a test jig, Figure 2 is a plan view of the test jig, and Figure 3 is a perspective view of the test jig. , FIG. 4 is a perspective view of the test tray, and FIG. 5 is a partially cutaway side view showing the test form. Further, FIGS. 6 and 7 relate to a conventional example, with FIG. 6 being a perspective view of a test jig, and FIG. 7 being a longitudinal sectional view showing a test form. A...Test jig 2...Semiconductor device 3...
・Insulating base 4...Supporting wall 4a...Peripheral groove (
Holding part) 8... Terminal 9 of semiconductor device... First electrode 11... Frame 13... Second electrode FIG.

Claims (1)

[Claims] (1) A holding part in which a semiconductor device having a large number of terminals arranged in parallel on its outer periphery is positioned and held in a fixed posture; a first electrode group provided on the holding part; and a second electrode group for contacting a test probe that is electrically connected to each of the first electrode groups and provided around the holding part.
an electrode group, and the second electrode group is arranged at a pitch larger than the pitch of the first electrode group.