JPH0439698B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention provides a watch dog timer (hereinafter referred to as
The present invention relates to an abnormality detection device for a central processing unit that includes a central processing unit equipped with a (abbreviated as WDT) circuit.

(Prior art) A WDT circuit monitors the operation of a central processing unit (hereinafter referred to as CPU), that is, the running of a program.
If an abnormality is detected (even after a certain period of time has passed)
If the WDT is not cleared and a time-up occurs), the CPU is reset and initialization is started.

In conventional CPUs with WDT circuits that operate in this way, even when the power is turned on,
The system is configured so that the entire system, including the CPU, is initialized in the same way that an error occurs in the CPU.

(Problem to be solved by the invention) For this reason, in a conventional device including a CPU, it is difficult to determine whether the cause of restarting after starting operation is due to the power being turned on or due to time-up of the WDT circuit. Impossible to recognize or WDT
It was not possible to know the number of times the circuit detected an abnormality. Therefore, the CPU that occurred after installing the CPU
There was a problem that no history of the number of abnormalities was kept, making it impossible to analyze abnormal system behavior.

The present invention has been made in view of these problems, and its purpose is to make it possible to count the number of abnormality detections by the WDT circuit.
The object of the present invention is to realize an abnormality detection device that can easily analyze abnormalities in a system including a CPU, malfunctions in programs, etc.

(Means for Solving the Problems) The present invention, which solves the above-mentioned problems, monitors the operations of a central processing unit, this central processing unit, and other processing units coupled to this central processing unit, and detects abnormalities. In a device equipped with a watchdog timer circuit that resets each processing unit when a central processing unit occurs, the central processing unit is reset by a power-on signal output from the power supply section when the power is turned on, and the central processing unit is reset after restarting. A watchdog timer flip-flop is provided which is set by a signal output from the central processing unit, and the central processing unit is configured to record the state of the watchdog timer flip-flop after the central processing unit is restarted. A watchdog timer counter is provided that is read, incremented when the relevant state is active, and reset when it is inactive. This is an abnormality detection device for a central processing unit that allows you to know the number of times a timer circuit has timed up.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the diagram, 1 is the CPU, 2 is this CPU1
Other processing devices 3 connected via a bus (not shown) are a power supply unit that supplies power to the CPU 1 and other processing devices 2. 4 is the WDT circuit,
5 is a watch/dog/timer/flip/flop (hereinafter referred to as
(abbreviated as WDTF), 6 is the or gate.

The OR gate 6 receives a power-on signal output from the power supply unit 3 when the power is turned on, and a power-on signal output from the WDT circuit 4 when the WDT times out.
WDT signal is input, and the OR output of these signals and the signal is given to each reset terminal of the CPU 1 and other processing devices 2,
Restart the CPU 1 and other processing devices 2.

WDTTF5 is a power-on signal from power supply section 3
PON is applied to the reset terminal RS, and CPU1
A signal (WDTF) output by the program is applied to the set terminal ST.
Therefore, this WDTF 5 is reset when the power is turned on, and is set by the CPU 1 after rebooting. In addition, the output signal WF indicating the state of WDTF5 is
It is applied to the CPU 1 and can be read from the program within the CPU 1.

Here, the CPU 1 is provided with a watchdog timer counter (WDT counter) as shown in the flowchart of FIG.
The count value is incremented or reset in accordance with the signal WF indicating the state from the WDTF5.

Next, the operation of the device configured as described above will be explained separately into the operation when the power is turned on and the operation when the WDT time-up occurs.

[Operation at power-on] When the power is turned on, a power-on signal is output from the power supply unit 3. This power-on signal resets the WDTF 5 and is applied to the reset terminals of the CPU 1 and other processing devices 2 through the OR gate 6, thereby restarting them.

When the CPU 1 is restarted, the program of the CPU 1 is initialized.

FIG. 2 is a flowchart of the operations executed by the CPU 1 after initialization starts according to this program. The CPU 1 first reads the output signal WF from the WDTF 5 and determines whether this signal WF is active or inactive (step 1). Here, WDTF5 has already received the power-on signal.
Since it is in the reset state by PON,
The output signal WF from the WDTF5 is inactive. From this, CPU1 recognizes that the current reboot is due to the power being turned on, and
Reset the WDT counter built into CPU1 (step 2). Further, the CPU 1 outputs a set signal SF to the WDTF 5 to put the WDTF 5 in the set state (step 3). After the above processing, the CPU 1 moves on to the next processing (step 4).

[Operation when the time-up of the WDT circuit occurs] When the time-up of the KDT circuit 4 occurs, the WDT circuit 4 outputs a signal. This signal is
The signal is given to the CPU 1 and other processing devices 2 through the OR gate 6, and these are restarted.
When the CPU 1 is restarted, the CPU 1 is initialized and performs the same operation as when the power is turned on, according to the flowchart in FIG. 2. That is, CPU1 is
The output signal WF from the WDTF 5 is read and it is determined whether this signal WF is active or inactive (step 1). Here, WDTF5 processes the program at power-on (step 3) as described above.
Since it is in the set state by
The output signal WF output from 5 is active. From this, in this step 1, CPU 1 understands that the current restart is WDT circuit 4.
Recognizing that this is due to time-up, the process moves to step 5, where the WDT counter in the CPU 1 is incremented. After the above processing,
CPU1 moves on to the next process.

Due to this operation, CPU1 calculates the count value of the built-in WDT counter from when the power is turned on.
You can know the number of times the WDT circuit times up.

(Effect of the invention) As explained above, according to the present invention, WDT
The number of abnormality detections by the circuit can be counted, so
Failures such as system failures and program malfunctions can be easily analyzed from the count value of the WDT counter. The present invention is suitable for analyzing abnormalities with low reproducibility that occur after installing a CPU.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a flowchart showing an example of the operation. 1...CPU, 2...Other processing devices, 3...Power supply unit, 4...WDT circuit, 5...WDTF, 6...Gate.

Claims (1)

[Scope of Claims] 1. A watchdog that monitors the operation of a central processing unit, this central processing unit, and other processing units coupled to this central processing unit, and resets each processing unit when an abnormality occurs. - In a device equipped with a timer circuit, a watch that is reset by a power-on signal output from the power supply unit when the power is turned on, and is set by a signal from the central processing unit after the central processing unit is restarted. A dog timer flip-flop is provided, and the central processing unit reads the state of the watch dog timer flip-flop after the central processing unit is restarted, is incremented when the state is active, and is incremented when the state is inactive. A central processing unit is equipped with a watchdog timer counter that is reset when the watchdog timer is turned on, and the number of times the watchdog timer circuit has timed up since the power was turned on can be determined from the counted value of the watchdog timer counter. Equipment abnormality detection device.