JP2011022833A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor for quickly recovering system abnormality without intervention of a serviceperson or a call center. <P>SOLUTION: Every time a time measuring reset signal C1 is outputted by a CPU 10, a clock part 13 starts time measuring, a WDT (Watch Dog Timer) forced reset circuit 20 outputs a CPU reset signal C3 as a measured time reaches a preset time for monitoring, and the CPU 10 is forced to reset. When operation start of the CPU 10 is caused by the forced reset, power supply by a power supply circuit 18 is started again after it is stopped for a prescribed period, and a system is restarted. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an information processing apparatus such as a personal computer or a POS (Point Of Sales) terminal provided with a function to cope with processing stoppage due to an abnormality.

  Conventionally, in an information processing apparatus such as a personal computer or a POS terminal, various inventions have been made in which a means for returning from the abnormal state and restarting the process when some abnormality occurs and it is difficult to continue the process. ing. (For example, see Patent Document 1)

  Information processing apparatuses such as POS terminals used for customer service are required to quickly return from an abnormal state so as not to hinder business continuity. However, the store clerk who is not familiar with the recovery method cannot deal with the abnormal state appropriately. Therefore, it was necessary for the store clerk to carry out recovery work while waiting for the arrival of a specialized service person or receiving instructions from the call center via telephone.

  As described above, the information processing apparatus cannot be used until waiting for the arrival of the service person or during the restoration work while exchanging with the call center, which hinders the operation of the store. At this time, a customer who wants to pay may be kept waiting for a long time, which may damage the credit of the store.

  The present invention has been made based on such circumstances, and an object thereof is to provide an information processing apparatus capable of quickly recovering from a system abnormality without intervention of a service person or a call center.

  In order to solve the above-described problems, the present invention provides a control unit that repeatedly executes an operation program including a routine for outputting a reset signal in an information processing apparatus that operates by receiving supply of operation power from a power supply unit, and the control unit Each time the reset signal is output from a watchdog timer that forcibly resets the control unit in response to reaching a preset monitoring time, and the control unit When the operation start is caused by a forced reset by the watchdog timer, the power supply unit includes a restarting unit that restarts the system by stopping the power supply by the power supply unit and then restarting the system. It is said.

  According to the present invention in which such measures are taken, it is possible to provide an information processing apparatus that can quickly recover from a system abnormality without the intervention of a service person or a call center.

The perspective view of the POS terminal which is the information processing apparatus in one Embodiment of this invention. The block diagram which shows the control circuit of the POS terminal in the same embodiment. FIG. 3 is a schematic diagram showing a data structure of a setting RAM in the same embodiment. The flowchart of the process of the POS terminal in the embodiment. The flowchart of the process of the POS terminal in the embodiment.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. This embodiment is a case where the present invention is applied to a POS terminal 1 used for accounting processing in a merchandise sales store such as a convenience store or a service providing store such as a restaurant.

First, the hardware configuration of the POS terminal 1 that is an information processing apparatus will be described.
FIG. 1 is an external perspective view of the POS terminal 1. The POS terminal 1 includes a base unit 2 on which a control circuit is mounted, a display 3, a keyboard 4, a key device 5, a receipt printer 6, and the like.

  The display 3 is an LCD (Liquid Cristal Display) that selectively displays various types of information necessary for merchandise registration work. The keyboard 4 has various operation keys such as a numeric key used for numerical input, an alphabet key used for character input, a PLU (Price Look Up) key for declaring the start of product registration work, and a close key for declaring the close of product registration work. It has. The key device 5 is a key switch that includes a keyhole that fits into a dedicated key possessed by a store clerk, and that receives a turning operation in a state where the key is inserted into the keyhole. The key device 5 switches processing modes such as a registration job mode for executing a product registration job and a maintenance mode for executing various settings in accordance with the stop position of the rotation operation of the keyhole.

  The receipt printer 6 is a thermal printer that issues a receipt in which transaction details and commercial information of a store are printed on thermal paper in response to an operation of a lock key provided on the keyboard 4.

  FIG. 2 is a block diagram showing a control circuit of the POS terminal 1. The control circuit includes a CPU (Central Processing Unit) 10 that functions as a control center. The CPU 10 has a ROM (Read Only Memory) 11, a RAM (Random Access Memory) 12, a clock unit 13, a display control circuit 14, an input control circuit 15, a printer control circuit 16, a buzzer control circuit 17, and a power supply unit. A power supply circuit 18, an OST (One Shot Timer) control circuit 19, and a WDT (Watch Dog Timer) forced reset circuit 20 are connected via a bus line 21 such as an address bus or a data bus. A control circuit is configured by connection. The control circuit operates by receiving power supply from an external power source 30 such as a commercial AC power source connected via an outlet or the like.

  The ROM 11 is a non-volatile memory that stores fixed data such as a program necessary for the basic operation of the POS terminal 1. The RAM 12 forms various working storage areas according to the processing scene.

  The clock unit 13 counts the time in response to a command from the CPU 10 and resets the timing operation in response to the timing reset signal C1 from the CPU 10. The clock unit 13 includes a setting RAM 131 that stores a WDT flag F described later. The clock unit 13 and the setting RAM 131 are connected to a battery 132 that forms an energization path and supplies power when power supply from the external power supply 30 to the POS terminal 1 is stopped. Therefore, even when the power supply from the external power supply 30 is stopped, the clock unit 13 can continue the clocking operation, and the setting RAM 131 can maintain the stored contents.

  The display control circuit 14 connects the display device 3 and controls the screen display of the display device 3 based on a display command from the CPU 10. The input control circuit 15 connects the keyboard 4 and the key device 5, and outputs an electrical signal output according to an operation key pressed on the keyboard 4 and an electrical signal output according to the rotation stop position of the key device 5. The data is taken in, converted into digital data, and notified to the CPU 10. The printer control circuit 16 controls the receipt printing operation by the receipt printer 6 in response to receiving a print command from the CPU 10. The buzzer control circuit 17 connects the buzzer device 171 and sounds the buzzer device 171 in response to a command from the CPU 10 to generate a predetermined beep sound.

The OST control circuit 19 is configured using electronic components such as relays and discrete components, and implements a one-shot timer function using the clock unit 13. Specifically, when a predetermined command is received from the CPU 10, the clock time of the clock unit 13 starts to be monitored, and the clock time of the clock unit 13 is set to the OST time T _OST (second monitoring time) designated by the command. On the condition that the power has been reached, a power-on signal C2 for starting power supply to each device is supplied to the power supply circuit 18.

The power supply circuit 18 and the OST control circuit 19 form a current path when the power supply from the external power supply 30 to the POS terminal 1 is stopped, and supply a power supply necessary for the operation of both the circuits 18 and 19. It is connected. The power supply circuit 18 converts the AC voltage supplied from the external power supply 30 into a DC voltage and supplies it to each device of the POS terminal 1, and charges the battery 132 and the battery 191.
The battery 132 and the battery 191 constitute a standby power supply unit in the present embodiment.

The WDT forced reset circuit 20 is configured using electronic components such as relays and discrete components, and implements a watchdog timer function using the clock unit 13. Specifically, the time keeping time of the clock unit 13 is monitored in a state where the system is activated, and the time keeping time reaches the WDT time T _WDT (monitoring time) set by the command from the CPU 10. A CPU reset signal C3 for forcibly resetting the operation is supplied to the CPU 10.

  Here, the setting RAM 131 which is a flag storage unit in the present embodiment will be described. FIG. 3 is a schematic diagram showing the data structure of the setting RAM 131. The relative address “offset Ah1” of the RAM 131 stores a WDT flag F indicating whether or not the timepiece unit 13 is measuring time by the watchdog timer function. When the timepiece unit 13 is measuring time by the watchdog timer function at the time of system operation or the like, the WDT flag F is set (on) to “1”. On the other hand, when the clock unit 13 is not in a timing operation by the watchdog timer function, such as when the system is normally terminated, the WDT flag F is set (off) to “0”.

Next, the operation of the POS terminal 1 configured as described above will be described.
At the beginning of the activation of the POS terminal 1 system, the WDT monitoring program stored in the ROM 11 is loaded into the RAM 12. Thereafter, the WDT process according to the flowchart shown in FIG. 4 is repeatedly executed by each unit of the POS terminal 1. Note that the processing is executed resident in the system, and does not interfere with other processing such as application execution even during execution of the processing. Hereinafter, the flow of the WDT process will be described with reference to FIG.

First, the CPU 10 issues a command to the WDT forced reset circuit 20 to set the WDT time T _WDT to, for example, 60 seconds (ST101), and causes the clock unit 13 to start measuring time (ST102). The WDT time T _WDT to be set in the WDT forced reset circuit 20 is set in advance in the ROM 11, and the CPU 10 accesses the ROM 11 and acquires the time.

The clock unit 13 that has started the time measuring operation accesses the setting RAM 131 and sets the WDT flag F to “1” (ST103). The WDT forced reset circuit 20 in which the WDT time T _WDT is set starts monitoring the time measured by the clock unit 13.

Thereafter, the CPU 10 monitors the time measured by the clock unit 13 until the reset time T _RE (T _RE ≦ T _WDT ) of, for example, 50 seconds is reached (ST104). Note that the reset time T _RE is preset in the ROM 11, and the CPU 10 accesses the ROM 11 and acquires the time.

Eventually, when the time measured by the clock unit 13 reaches the reset time T _RE (Yes in ST104), the CPU 10 outputs a timed reset signal C1 to the clock unit 13 (ST105). In response to the output of the clock reset signal C1, the clock unit 13 stops the clocking operation (ST106), and accesses the setting RAM 131 to set the WDT flag F to “0” (ST107). Thereafter, the clock unit 13 resets the time measurement and starts again (ST101), accesses the setting RAM 131 and sets the WDT flag F to “1” (ST102).

When a system abnormality such as a freeze of various IC circuits constituting the control circuit, a decrease in power supply voltage supplied from an external power source, or a system lock occurs while the processing is repeated, the processing by the CPU 10 slows or stops. To do. That is, because the CPU 10 does not output the time reset signal C1 or the output timing is delayed, the time measuring operation is not reset even if the time measured by the clock unit 13 exceeds the reset time _TRE . Processing executed in such a case will be described with reference to the flowchart shown in FIG. This process constitutes restarting means in the present embodiment.

When the clocking operation of the clock unit 13 is not stopped and the clocking time of the clock unit 13 has exceeded the WDT time T _WDT , the CPU reset signal C3 that generates an interrupt to the CPU 10 is output from the WDT forced reset circuit 20. Receiving this signal C3, the CPU 10 stops the process being executed and resets its operation (ST201).

Thereafter, the CPU 10 refers to the setting RAM 131 to determine whether or not the WDT flag F is set to “1” (ST202). In other words, it is specified whether or not the operation start of the CPU 10 is caused by a forced reset by the watchdog timer function. If the operation start of the CPU 10 is caused by the forced reset by the watchdog timer function, the WDT flag F is set to “1” (Yes in ST202). At this time, CPU 10 is sets the OST time T _OST of example 3 seconds OST control circuit 19 (ST 203), is set to "0" WDT flag F to access the setting RAM 131 (ST 204). The OST time T _OST is set in the ROM 11 in advance, and the CPU 10 accesses the ROM 11 and acquires the time.

  Further, the clock unit 13 is started to measure time (ST205), and a power supply stop command is output to the power supply circuit 18. Upon receiving this command, the power supply circuit 18 stops the power supply from the external power supply 30 to each device of the POS terminal 1.

  When the power supply by the power supply circuit 18 is stopped, an energization path from the battery 132 to the timepiece unit 13 and the setting RAM 131 is formed and power is supplied. Therefore, as described above, even after the power supply by the power supply circuit 18 is stopped, the timepiece unit 13 continues the clocking operation, and the stored contents of the setting RAM 131 are retained.

In addition, a current path from the battery 191 to the OST control circuit 19 is formed and power is supplied. The OST control circuit 19 receives the power supply from the battery 191 and monitors the time measured by the clock unit 13. When the time measured by the clock unit 13 reaches the OST time _TOST , the OST control circuit 19 outputs a power-on signal C2 to the power supply circuit 18. Receiving this signal C2, the power supply circuit 18 resumes power supply from the external power supply 30 to each device. When the power supply is resumed, a system restart process is started (ST206). Specifically, the BIOS is read, and abnormality diagnosis and initialization of each device including the CPU 10 are performed.

The reason why the power supply by the power supply circuit 18 is stopped after a predetermined time and then restarted to restart the system is to completely initialize each device and eliminate the influence of the failure. Therefore, it is desirable to set the OST time T _OST to a length that is sufficient for the charge to disappear from electronic components such as capacitors that constitute each device of the POS terminal 1.

  In the restart of the system, when the CPU 10 that has been initialized by the BIOS starts operating (ST201), the setting RAM 131 is referred to and it is determined whether or not the WDT flag F is set to "1" (ST202). . If the power supply from the power supply circuit 18 is once stopped by the one-shot timer function and then restarted, the WDT flag F is set to “0” (No in ST202). In this case, the system startup process being executed proceeds as usual. After the control right is transferred from the BIOS to the OS (Operating System), an application used for product data registration work is started, and a work menu screen related to the application is displayed via the display control circuit 14 on the display unit. 3 is displayed (ST207).

  When the user gives an instruction to terminate the system by operating the keyboard 4 or the like, the CPU 10 sets the WDT flag F to “0” and then shuts down the system, causing the power supply circuit 18 to stop power supply. Therefore, when the POS terminal 1 is activated after the normal system is terminated, the WDT flag F is set to “0” (No in ST202), and therefore processing using the one-shot timer function (ST203 to ST206). Is not executed.

  As described above, the POS terminal 1 according to the present embodiment temporarily stops the power supply after resetting the CPU 10 by the watchdog timer function when some trouble occurs and the operation of the CPU 10 is abnormal. Restart the system. By doing so, even when an abnormality occurs in the POS terminal 1 and the process is stopped, the user does not wait for the arrival of the service person and the user does not perform the recovery process by exchanging with the call center. The business can be resumed quickly.

Further, the time from when the power supply is stopped to when it is restarted is determined by the OST time _TOST . By adjusting the OST time T _OST to an appropriate length, it is possible to prevent the abnormality before the power supply is stopped from affecting even after the power supply is resumed.

  The clock unit 13 and the OST control circuit 19 constituting the restarting unit operate even after the power supply from the power supply circuit 18 is stopped by receiving the power supply from the battery 132 and the battery 191, respectively. In this way, a restarting unit that operates even when the power supply is stopped after the forced reset of the CPU 10 is realized.

  When the monitoring process by the watchdog timer function is being executed, the WDT flag F stored in the setting RAM 131 is set to “1”. A means for specifying whether or not the start of the operation of the CPU 10 is due to a forced reset by the watchdog timer function by referring to the value of the WDT flag F when the operation is started after the CPU 10 is reset. Realized.

  In addition, this invention is not limited to the said embodiment as it is, In an implementation stage, within the range which does not deviate from the summary, each component can be changed suitably and can be embodied.

  For example, in the above embodiment, the case where the present invention is applied to the POS terminal 1 has been described. However, it goes without saying that the present invention may be applied to an information processing apparatus such as a personal computer or other types of office computers. Nor.

  Further, although both the watchdog timer function and the one-shot timer function are realized using the clock unit 13, each timer function may be realized using a separate timer.

Further, the WDT time T _WDT , the reset time T _RE , and the OST time T _OST set in the ROM 11 may be changed by the user to any time. In this case, for example, each time is stored in a nonvolatile memory such as a flash ROM instead of the ROM 11. When the user desires to change each time, the key device 5 is rotated to set the maintenance mode, and an input column for each time is displayed on the screen display of the display device 3. An arbitrary time can be input to the input field by operating the keyboard 4, and the nonvolatile memory is stored at the time input to each input field in response to the user operating the keyboard 4 to declare the change. Update each time stored in. Thus, if the user can arbitrarily change the WDT time T _WDT , the reset time T _RE , and the OST time T _OST , a setting more suitable for the use environment of the apparatus can be realized.

  In addition, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment.

  DESCRIPTION OF SYMBOLS 1 ... POS terminal, 10 ... CPU, 13 ... Clock part, 18 ... Power supply circuit, 19 ... OST control circuit, 20 ... WDT forced reset circuit, 131 ... Setting RAM, 132, 191 ... Battery

Japanese Patent Laid-Open No. 10-31790

Claims (4)

In an information processing apparatus that operates by receiving operation power from a power supply unit,
A control unit that repeatedly executes an operation program including a routine for outputting a predetermined reset signal;
A watchdog timer that forcibly resets the control unit in response to reaching a preset monitoring time while starting a time measuring operation each time the reset signal is output from the control unit,
When the operation start of the control unit is due to a forced reset by the watchdog timer, restart means for restarting the system by restarting the power supply by the power supply unit after stopping for a predetermined time;
An information processing apparatus comprising:   In the case where the operation start of the control unit is caused by a forced reset by the watchdog timer, the restarting unit stops the power supply to the power supply unit and starts a time measurement operation, and the time measurement is previously performed. The information processing apparatus according to claim 1, wherein the power supply unit restarts the power supply and restarts the system in response to reaching the set second monitoring time. A standby power supply means for supplying a standby power supply for operating the restarting means;
The information processing apparatus according to claim 2, wherein the restarting unit operates by receiving power supply from the standby power supply unit when power supply by the power supply unit is stopped. Flag storage means for storing a flag that is turned on during the time counting operation by the watchdog timer and turned off when the system is normally terminated;
The restarting unit refers to the flag stored in the flag storage unit when the operation of the control unit starts, and when the flag is turned on, the operation start of the control unit is forced to be reset by the watchdog timer. The information processing apparatus according to claim 1, wherein the information processing apparatus is specified as being caused.

Images