JPH043941A - Manufacture of polycrystalline silicon thin-film transistor - Google Patents
Manufacture of polycrystalline silicon thin-film transistorInfo
- Publication number
- JPH043941A JPH043941A JP10488490A JP10488490A JPH043941A JP H043941 A JPH043941 A JP H043941A JP 10488490 A JP10488490 A JP 10488490A JP 10488490 A JP10488490 A JP 10488490A JP H043941 A JPH043941 A JP H043941A
- Authority
- JP
- Japan
- Prior art keywords
- deposited
- silicon nitride
- nitride film
- section
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 239000013078 crystal Substances 0.000 claims abstract description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 13
- 239000010408 film Substances 0.000 abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 8
- 239000010410 layer Substances 0.000 abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 8
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 4
- 238000000137 annealing Methods 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 238000009279 wet oxidation reaction Methods 0.000 abstract description 2
- 230000004913 activation Effects 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、多結晶シリコン薄膜トランジスタの製法に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing polycrystalline silicon thin film transistors.
従来、TPTの製造工程の簡略化のため活性層を島状に
分離して作成することが提案されている(特開昭59−
132677号)。しかしながら、この方法で得られた
第1図に示すようなTPTは。Conventionally, in order to simplify the manufacturing process of TPT, it has been proposed to separate the active layer into island shapes (Japanese Unexamined Patent Application Publication No. 1983-1999)
No. 132677). However, the TPT as shown in FIG. 1 obtained by this method.
活性M12のエツジ部〔第1図(a)の個所等〕でのゲ
ート絶縁膜13の耐圧劣化、段差〔第1図(b)の個所
等〕による配線の段切れ1段差部〔第1図(C)の個所
等〕でのゲートポリシリコン14のエツチング残等の問
題点があった。Deterioration of the breakdown voltage of the gate insulating film 13 at the edge portion of the active M12 (such as the location shown in FIG. 1(a)), and a one-step break in the wiring due to a step difference (such as the location shown in FIG. 1(b)) [FIG. 1] There were problems such as etching residues on the gate polysilicon 14 in areas such as (C).
また、TPTを高移動度にするため、半導体薄膜をアニ
ールし、結晶性を改善することが提案されている(特開
昭60−66471号)、シかしながら、そのためには
アニール工程が1工程増加することになる。Furthermore, in order to make TPT high in mobility, it has been proposed to anneal the semiconductor thin film to improve its crystallinity (Japanese Patent Application Laid-Open No. 60-66471). This will result in an increase in process steps.
本発明は、ウェハプロセスの素子分離技術(LOGO5
)を導入することにより、段差を無くするとともに、素
子分離工程において多結晶シリコン(ポリシリコン)の
結晶を大粒子化することにより、前述の2つの問題点を
一挙に解決することを目的とするものである。The present invention is a wafer process element isolation technology (LOGO5
), the aim is to eliminate the step difference and to make polycrystalline silicon (polysilicon) crystals larger in size in the element isolation process, thereby solving the two problems mentioned above at once. It is something.
本発明は、絶縁基盤上に堆積したアモルファスシリコン
薄膜のうち、トランジスタの活性領域となる部分以外の
部分を熱酸化するとともに。The present invention thermally oxidizes a portion of an amorphous silicon thin film deposited on an insulating substrate other than a portion that will become an active region of a transistor.
前記活性領域も同時に熱処理をうけ、アモルファスシリ
コンが平均結晶粒径0.5μm以上、好ましくは1μ厘
以上の多結晶シリコンに結晶成長することを特徴とする
多結晶シリコン薄膜トランジスタの製法に関する。The present invention relates to a method for manufacturing a polycrystalline silicon thin film transistor, characterized in that the active region is also subjected to heat treatment at the same time, and the amorphous silicon crystals grow into polycrystalline silicon having an average crystal grain size of 0.5 μm or more, preferably 1 μm or more.
第2図を参照して本発明の1具体例を説明する。石英の
ような絶縁基板21上に、アモルファスシリコン(a−
5i)22をLPCVD法により1000人厚に堆積し
、その上にシリコン窒化膜28をLPCVD法により1
000人厚に堆積する〔第2図(a)〕。ついで、フォ
トリソエツチング技術で活性層領域となる部分を残す。One specific example of the present invention will be described with reference to FIG. Amorphous silicon (a-
5i) 22 is deposited to a thickness of 1,000 layers by the LPCVD method, and a silicon nitride film 28 is deposited on top of it by the LPCVD method.
It is deposited to a thickness of 0,000 people [Figure 2 (a)]. Next, a portion that will become the active layer region is left by photolithography.
全体を600℃に加熱して、ウェット酸化と結晶成長を
同時併行的に行う。すなわち、この加熱処理によりシリ
コン窒化膜28の無い部分29は選択的に酸化される。The whole is heated to 600° C., and wet oxidation and crystal growth are performed simultaneously. That is, by this heat treatment, the portion 29 where the silicon nitride film 28 is not present is selectively oxidized.
1000人厚の堆積3iの完全酸化に必要な時間は約1
0時間であった。一方、この加熱処理の間にシリコン窒
化膜28で被覆されているa−3iの部分は結晶化がお
こり、約10時間の間にa−5iは平均結晶粒1μm以
上の多結晶シリコン(Poly−5i)に成長していた
。シリコン窒化膜28を全面除去した後、グー1−酸化
膜23を1000℃でトライ酸化して700人厚堆積成
する〔第2図(b)〕。The time required for complete oxidation of 1,000-layer thick deposit 3i is approximately 1
It was 0 hours. On the other hand, during this heat treatment, the portion of a-3i covered with the silicon nitride film 28 crystallizes, and during about 10 hours, a-5i becomes polycrystalline silicon (Poly-5i) with an average crystal grain of 1 μm or more. 5i). After removing the silicon nitride film 28 from the entire surface, a goo 1-oxide film 23 is tri-oxidized at 1000 DEG C. to a thickness of 700 nm [FIG. 2(b)].
つぎに、ゲートとなるPo1y−5i 24をLPCV
D法により3000人厚に堆積し、フォトリソエツチン
グ技術でパターニングした後、リン又はボロン等のドー
プ材料をイオン注入して、ソース・トレイン領域25を
形成し、層間絶縁膜26となるBPSGをLPCVD法
により6000人厚に堆積した。ドーピング材の活性化
とBPSGのフローを兼ねて900℃でアニールした後
コンタクトホールを形成し、最後に配線用金属としてA
Q27をスパッタ法で1μm堆積し、フォトリソエツチ
ング技術でパターニングした〔第2図(C)〕。Next, LPCV Po1y-5i 24, which will become the gate.
After depositing to a thickness of 3000 nm using the D method and patterning using photolithography, ions of phosphorus or boron doped material are implanted to form the source/train region 25, and BPSG, which will become the interlayer insulating film 26, is deposited using the LPCVD method. It was deposited to a thickness of 6,000 people. After annealing at 900°C to activate the doping material and flow the BPSG, a contact hole is formed, and finally A is used as a wiring metal.
Q27 was deposited to a thickness of 1 .mu.m by sputtering and patterned by photolithography (FIG. 2(C)).
このようにして得られたPo1y−Si薄膜トランジス
タの電気特性を第3図に示す。曲線(1)が従来型のも
のであり、曲線(n)が本発明実施例のものである。P
o1y−5iの平均結晶粒径が大きくなるにつれてオン
電流が増加しく移動度が増大)、オフ電流の小さい良好
なトランジスタが得られた。The electrical characteristics of the Po1y-Si thin film transistor thus obtained are shown in FIG. Curve (1) is that of the conventional type, and curve (n) is that of the embodiment of the present invention. P
As the average crystal grain size of o1y-5i becomes larger, the on-current increases and the mobility increases), and a good transistor with a small off-current was obtained.
本発明は、シリコン層の所定部署を熱酸化膜とすること
により素子分離しているので、段差が発生しない。In the present invention, elements are isolated by forming a thermal oxide film in a predetermined portion of the silicon layer, so that no step difference occurs.
また、結晶成長工程を前記熱酸化膜の形成工程で同時に
実施しているので、工程数の低減につながる。Furthermore, since the crystal growth step is performed simultaneously with the thermal oxide film formation step, the number of steps can be reduced.
第1図は、従来の方法により得られたPo1ySi薄膜
トランジスタの断面図を示す。第2図は、本発明方法実
施例の工程を(a)、(b)、(c)で示す。第3図は
、従来法により得られたPo1y−5i薄膜トランジス
タと本発明方法により得られたPo1y−5i薄膜トラ
ンジスタのそれぞれの電気特性の対比を示すグラフであ
る。
11 、21−・絶縁基板 12.22− Po1
y−Si層22′・・・a−5i層 13.2
3・・・ゲート絶縁膜14.24・=ゲートPo1y−
5iFIG. 1 shows a cross-sectional view of a Po1ySi thin film transistor obtained by a conventional method. FIG. 2 shows steps (a), (b), and (c) of an embodiment of the method of the present invention. FIG. 3 is a graph showing a comparison of the electrical characteristics of a Po1y-5i thin film transistor obtained by the conventional method and a Po1y-5i thin film transistor obtained by the method of the present invention. 11, 21-・Insulating substrate 12.22- Po1
y-Si layer 22'...a-5i layer 13.2
3... Gate insulating film 14.24.=gate Po1y-
5i
Claims (1)
うち、トランジスタの活性領域となる部分以外の部分を
熱酸化するとともに、前記活性領域も同時に熱処理をう
け、アモルファスシリコンが平均結晶粒径0.5μm以
上の多結晶シリコンに結晶成長することを特徴とする多
結晶シリコン薄膜トランジスタの製法。1. Of the amorphous silicon thin film deposited on the insulating substrate, the parts other than the part that will become the active region of the transistor are thermally oxidized, and the active region is also heat-treated at the same time, so that the amorphous silicon has an average crystal grain size of 0.5 μm or more. A method for manufacturing a polycrystalline silicon thin film transistor characterized by crystal growth on polycrystalline silicon.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10488490A JPH043941A (en) | 1990-04-20 | 1990-04-20 | Manufacture of polycrystalline silicon thin-film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10488490A JPH043941A (en) | 1990-04-20 | 1990-04-20 | Manufacture of polycrystalline silicon thin-film transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH043941A true JPH043941A (en) | 1992-01-08 |
Family
ID=14392612
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10488490A Pending JPH043941A (en) | 1990-04-20 | 1990-04-20 | Manufacture of polycrystalline silicon thin-film transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH043941A (en) |
-
1990
- 1990-04-20 JP JP10488490A patent/JPH043941A/en active Pending
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