JPH043941A - Manufacture of polycrystalline silicon thin-film transistor - Google Patents

Abstract

PURPOSE:To remove a stepped section by thermally oxidizing sections except a section as the active region of a transistor in an amorphous silicon thin-film deposited on an insulating substrate. CONSTITUTION:Amorphous silicon 22 is deposited on an insulating substrate 21, a silicon nitride film 28 is deposited on the amorphous silicon 22, and a section as an active layer region is left. When the whole is heated and wet oxidation and crystal growth are conducted simultaneously, the silicon nitride film 23 is removed extending over the whole surface and a gate oxide film 23 is dry-oxidized and formed because sections 29, in which there is no silicon nitride film 28, are oxidized selectively while the section of a-Si coated with the silicon nitride film 23 is crystallized. Poly-Si 24 as a gate is deposited and patterned, the ions of a doping material are implanted to form source-drain regions 25, BPSG as an inter-layer insulating film 26 is deposited, annealing is conducted in combination with the activation of the doping material and the flow of BPSG, a contact hole is formed, and lastly Al 27 as a metal for a wiring is deposited, and patterned.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a method for manufacturing polycrystalline silicon thin film transistors.

[Prior art]

Conventionally, in order to simplify the manufacturing process of TPT, it has been proposed to separate the active layer into island shapes (Japanese Unexamined Patent Application Publication No. 1983-1999)
No. 132677). However, the TPT as shown in FIG. 1 obtained by this method.

Deterioration of the breakdown voltage of the gate insulating film 13 at the edge portion of the active M12 (such as the location shown in FIG. 1(a)), and a one-step break in the wiring due to a step difference (such as the location shown in FIG. 1(b)) [FIG. 1] There were problems such as etching residues on the gate polysilicon 14 in areas such as (C).

Furthermore, in order to make TPT high in mobility, it has been proposed to anneal the semiconductor thin film to improve its crystallinity (Japanese Patent Application Laid-Open No. 60-66471). This will result in an increase in process steps.

〔the purpose〕

The present invention is a wafer process element isolation technology (LOGO5
), the aim is to eliminate the step difference and to make polycrystalline silicon (polysilicon) crystals larger in size in the element isolation process, thereby solving the two problems mentioned above at once. It is something.

〔composition〕

The present invention thermally oxidizes a portion of an amorphous silicon thin film deposited on an insulating substrate other than a portion that will become an active region of a transistor.

The present invention relates to a method for manufacturing a polycrystalline silicon thin film transistor, characterized in that the active region is also subjected to heat treatment at the same time, and the amorphous silicon crystals grow into polycrystalline silicon having an average crystal grain size of 0.5 μm or more, preferably 1 μm or more.

One specific example of the present invention will be described with reference to FIG. Amorphous silicon (a-
5i) 22 is deposited to a thickness of 1,000 layers by the LPCVD method, and a silicon nitride film 28 is deposited on top of it by the LPCVD method.
It is deposited to a thickness of 0,000 people [Figure 2 (a)]. Next, a portion that will become the active layer region is left by photolithography.

The whole is heated to 600° C., and wet oxidation and crystal growth are performed simultaneously. That is, by this heat treatment, the portion 29 where the silicon nitride film 28 is not present is selectively oxidized.

The time required for complete oxidation of 1,000-layer thick deposit 3i is approximately 1
It was 0 hours. On the other hand, during this heat treatment, the portion of a-3i covered with the silicon nitride film 28 crystallizes, and during about 10 hours, a-5i becomes polycrystalline silicon (Poly-5i) with an average crystal grain of 1 μm or more. 5i). After removing the silicon nitride film 28 from the entire surface, a goo 1-oxide film 23 is tri-oxidized at 1000 DEG C. to a thickness of 700 nm [FIG. 2(b)].

Next, LPCV Po1y-5i 24, which will become the gate.
After depositing to a thickness of 3000 nm using the D method and patterning using photolithography, ions of phosphorus or boron doped material are implanted to form the source/train region 25, and BPSG, which will become the interlayer insulating film 26, is deposited using the LPCVD method. It was deposited to a thickness of 6,000 people. After annealing at 900°C to activate the doping material and flow the BPSG, a contact hole is formed, and finally A is used as a wiring metal.
Q27 was deposited to a thickness of 1 .mu.m by sputtering and patterned by photolithography (FIG. 2(C)).

The electrical characteristics of the Po1y-Si thin film transistor thus obtained are shown in FIG. Curve (1) is that of the conventional type, and curve (n) is that of the embodiment of the present invention. P
As the average crystal grain size of o1y-5i becomes larger, the on-current increases and the mobility increases), and a good transistor with a small off-current was obtained.

〔effect〕

In the present invention, elements are isolated by forming a thermal oxide film in a predetermined portion of the silicon layer, so that no step difference occurs.

Furthermore, since the crystal growth step is performed simultaneously with the thermal oxide film formation step, the number of steps can be reduced.

[Brief explanation of drawings]

FIG. 1 shows a cross-sectional view of a Po1ySi thin film transistor obtained by a conventional method. FIG. 2 shows steps (a), (b), and (c) of an embodiment of the method of the present invention. FIG. 3 is a graph showing a comparison of the electrical characteristics of a Po1y-5i thin film transistor obtained by the conventional method and a Po1y-5i thin film transistor obtained by the method of the present invention. 11, 21-・Insulating substrate 12.22- Po1
y-Si layer 22'...a-5i layer 13.2
3... Gate insulating film 14.24.=gate Po1y-
5i

Claims (1)

[Claims] 1. Of the amorphous silicon thin film deposited on the insulating substrate, the parts other than the part that will become the active region of the transistor are thermally oxidized, and the active region is also heat-treated at the same time, so that the amorphous silicon has an average crystal grain size of 0.5 μm or more. A method for manufacturing a polycrystalline silicon thin film transistor characterized by crystal growth on polycrystalline silicon.