JPH0438789A - Dynamic memory - Google Patents

Abstract

PURPOSE:To surely execute the self-refresh (SRF) operation by decreasing an amplification speed of memory cell data at the time of SRF in a dynamic memory having an SRF function. CONSTITUTION:At the time of access, a signal phiSREF for showing an SRF state is L. Accordingly, at the time of access, a sense amplifier (SA) driving signal generating circuit 1 becomes active. When an SA driving signal phiS1 is inputted, an SA driving signal phiS2 is generated. A delay time from the signal phiS1 to phiS2 in this case becomes T1. In the T1 period, data amplifying signals SEN, SEP are varied slowly by the signal phiS1, but due to generation of the signal phiS2, the data amplifying signals SEN, SEP are varied suddenly and an SA 3 is operated quickly, and the amplification of a memory cell data signal B, the inverse of B is completed in the time T2.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to dynamic memory.

[Prior Art] A dynamic memory sense amplifier with a conventional self-refresh function uses two types of sense amplifier drive signals φ.
51. Memory data was amplified by φ5□.

That is, the sense amplifier drive signal φs1 drives the sense amplifier slowly, and the sense amplifier drive signals φ and 2 drive the sense amplifier relatively quickly. The sense amplifier drive signal φs1 gradually drives and amplifies the sense amplifier so that minute memory cell data does not malfunction, and when the data signal has been amplified to a certain extent, high-speed amplification is performed. The sense amplifier drive signal φ5□ is generated by the sense amplifier drive signal φ8. This was done with an appropriate delay. There was no distinction between these operations during access and during self-refresh.

[Problems to be Solved by the Invention] Since the sensing speed of memory data affects the access time during access, it is desirable that the sensing speed be faster. However, increasing the sensing speed may cause the sense amplifier to malfunction. Therefore, it is designed to maintain a sensing speed as fast as possible without causing malfunction.

On the other hand, the self-refresh operation in a dynamic memory having a self-refresh function is not related to access time. Therefore, there is no need to keep the sensing speed the same as the access speed. If the sensing speed is faster than necessary during self-refresh, there is a high probability of malfunction.

[Means for Solving the Problems] The dynamic memory of the present invention outputs a first sense amplifier drive signal and at least one second sense amplifier drive signal obtained by delaying the first sense amplifier drive signal during access. and a sense amplifier drive signal generation circuit that outputs only the first sense amplifier drive signal during self-refresh, and a plurality of transistors driven by the first and second sense amplifier drive signals, and includes a plurality of transistors that are driven by the first and second sense amplifier drive signals, and a data amplification signal generation circuit that outputs an amplification signal.

[Function] During self-refresh, the number of active transistors in the data amplification signal generation circuit is smaller than during access, the data amplification signal changes slowly and the sensing speed is slow), and the operation during self-refresh becomes more certain.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the dynamic memory of the present invention, and FIG. 2 is a diagram showing the timing of each signal.

This embodiment has a sense amplifier drive signal generation circuit 1, a data amplification signal generation circuit 2, and a sense amplifier 3.

The sense amplifier drive signal generation circuit 1 inverts the outputs of the Nandt gate 11 which inputs the inverted signal of the sense amplifier drive signal φSl and the signal φ5REF indicating the refresh state by the inverter 10, the delay circuit 2, and the delay circuit 2. , an inverter I that outputs a sense amplifier drive signal φ5□
It is composed of 3. The data amplification signal generation circuit 2 is
Sense amplifier drive signal φ, 1. Inverters 21 and 22 each invert φ8□, P-channel transistors Q, Q3 whose sources are connected to the power supply and whose gates receive the outputs of the inverters 21 and 22, and whose sources are grounded.
Sense amplifier drive signal φ, 1. N-channel transistor Q2 to which φS2 is input. Q4, and an N-channel transistor q7 whose source and drain are connected to N-channel transistors Q1 and 03 and P-channel transistors Q2 and 04, and whose gate receives a precharge signal φPBL, and outputs a data amplification signal SEP to the sense amplifier 3. , outputs SEN.

Next, the operation of this embodiment will be explained.

Signal φ5 indicating self-refresh state during access
REF is at low level. Therefore, the sense amplifier drive signal generation circuit 1 becomes active during access. As shown in FIG. 2, the sense amplifier drive signal φ5. is input, the sense amplifier drive signal φs2 is input after a while.
occurs. At this time, the delay time from the sense amplifier drive signal φ,1 to φs2 becomes T1 as shown in FIG. During the T1 period, the data amplification signals SEN and SEP change slowly due to the sense amplifier drive signal φ5□, but the data amplification signals SUN and SEP change rapidly due to the generation of the sense amplifier drive signal φs2, causing the sense amplifier 3 to operate quickly. , memory cell data signal B, amplification of B is completed at time T2.

Since the signal φ5REF is at a high level during self-refresh, the sense amplifier drive signal generation circuit 1 is inactive and the signal φ8□ is not generated. Therefore, the data amplification signals SEN and SEP are controlled by the sense amplifier drive signal φ5 from beginning to end and change slowly, and the sense amplifier 3 also slowly changes the memory cell data signal B.
, B is amplified, and the amplification ends at time T3. Note that at this time, T2<T3.

In this way, by increasing the operating time of the sense amplifier, stable operation with fewer malfunctions is ensured, and self-refresh reliability is increased.

FIG. 3 is a circuit diagram of a second embodiment of the dynamic memory of the present invention.

In this embodiment, the sense amplifier drive signal input to the data drive signal generation circuit IA is φ57. There are three signals: φ5□ and φs3. The sense amplifier drive signal generation circuit IA includes a delay circuit 14 that delays the sense amplifier drive signal φ5□, a Nant gate 15 that inputs each output signal of the inverter 10 and the delay circuit 14, and a signal φ5REF indicating a self-refresh state. A Nantes gate 16 which inputs the output signal of the delay circuit 14 and the output signal of the Nantes gate 15.16 is inverted to generate a self-refresh signal φ85. It is composed of inverters 17 and 18 that output φ and 2, respectively. The data amplification signal generation circuit 2B has a configuration in which an inverter 23, a P-channel transistor 5, and an N-channel transistor 6 are added to the data amplification circuit 2 of FIG.

In this embodiment, during access, the sense amplifier drive signal φ5
, and φ,2. The memory cell data signals B, B are amplified by the sense amplifier drive signals φ8□ and φs3 during self-refresh.

At this time, the current capacity of each transistor 01 to Q6 that drives the sense amplifier drive signals SEP and SEN is QB>Q5> and Q4>QB>02, and due to the difference in current capacity, the sense amplifier drive signal SEP and SEN are The amplifier drive signals SEN and SEP move slowly, and the same effect as in the first embodiment can be obtained.

Even when the number of sense amplifier drive signals is larger, the same effect can be obtained using a similar circuit.

[Effects of the Invention] As explained above, in a dynamic memory having a self-refresh function, the present invention can perform a self-refresh operation more reliably by slowing down the amplification speed of memory cell data during self-refresh. effective.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the dynamic memory of the present invention, FIG. 2 is a timing chart of each signal in the first embodiment of the dynamic memory of the present invention, and FIG. 3 is a circuit diagram of the first embodiment of the dynamic memory of the present invention. FIG. 3 is a circuit diagram of an embodiment of the invention. 1. IA... sense amplifier drive signal generation circuit, 2.
2B...Data amplification signal generation circuit, 3...
...Sense amplifier, φ81. φ82. φs3・
・Sense amplifier drive signal, SEP, SEN...Data amplification signal, B, B...Memory cell data signal, Q, QB, Q5...P-type MO3FE
T. Q2. Q4. Q,, Qfu...N type M
O3FET.

Claims (1)

[Claims] 1. In a dynamic memory having a self-refresh function and including a bit line sense amplifier, the bit line sense amplifier is amplified by changing the amplification speed using a pair of data drive signals, A sense amplifier drive that outputs a first sense amplifier drive signal and at least one second sense amplifier drive signal obtained by delaying the first sense amplifier drive signal, and outputs only the first sense amplifier drive signal during self-refresh. A dynamic memory comprising: a signal generation circuit; and a data amplification signal generation circuit that includes a plurality of transistors driven by first and second sense amplifier drive signals and outputs the pair of data amplification signals. .