JPH0438080B2 - - Google Patents

Abstract

PURPOSE:To eliminate the need to flow a current to a nonvolatile storage element normally and to improve the reliability of a device, by connecting the nonvolatile storage element which varies nonvolatile variation in impedance and a capacitor to the output terminal of a flip-flop, and varying the stable state of the flip-flop in power-on operation. CONSTITUTION:When C1>C2 with regard to capacity relation in a figure, an output N1' is charged more speedily than an output N1 when a current VD is fed, so the potential of the output N1' becomes higher than that of the N1. Consequently, a transistor (TR)QE1 turns on and a QE2 turns off to stabilize the flip-flop FL1 when N1=''0'' and N1'=''1''. At this time, the output N1 serves as said switching control signal and a stand-by circuit (stand-by memory cell) is not used because N1=''0''. At this time, a polysilicon fuse F is in a low impedance state. Therefore when the stand-by circuit is in use, the polysilicon fuse F is blown by, for example, a laser. In this case, the polysilicon fuse F corresponds to a high impedance state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit device suitable for use when switching a regular circuit to a spare circuit.

[Technical background of the invention]

Recently, in semiconductor integrated circuit devices, especially semiconductor memories, a regular memory cell circuit and a spare memory cell circuit are formed, and if a defective bit is found in the regular memory cell circuit during manufacturing, this defective bit can be removed. The number of devices with redundancy functions, such as replacing parts with spare memory cell circuits, is increasing. This is because even if a normal memory cell circuit has just one defective cell, the memory as a whole is defective, and such a memory is discarded as a defective product.
In other words, as memory capacity increases, the probability of defective memory cells is increasing, and if defective memory is thrown away, the cost of the product becomes extremely high. Put it away. Therefore, in order to improve the overall yield, a method has been adopted in which a spare memory cell circuit is formed and used by switching it when a part of the regular memory cell circuit is defective.

FIG. 1 is a block diagram of a semiconductor memory in which the above-mentioned spare memory cell circuit is formed. In the figure, 1 is an address buffer to which an address signal is applied, and the output from this address buffer 1 is applied to a regular address decoder 2 and a spare address decoder 3 in parallel. The decoded output of the regular address decoder 2 is given to the regular memory cell circuit 4, one row line in the regular memory cell circuit 4 is selected by this decoded output, and then connected to this selected row line. Data is stored in and read from memory cells that have been stored. Further, the decoding operation of the regular address decoder 2 is controlled by the output from the spare address decoder 3. The decoded output of the spare address decoder 3 is given to the spare memory cell circuit 5, a memory cell in the spare memory cell circuit 5 is selected by this decoded output, and data is then stored in the selected memory cell. data is read.

On the other hand, depending on the configuration of the spare address decoder 3, there may be a defective bit in the regular memory cell circuit 4, and when replacing this defective part with a memory cell in the spare memory cell circuit 5,
Exchange control signal generator 6 in which information for memory cell exchange is written in advance in the nonvolatile memory element
It can also be controlled by an exchange control signal output from. That is, in a semiconductor memory having such a configuration, if there is no defective bit in the normal memory cell circuit 4, the exchange control signal will not be output.
Only the regular address decoder 2 operates and the memory cells in the regular memory cell circuit 4 are accessed. On the other hand, if there is a defective bit in the regular memory circuit 4, the spare address decoder 3 is programmed in advance so as to obtain a decode output corresponding to the row or column address including the defective bit, and the replacement control signal is The nonvolatile memory element is programmed so that an exchange control signal of "1" level or "0" level can be obtained from the generating section 6. Therefore, now address buffer 1
When an output corresponding to the row or column address containing the defective bit of the regular memory cell circuit 4 is obtained, the spare address decoder 3 selects a memory cell in the spare memory cell circuit 5. Further, the decoding output of the spare address decoder 3 at this time stops the decoding operation of the regular address decoder 2, and the regular memory cell circuit 4 is not accessed. Through such operations, a defective portion in the regular memory cell circuit 4 is replaced with a spare memory cell circuit 5.

FIGS. 2a and 2b are circuit diagrams showing the conventional configuration of the exchange control signal generating section 6. FIG. The circuit shown in Fig. 2a has a fuse element F made of polysilicon, which is a type of nonvolatile memory element, inserted between the power supply VD application point and the output terminal Out. An enhancement mode MOS transistor Q _E for programming is inserted between the ground point and a depletion mode MOS transistor Q _D is inserted between the output terminal Out and the ground point, and the gate of the MOS transistor Q _E is inserted. At the same time, the program signal P is applied to the MOS transistor.
The gate of Q _D is connected to the ground point.
In addition, the circuit shown in Figure 2b has an enhancement mode MOS transistor Q _E for programming inserted between the power supply VD application point and the output terminal Out, and similarly between the power supply VD application point and the output terminal Out. A depletion mode MOS transistor Q _D is inserted, a fuse element F is inserted between the output terminal and the ground point, a program signal P is applied to the gate of the MOS transistor Q _E , and a program signal P is applied to the gate of the MOS transistor Q _D. The gate is connected to the output terminal Out.

In the circuit of Figure 2a, when fuse element F is not blown, the level of output terminal Out is
It is maintained at the "1" level by the resistance ratio between the MOS transistor Q _D and the fuse element F. on the other hand,
When a “1” level program signal P is applied to the gate of the MOS transistor _QE , this transistor
When _QE is turned on, a large current flows through fuse element F, and fuse element F is blown out by the Joule heat generated at this time. When the fuse element F is blown, the signal P becomes the "0" level again, the transistor _QE is cut off, and the output terminal Out is discharged to the "0" level via the transistor _QD . When the level of the signal at the output terminal Out, that is, the exchange control signal, is, for example, "1" level, the decoding operation of the spare address decoder 3 is stopped, and when it is, for example, "0" level, the decoding operation is performed.

In the circuit of FIG. 2b, contrary to the circuit of FIG. 2a, when the fuse element F is not blown, the level of the output terminal Out depends on the resistance ratio of the MOS transistor Q _D and the fuse element F. It is maintained at the 0" level. When the program signal P at the "1" level is applied to the gate of the transistor _QE , the fuse element F is blown out in the same manner as described above, and then the output terminal Out is charged to the "1" level via the transistor _QD . In this case, when the level of the signal at the output terminal Out, that is, the exchange control signal, is, for example, "0" level, the decoding operation of the spare address decoder 3 is stopped, and when it is, for example, "1" level, the decoding operation is performed. .

FIG. 3 shows an example of the configuration of one decoding circuit of the spare address decoder 3 when the exchange control signal generating section 6 is not used. This circuit uses a depletion mode transistor Q _LD for the load
and a plurality of drive enhancement mode transistors Q _DR and transistors Q _LD , each of which receives address signals A ₀ , ₀ , A ₁ , ₁ . . . output from the address buffer 1 as gate inputs. It is composed of a plurality of fuse elements _FB .

In such a decoding circuit, if one of the memory cells of the regular memory cell circuit 4 corresponding to, for example, address A ₀ =A ₁ =...An=0 is defective, the decoding output corresponding to this address is Each fuse element F _B is programmed so that the fuse element F _B connected to the transistor Q _DR whose gate input _{is 0} , ₁ , . . . is blown. Therefore, when A ₀ =A ₁ =...=An=0, the spare memory cell at that address is accessed.

[Problems with background technology]

By the way, in the conventional exchange control signal generator shown in FIGS. 2a and 2b or the conventional spare decoder shown in FIG. 3, when the fuse element F is not blown, current is always flowing. It's summery. On the other hand, the width of the pattern shape of the fuse element F is made extremely narrow so that it can be easily blown out. For this reason, it is not preferable in terms of reliability to constantly supply current to the fuse element F. For example, if noise is applied to the power supply VD for some reason, or if the power supply voltage is increased by mistake, an abnormal current will flow to the fuse element F, and there is a risk that it will be blown out by mistake. .

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and provides a highly reliable semiconductor integrated circuit that can obtain a desired binary output without constantly flowing current to a nonvolatile memory element (fuse element). The aim is to provide equipment.

[Summary of the invention]

The present invention connects a non-volatile memory element whose impedance changes in a non-volatile manner and a capacitor to the output terminal of a flip-flop, and calculates the ratio of the capacitances connected to the two output terminals of the flip-flop to the non-volatile memory element. By changing the impedance state of the flip-flop, the stable state of the flip-flop can be changed when the power is turned on, thereby eliminating the need for constant current to flow through the nonvolatile memory element and increasing the reliability of the device. It is something.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 4, the output _N1 of the flip-flop _FL1 , which is composed of enhancement mode MOS transistors Q _E1 and Q _E2 and depletion mode MOS transistors Q _D1 and Q _D2 , is connected to a polysilicon film that serves as a nonvolatile memory element. Capacitor C ₁ is connected via fuse F. On the other hand, flipflop FL ₁
Capacitor C ₂ is connected to the other output ₁ of .

If the capacitance relationship in Figure 4 is C ₁ > C ₂ , then
When the current VD is applied, output ₁ is charged faster than N ₁ , so the potential of output ₁ becomes higher than the potential of N ₁ , so transistor Q _E1 turns on, Q _E2
turns off, flip-flop FL ₁ becomes N ₁ = “0”,
N ₁ becomes stable at “1”. At this time, the output N ₁ becomes the above-mentioned exchange control signal, and since N ₁ = "0" at this time, the spare circuit (spare memory cell) is not used. Also, at this time, the polysilicon fuse F is in a low impedance state. However, when using the reserve circuit,
The polysilicon fuse F is fused with, for example, a laser. At this time, the polysilicon fuse F corresponds to a high impedance state. Therefore, the capacitor C ₁ is disconnected from the output N ₁ , and when the power is turned on, the output N ₁ reaches a high potential more quickly than ₁ , so the transistor Q _E2 turns on and Q _E1 turns off, and the output N ₁ =
"1", ₁ = "0", and the output _N1 , which becomes the exchange control signal, puts the backup circuit into an operating state.

As described above, according to this embodiment, no current constantly flows through the polysilicon fuse F. Furthermore, when the polysilicon fuse F is in a low impedance state, the output N ₁ is at the “0” level, so after the power is turned on, current only flows through the polysilicon fuse F for a moment to charge the capacitor C ₁ . .

FIG. 5 shows another embodiment of the present invention, in which a high resistance polysilicon R is used in place of the polysilicon fuse F in FIG. Normally, this R has a high resistance, but it becomes low resistance by laser annealing. The resistance is reduced in this way when the backup circuit is used. In other words, since the capacitance relationship is C ₁ > C ₂ , when the resistance of polysilicon R is reduced, the output N ₁ becomes “0” level and ₁ becomes “1” level, and at this time, ₁ becomes the exchange control signal. Become. In this case as well, the same signals as in the case of FIG. 4 can be supplied.

FIG. 6 shows a specific example in which the present invention is applied to a preliminary decoder. Flip-flop FL ₂ , which is composed of enhancement mode MOS transistors Q' _E1 , Q' _E2 and depletion mode MOS transistors Q _D1 , Q _D2 , connects polysilicon fuses F ₁ and F ₂ to its outputs N ₂ and _2, respectively. A capacitor _C3 is connected through the capacitor C3. Then, depending on the defective address, either polysilicon fuse F ₁ or F ₂ is cut. Enhancement mode MOS transistors Q _E3 , Q _E4 are connected to the outputs N ₂ and ₂ of flip-flop FL ₂ .
are connected, and signal ₁ is input to the gates of these transistors. An enhancement mode MOS transistor Q E5 is inserted between the address signal Ax supply end and the signal A′x supply end, and an enhancement mode MOS transistor Q _E5 is inserted between the address signal supply end and the signal A′x supply end. Q _E6 is inserted. The gate of the transistor Q _E5 is connected to the output ₂ of the flip-flop FL ₂ , and the gate of the transistor Q _E6 is connected to the output N ₂ . The spare decoder consists of enhancement mode MOS transistors Q _EX , Q _EX1 , Q _EX2 ,...Q _E7 , Q _E8 and depletion mode MOS transistor Q _D3 .
The gates of the transistors Q _EX , Q _EX1 , Q _EX2 , ...Q _E7 , Q _E8 are supplied with signals A′x, A′x ₁ , A′x ₂ , ... ₁ , N ₁ and the output of this preliminary decoder The end is connected to the spare memory cell via the buffer Bu.

In FIG. 6, address signal Ax="0", =
If there is a defective memory cell at address "1", polysilicon fuse _F2 is cut. Therefore, in flip-flop FL ₂ , the capacitance of output ₂ is larger than ₂ , and therefore when the power supply VD is turned on,
N ₂ = “0”, ₂ = “1”, transistor Q _E5
turns on, Q _E6 turns off, address signal Ax becomes A′x via transistor Q _E5 , and transistor Q _Ex
is transmitted to the gate. Similarly transistor
Signals A'x ₁ , A'x ₂ , ... from other address inputs are input to the gates of Q _EX1 , Q _EX2 , .... These signals are output when either fuse F ₁ or F ₂ is disconnected depending on the defective address in a structure similar to that of the flip-flop system shown in FIG. And all of the signals A′x, A′x ₁ , A′x ₂ , … are “0”
When the level is reached, the spare memory will be selected. On the other hand, when the spare memory cell is not used, the signals N ₁ = "0", ₁ = "1" level turn on transistors Q _E3 , Q _E4 , Q _E7 and turn off Q _E8 , and the spare memory cell also outputs. Since the signal is at the "0" level, it will never be selected.

Note that the present invention is not limited to the examples only,
Various applications are possible. For example, as shown in FIG. 7, the present invention is particularly effective when applied to a CMOS circuit. Because as shown in the diagram, P
When using a flip-flop circuit using channel type transistors Q _P11 , Q _P12 , and N channel type transistors Q _N11 , Q _N12 , not only does a current not constantly flow through the nonvolatile memory element F, but also the exchange control signal shown in FIG. This is because the current flowing through the generation circuit itself also becomes zero.

〔Effect of the invention〕

As explained above, according to the present invention, since current does not constantly flow through the nonvolatile memory element,
It is possible to provide a highly reliable semiconductor integrated circuit device in which data is not erroneously written due to power supply noise or the like.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a semiconductor memory in which a spare memory cell circuit is formed, FIGS. 2 and 3 are partial detailed circuit diagrams of the same configuration, and FIGS. 4 and 5 are each embodiment of the present invention. FIG. 6 is a circuit diagram when the present invention is applied to a preliminary decoder, and FIG. 7 is a circuit diagram of another embodiment of the present invention. FL ₁ ... flip-flop circuit, C ₁ , C ₂ ... capacitance,
N ₁ , ₁ ...output end, F...polysilicon fuse,
R...High resistance polysilicon.

Claims (1)

[Claims] 1. A flip-flop circuit, a capacitor connected to a first output terminal of the flip-flop circuit, a capacitor connected to a second output terminal of the flip-flop circuit, and a capacitor connected in series to this capacitor. means for changing the capacitance ratio between the first and second output terminals according to the data stored in the non-volatile storage element,
A semiconductor integrated circuit device characterized in that a steady current does not flow through the nonvolatile memory element and a capacitor connected in series with the element. 2. The semiconductor integrated circuit device according to claim 1, wherein the flip-flop circuit determines whether or not to use a spare memory cell area depending on its output state. 3. A flip-flop circuit, a capacitor connected to a first output terminal of the flip-flop circuit, a capacitor connected to a second output terminal of the flip-flop circuit, and a non-volatile memory element connected in series to each of the capacitors. means for changing the capacitance ratio between the first and second output terminals according to the stored data, so that no steady current flows through the nonvolatile memory element and the capacitance connected in series with the element. A semiconductor integrated circuit device characterized by: 4. The semiconductor integrated circuit device according to claim 3, wherein the flip-flop circuit determines whether or not to use a spare memory cell area depending on its output state.