JPH0437941A - Data transfer method - Google Patents

Abstract

PURPOSE:To improve the availability of a bus by grasping the data store states of all buffers, by continuing an occupied state of the bus when the transfer is possible for the data on another buffer when the transfer of data is through with a certain buffer and then transferring the data on the relevant buffer. CONSTITUTION:When the data on an input/output device 55A are transferred, to memory 53 a bus is occupied for transfer of data until the end of the transfer of data on a buffer 561, for example, with occupation of the bus granted every time the transfer of data is possible for those buffers 561-56n. Then the occupation of the bus is continued as long as another transferable buffer 562, for example, is available when the transfer of data is through with the buffer 561 after the data store states of all buffers 561-56n are grasped and the bus is once occupied. Thus the data on the buffer 562 are continuously transferred. As a result, the decision of the bus occupation is not needed as long as the data can be continuously transferred. Then the availability of the bus is improved.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a data transfer method for controlling competition between bus occupation requests of input/output devices when transferring data from the input/output devices to memory in an information processing device having a plurality of input/output devices. , with the aim of improving bus usage efficiency, has multiple buffers that temporarily store data to be transferred, and sends a bus occupancy request to each buffer when data can be transferred, and requests bus occupancy permission. In a data transfer method that occupies a bus and transfers the data in the corresponding buffer according to the transfer, and releases the bus when the transfer is completed, the data storage status of all buffers is grasped, and when the data transfer of one buffer is completed, When data in another buffer can be transferred, the bus continues to be occupied and the data in that buffer is transferred.

[Field of Industrial Application] The present invention relates to a data transfer method for controlling competition between bus occupancy requests of input/output devices when transferring data from the input/output devices to a memory in an information processing device having a plurality of input/output devices. .

[Conventional technology]

FIG. 5 is a configuration block diagram of an information processing device including a plurality of input/output devices.

In the figure, a central processing unit (CPU) 51, a memory 53
and multiple input/output devices (IOA, 10B) 55A, 5
5B is connected via a bus 57. Each input/output device 5
5A and 55B are a plurality of buffers 56.5A and 55B for temporarily storing input/output data. It is a configuration having an angle of ˜561°.

The arbiter 59 receives bus occupancy request signals (here, transfer request signals RQA, RQB, R
QC), adjusts the competition based on a predetermined priority, and sends a permission signal ACK indicating that the request has been accepted to one of the transfer request sources.

Hereinafter, with reference to the flowchart shown in FIG. 6 and the timing chart shown in FIG. 7, the input/output device (IOA) 5
A DMA data transfer processing procedure between 5A and memory 53 will be explained.

The input/output device (IOA) 55A has each buffer 56, ~5
Each buffer has a status signal FULLi (i is 1 to n) that is set when data is clogged corresponding to 6ゎ, and corresponds to buffer 56゜ when even one of the buffers is clogged with data. Status signal FULL 1
The transfer request signal RQA is sent to the arbiter 59 according to the set of
Send out.

The arbiter 59 receives a transfer request signal RQA from an input/output device (IOA) 55A, and transfers it to another input/output device (IOB).
) 55B or the transfer request signals RQB and RQC from the central processing unit (CPU) 51. After this bus occupancy determination time T, the input/output device (IOA)
) A permission signal A indicating that the transfer request has been accepted to 55A.
Send CK.

The input/output device (IOA) 55A receives this permission signal ACK, sets a bus occupancy signal BGACK indicating that it occupies the bus 57 for data transfer, and transfers the memory 53.
buffer 56. Start transferring the data contained in the .

The input/output device (IOA) 55A outputs a bus occupancy signal BGACK in response to a transfer end signal EOP accompanying the end of data transfer.
and buffer 56. Reset the state signal FULLI corresponding to . Note that the input/output device (IOA) 55A does not know the data storage status of other buffers, so even if the other buffer (here, the buffer 56□) is full of data and ready for transfer, the transfer will not be completed. Signal EOP
The bus occupancy signal BGACK is reset in response to this. On the other hand, the transfer request signal RQA of the input/output device (IOA) 55A
will not be reset as long as the status signals FULLi of other buffers are in the cent state.

In response to the transfer request signal RQA that is continuously sent from the input/output device (IOA) 55A, the arbiter 59 sends a permission signal ACK to the input/output device (IOA) indicating that the transfer request signal RQA has been accepted. ) 55A, and the data in the buffer 56□ is transferred to the memory 53 in the same manner.

In this way, each input/output device sends a transfer request signal to the arbiter 59 in response to the status signal FULL i of each buffer, and receives the permission signal A notified from the arbiter 59.
CK, the bus occupancy signal BGACK is set, and the buffer 56. data is being transferred. Further, the bus occupancy signal BGACK is reset by the transfer end signal EOP corresponding to the end of the data transfer, and the bus is released.

Here, the relationship among the buffer status signal FULLi, the bus occupancy signal BGACK, and the transfer end signal EOP can be schematically expressed by the OR circuit 81, the AND circuit 83, and the JK flip-flop 85 shown in FIG.

[Problems to be Solved by the Invention] As described above, in the conventional data transfer method, each time the data in the fixed-length buffer is transferred, the bus occupancy signal B (1, ACK is reset and the bus is Because it is open, it is necessary to process the transfer request signal again.In other words, the arbiter, which performs contention control in response to the transfer request signal, controls data transfer on a buffer-by-buffer basis each time.

Incidentally, while the arbiter was processing the transfer request signal, the bus could not be used. In other words, the bus is occupied and released each time data from a fixed-length buffer is transferred, regardless of whether data from other buffers can be transferred in succession. The number of determinations was increasing, and the efficiency of bus usage was decreasing.

The present invention solves these problems, and aims to provide a data transfer method that can improve bus usage efficiency.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the data transfer method has multiple buffers that temporarily store the data to be transferred, sends a bus occupancy request for each buffer when data can be transferred, and occupies the bus according to bus occupancy permission. The data in the corresponding buffer is transferred, and the bus is released when the transfer is completed.

In the present invention, the data storage state of all buffers is grasped, and when data transfer of one buffer is completed and data of another buffer can be transferred, the bus is continued to be occupied and the data of that buffer is transferred.

[For production]

The data transfer method includes multiple buffers and requests bus occupancy each time data in each buffer becomes available for transfer.
When bus occupancy permission is received, data is transferred by occupying the bus until data transfer for that buffer is completed.

In the present invention, the data storage status of all buffers is grasped, and -
Once the bus is occupied, the bus continues to be occupied as long as there is another buffer that can be transferred at the end of the data transfer of one buffer, and the data of that buffer is continuously transferred.

In other words, since the bus is not released until all data in the buffer that can be transferred while the bus is occupied is transferred, bus occupancy determination is not required while continuous data transfer is possible, improving bus usage efficiency. I can do it.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a flowchart of data transfer processing according to the embodiment. Further, FIG. 3 is a timing chart of data transfer processing in the embodiment.

The operation of the embodiment when data of the input/output device 55A is transferred to the memory will be described below with reference to FIGS. 2, 3, and 5.

Note that the buffer 56. of the input/output device 55A. The procedure from when the status signal FULLI corresponding to is set until the data transfer of the buffer 561 is completed is the same as the procedure described in the related art.

According to the embodiment of the present invention, the status signal FULLI corresponding to the buffer 561 is reset in response to the transfer end signal EOP output when the data transfer of the buffer 561 is completed, but the bus occupancy signal BGACK is While the state signal FULL i of 562 is set, here, it is not reset while the state signal FULL2 corresponding to the buffer 562 is set. Therefore, the input/output device 55A continues to occupy the bus and continues to use the buffer 55A.
! data can be transferred.

When the transfer of data in the buffer 56□ is completed, the buffer 56. Since the state signal FULL2 corresponding to the buffer 56 is reset and the state signal FULLi corresponding to all the buffers 56 is reset, the bus occupancy signal BGACK is reset and the bus is released.

In this way, each input/output device receives the transfer request signal once and sets the bus occupancy signal BGACK, and then transfers the data in all the buffers that become clogged with data while the bus is occupied and become transferable. The bus will not be released until
Repeat data transfer for each buffer in sequence.

The relationship between the buffer status signal FULLi and the bus occupancy signal BGACK can be schematically expressed by adding an inverter circuit 61 to the conventional configuration shown in FIG. 8, as shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, even if the transfer of data in one buffer ends, as long as there is another buffer full of data at the time of the end of transfer, the bus continues to be occupied and continuous data is transferred. enable transfer.

Therefore, since bus occupancy is not always determined for each buffer, the number of bus occupancy determinations is reduced, and the number of unused bus states associated with bus occupancy determination is reduced, making it possible to improve bus usage efficiency. becomes.

[Brief explanation of drawings]

Fig. 1 is a principle block diagram of the present invention, Fig. 2 is a flowchart of data transfer processing in the embodiment, Fig. 3 is a timing chart of data transfer processing in the embodiment, and Fig. 4 is a status signal and bus occupancy in the embodiment. FIG. 5 is a block diagram of the configuration of the information processing device, FIG. 6 is a flowchart of conventional data transfer processing, and FIG. 7 is a diagram of conventional data transfer processing. Timing Chart FIG. 8 is a diagram schematically explaining the relationship among a conventional status signal, bus occupancy signal, and transfer end signal. In the figure, 51 is a central processing unit, 53 is a memory, 55 is an input/output device, 56 is a buffer, 57 is a bus, 59 is an arbiter, 61 is an inverter circuit, 81 is an OR circuit, 83 is an AND circuit, and 85 is an AND circuit. It's a JK flip-flop. ↓ Principle block diagram of the present invention Fig. 1 Flowchart of data transfer processing in the embodiment Fig. 2 Fig. Timing chart of data transfer processing in the embodiment Fig. 3 Timing chart of conventional data transfer processing Part 7 V Information Configuration block diagram of processing device

Claims (1)

[Claims] (1) It has multiple buffers that temporarily store data to be transferred, sends a bus occupancy request for each buffer when data can be transferred, and occupies the bus in response to bus occupancy permission. In a data transfer method that transfers data in a buffer and releases the bus upon completion of the transfer, the data storage status of all buffers is grasped, and when data transfer in one buffer is completed, data in other buffers can be transferred. In such a case, the data transfer method continues to occupy the bus and transfer the data in the buffer.