JPH04372130A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04372130A
JPH04372130A JP17715491A JP17715491A JPH04372130A JP H04372130 A JPH04372130 A JP H04372130A JP 17715491 A JP17715491 A JP 17715491A JP 17715491 A JP17715491 A JP 17715491A JP H04372130 A JPH04372130 A JP H04372130A
Authority
JP
Japan
Prior art keywords
insulating film
photoresist layer
semiconductor device
cut
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17715491A
Other languages
Japanese (ja)
Inventor
Takehiko Nomura
剛彦 野村
Masayuki Iwase
正幸 岩瀬
Yoshio Nakamura
中村 芳雄
Toshio Kikuta
俊夫 菊田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Furukawa Electric Co Ltd
Original Assignee
Furukawa Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Furukawa Electric Co Ltd filed Critical Furukawa Electric Co Ltd
Priority to JP17715491A priority Critical patent/JPH04372130A/en
Publication of JPH04372130A publication Critical patent/JPH04372130A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Weting (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE:To manufacture a semiconductor device by forming a pattern consisting of submicron-order air gaps in an insulating film by a normal optical exposure method. CONSTITUTION:A semiconductor substrate is spread with an insulating film 23, and a photoresist layer 24 with a desired pattern is deposited over the insulating film 23; then, the photoresist layer 24 is used as a mask for etching the insulating film 23 so as to bite into the bottom of the photoresist layer 24 to form a bite-in 29. Another insulating film 25 is piled up, the insulating film 25 on the photoresist layer 24 and the photoresist layer 24 are lifted off.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、電子デバイスのゲート
電極などサブミクロンパターンを有する半導体装置の製
造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device having a submicron pattern such as a gate electrode of an electronic device.

【0002】0002

【従来技術】GaAsを用いたMESFETは、Siバ
イポーラトランジスタに比べて高速性を有し、個別のマ
イクロ波用FETとして実用化されている。また、最近
では、MBEやMOCVD法などの薄膜エピタキシャル
成長技術の進展により、選択ドープヘテロ接合を用いた
HEMTがより高速性に優れた素子として開発されてい
る。これらの電子デバイスをより高周波で動作させるた
めには、ゲート長を短くして、相互コンダクタンスを大
きくし、ゲート下の寄生容量を小さくすることが必要で
ある。また、ゲート長を短くすると、雑音性能を向上さ
せることができる。そのため、通常、ゲート長は0.5
〜1μmのサブミクロンオーダとなっている。上述のよ
うな短いゲートは、例えば、図2(a)〜(c)に示す
ような方法で形成されていた。即ち、 1)先ず、半導体基板10上にフォトレジスト層11を
塗布し、サブミクロン幅の開口部13を形成する(図2
(a))。 2)次に、ゲート金属12を全面に蒸着する(図2(b
))。 3)次に、アセトンによってフォトレジスト層11上の
ゲート金属12およびフォトレジスト層11をリフトオ
フし、サブミクロン幅のゲート電極14を形成する(図
2(c))。
2. Description of the Related Art MESFETs using GaAs have higher speeds than Si bipolar transistors, and have been put to practical use as individual microwave FETs. Furthermore, with the recent progress in thin film epitaxial growth techniques such as MBE and MOCVD, HEMTs using selectively doped heterojunctions have been developed as devices with higher speed performance. In order to operate these electronic devices at higher frequencies, it is necessary to shorten the gate length, increase mutual conductance, and reduce parasitic capacitance under the gate. Additionally, reducing the gate length can improve noise performance. Therefore, the gate length is usually 0.5
It is on the submicron order of ~1 μm. The short gates described above have been formed, for example, by the methods shown in FIGS. 2(a) to 2(c). That is, 1) First, a photoresist layer 11 is applied on the semiconductor substrate 10, and an opening 13 with a submicron width is formed (FIG. 2).
(a)). 2) Next, gate metal 12 is deposited on the entire surface (see FIG. 2(b)
)). 3) Next, the gate metal 12 and the photoresist layer 11 on the photoresist layer 11 are lifted off using acetone to form a gate electrode 14 with a submicron width (FIG. 2(c)).

【0003】0003

【発明が解決しようとする課題】しかしながら、通常の
光学露光法では1μm程度の分解能が限界であり、サブ
ミクロンのレジスト開口部を得るためには、縮小投影露
光方式、または、電子ビーム露光装置のような非常に高
額な装置を用いる必要がある。また、電子ビーム露光装
置はスループットが低く、生産性に問題がある。
[Problems to be Solved by the Invention] However, the resolution of ordinary optical exposure methods is limited to about 1 μm, and in order to obtain submicron resist openings, reduction projection exposure methods or electron beam exposure systems are required. It is necessary to use very expensive equipment such as Furthermore, electron beam exposure apparatuses have low throughput and have problems with productivity.

【0004】0004

【課題を解決するための手段】本発明は上記問題点を解
決した半導体装置の製造方法を提供するもので、半導体
基板上に絶縁膜を形成し、次いで、該絶縁膜上に所望の
パターンを有するフォトレジスト層を形成し、次いで、
該フォトレジスト層をマスクとして前記絶縁膜を前記フ
ォトレジスト層の下側に食い入るようにエッチングして
食い入り部を形成し、次いで、再び絶縁膜を積層し、次
いで、前記フォトレジスト層上の絶縁膜およびフォトレ
ジスト層をリフトオフし、前記食い入り部からなる所望
の空隙パターンを絶縁膜に形成する工程を含むことを特
徴とするものである。
[Means for Solving the Problems] The present invention provides a method for manufacturing a semiconductor device that solves the above problems, and includes forming an insulating film on a semiconductor substrate, and then forming a desired pattern on the insulating film. forming a photoresist layer with
Using the photoresist layer as a mask, the insulating film is etched to cut into the underside of the photoresist layer to form a cut-in part, then an insulating film is laminated again, and then the insulating film on the photoresist layer is etched. and a step of lifting off the photoresist layer to form a desired void pattern made of the cut-in portions in the insulating film.

【0005】[0005]

【作用】上述のように、絶縁膜上に形成されたフォトレ
ジスト層をマスクとして、絶縁膜をエッチングすると、
等方的にエッチングが行われるため、エッチング時間を
長くすると、絶縁膜はフォトレジスト層端部の下側まで
アンダーカット状にエッチングされる。次いで、再び絶
縁膜を積層すると、この絶縁膜と最初に形成された絶縁
膜との間にアンダーカットされた分だけの絶縁膜の空隙
部分が生ずる。次いで、前記フォトレジスト層をリフト
オフすると、絶縁膜の上記空隙部分を回路パターンの開
口部として利用できる。この空隙部分の幅はアンダーカ
ットの量できまるため、エッチング時間を制御すること
により、サブミクロンオーダの所望の空隙幅を得ること
ができる。
[Operation] As mentioned above, when the insulating film is etched using the photoresist layer formed on the insulating film as a mask,
Since etching is performed isotropically, if the etching time is increased, the insulating film is etched to the bottom of the end of the photoresist layer in an undercut shape. Then, when the insulating film is laminated again, a gap portion corresponding to the undercut is created between this insulating film and the first insulating film. Next, when the photoresist layer is lifted off, the void portion of the insulating film can be used as an opening for a circuit pattern. Since the width of this gap portion is determined by the amount of undercut, a desired gap width on the order of submicrons can be obtained by controlling the etching time.

【0006】[0006]

【実施例】以下、図面に示した実施例に基づいて本発明
を詳細に説明する。図1(a)〜(g)は本発明に係る
半導体装置の製造方法の一実施例の工程説明図であり、
以下のようにしてGaAs・MESFETのゲート電極
を形成した。即ち、 1)半絶縁性GaAs基板(図示されず)上に、エピタ
キシャル成長法またはイオン注入法によってn型半導体
層20を形成し、その上に、AuGe/Auなどの金属
でオーミック接触をするソース電極21、ドレイン電極
22を形成する(図1(a))。 2)次いで、ソース電極21、ドレイン電極22及び半
導体層20上に、SiO2 またはSiNX の絶縁膜
23を熱CVD法によって2000Åの厚さに形成し、
その上に、ソース電極21とドレイン電極22の間に端
面が来るようにフォトレジスト層24を形成する(図1
(b))。 3)次いで、フォトレジスト層24をマスクにして、バ
ッファードフッ酸で絶縁膜23を40秒エッチングする
。絶縁膜23は等方的にエッチングされるため、エッチ
ング時間を長めにすることにより、絶縁膜23をフォト
レジスト層24の下側に食い入るようにエッチングして
食い入り部29を形成する(図1(c))。 4)次いで、絶縁膜25を全面に積層する。この状態で
は、食い入り部29には絶縁膜25は形成されない(図
1(d))。 5)次いで、フォトレジスト層24上の絶縁膜25をリ
フトオフする。そうすると、食い入り部29だけの幅0
.5μmの空隙28が生ずる(図1(e))。 6)次いで、フォトレジスト層26を形成し、ゲート電
極の形状を規定する(図1(e))。 7)次いで、半導体層20とショットキー接合を形成す
るAuなどの金属層を全面に蒸着し、不要なゲート金属
をリフトオフし、サブミクロンオーダーのゲート電極2
7を形成する(図1(e))。以上、GaAs・MES
FETを例にとって説明したが、半導体材料はGaAs
に限るものではなく、他の3−5族化合物半導体もしく
はSiでもよい。また、上記の説明では絶縁膜23のエ
ッチングはバッファードフッ酸によるものとしたが、エ
ッチングが等方的に進むのならば、ドライエッチングを
用いてもよく、例えば、高圧CF4 によるRIFを用
いてもよい。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained in detail below based on embodiments shown in the drawings. FIGS. 1(a) to 1(g) are process explanatory diagrams of an embodiment of the method for manufacturing a semiconductor device according to the present invention,
A gate electrode of a GaAs MESFET was formed in the following manner. That is, 1) An n-type semiconductor layer 20 is formed on a semi-insulating GaAs substrate (not shown) by epitaxial growth or ion implantation, and a source electrode is formed thereon to make ohmic contact with a metal such as AuGe/Au. 21, a drain electrode 22 is formed (FIG. 1(a)). 2) Next, an insulating film 23 of SiO2 or SiNX is formed to a thickness of 2000 Å on the source electrode 21, drain electrode 22 and semiconductor layer 20 by thermal CVD method,
A photoresist layer 24 is formed thereon so that the end surface is between the source electrode 21 and the drain electrode 22 (see FIG.
(b)). 3) Next, using the photoresist layer 24 as a mask, the insulating film 23 is etched with buffered hydrofluoric acid for 40 seconds. Since the insulating film 23 is etched isotropically, by making the etching time longer, the insulating film 23 is etched so as to dig into the underside of the photoresist layer 24, thereby forming a digging part 29 (see FIG. 1). c)). 4) Next, an insulating film 25 is laminated over the entire surface. In this state, the insulating film 25 is not formed in the cut-in portion 29 (FIG. 1(d)). 5) Next, the insulating film 25 on the photoresist layer 24 is lifted off. Then, the width of only the cut-in part 29 is 0.
.. A gap 28 of 5 μm is created (FIG. 1(e)). 6) Next, a photoresist layer 26 is formed to define the shape of the gate electrode (FIG. 1(e)). 7) Next, a metal layer such as Au that forms a Schottky junction with the semiconductor layer 20 is deposited on the entire surface, unnecessary gate metal is lifted off, and a submicron-order gate electrode 2 is formed.
7 (Fig. 1(e)). Above, GaAs・MES
The explanation was given using FET as an example, but the semiconductor material is GaAs.
The material is not limited to, and other Group 3-5 compound semiconductors or Si may be used. Furthermore, in the above explanation, the etching of the insulating film 23 was performed using buffered hydrofluoric acid, but if the etching progresses isotropically, dry etching may be used. Good too.

【0007】[0007]

【発明の効果】以上説明したように本発明によれば、半
導体基板上に絶縁膜を形成し、次いで、該絶縁膜上に所
望のパターンを有するフォトレジスト層を形成し、次い
で、該フォトレジスト層をマスクとして前記絶縁膜を前
記フォトレジスト層の下側に食い入るようにエッチング
して食い入り部を形成し、次いで、再び絶縁膜を積層し
、次いで、前記フォトレジスト層上の絶縁膜およびフォ
トレジスト層をリフトオフし、前記食い入り部からなる
所望の空隙パターンを絶縁膜に形成するため、縮小投影
露光装置や電子ビーム露光装置などの高価な装置を用い
ることなく、従来の光学露光法でサブミクロンオーダー
のパターンを形成することができるという優れた効果が
ある。従って、サブミクロンのゲート電極や、T字型の
ゲート電極を形成し、ゲート抵抗の小さい電子デバイス
を容易に得ることができる。
As explained above, according to the present invention, an insulating film is formed on a semiconductor substrate, a photoresist layer having a desired pattern is formed on the insulating film, and then the photoresist layer is Using the layer as a mask, the insulating film is etched to cut into the underside of the photoresist layer to form a cut-in part, and then the insulating film is laminated again, and then the insulating film and the photoresist on the photoresist layer are etched. In order to lift off the layer and form a desired void pattern consisting of the cut-in portions in the insulating film, the submicron order can be formed using conventional optical exposure methods without using expensive equipment such as reduction projection exposure equipment or electron beam exposure equipment. It has the excellent effect of being able to form a pattern. Therefore, a submicron gate electrode or a T-shaped gate electrode can be formed, and an electronic device with low gate resistance can be easily obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】(a)〜(g)は本発明に係る半導体装置の製
造方法の一実施例の工程説明図である。
FIGS. 1A to 1G are process explanatory diagrams of an embodiment of a method for manufacturing a semiconductor device according to the present invention.

【図2】(a)〜(c)は従来のゲート電極を形成する
工程説明図である。
FIGS. 2(a) to 2(c) are explanatory diagrams of steps for forming a conventional gate electrode.

【符号の説明】[Explanation of symbols]

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  半導体基板上に絶縁膜を形成し、次い
で、該絶縁膜上に所望のパターンを有するフォトレジス
ト層を形成し、次いで、該フォトレジスト層をマスクと
して前記絶縁膜を前記フォトレジスト層の下側に食い入
るようにエッチングして食い入り部を形成し、次いで、
再び絶縁膜を積層し、次いで、前記フォトレジスト層上
の絶縁膜およびフォトレジスト層をリフトオフし、前記
食い入り部からなる所望の空隙パターンを絶縁膜に形成
する工程を含むことを特徴とする半導体装置の製造方法
1. An insulating film is formed on a semiconductor substrate, and then a photoresist layer having a desired pattern is formed on the insulating film, and then, using the photoresist layer as a mask, the insulating film is bonded to the photoresist. Etch to cut into the underside of the layer to form a cut-in portion, and then
A semiconductor device comprising the steps of laminating an insulating film again, then lifting off the insulating film on the photoresist layer and the photoresist layer, and forming a desired void pattern made of the cut-in portions in the insulating film. manufacturing method.
JP17715491A 1991-06-20 1991-06-20 Manufacture of semiconductor device Pending JPH04372130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17715491A JPH04372130A (en) 1991-06-20 1991-06-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17715491A JPH04372130A (en) 1991-06-20 1991-06-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04372130A true JPH04372130A (en) 1992-12-25

Family

ID=16026136

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17715491A Pending JPH04372130A (en) 1991-06-20 1991-06-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04372130A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100251106B1 (en) * 1996-12-11 2000-05-01 전주범 Method for fabricating thin film type light-path controlling device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100251106B1 (en) * 1996-12-11 2000-05-01 전주범 Method for fabricating thin film type light-path controlling device

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