JPH04370582A - Digital signal recording and reproducing device - Google Patents

Abstract

PURPOSE:To suppress deterioration in reproduced picture quality by dividing an information recording block into two blocks for MSB, LSB and adding error correction codes to plural different directions after mixing again by adding the error correction code to only the side of MSB block. CONSTITUTION:Data of an input signal 1 are bi-sected 4 to high-order and low-order columns, then the error correction code in at least one direction is added 44 to the MSB block constituted with the high-order bit column and recorded. For reproduced data 33, an error generated in the reproduced data is corrected and detected 50 at the reproducing time by the error correction code 48 which is added to the different plural directions, and after that, the data are bi-sected 52 to the MSB block and LSB block, then an error generated in the MSB block is corrected and detected for the MSB block by the error correction code 53, and the data to which the MSB block and LSB block are corresponded, are again combined 30 respectively, then an original digital signal is obtained by correcting the data.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a video tape recorder (digital recording and playback of video and audio signals).
The present invention relates to digital signal recording and reproducing devices such as VTRs (hereinafter referred to as VTRs), video disc players, and audio tape recorders, and particularly relates to the code structure of recorded signals.

0002

[Background Art] In a digital signal recording and reproducing device that digitally records video signals, audio signals, etc., an information symbol block to be recorded is divided into a plurality of blocks starting from the upper bit (MSB bit), and each block has a different error correction capability. There is a method of recording by adding an error correction code with . In this method, as mentioned above, the ability of the error correction code added to the information data of each block is biased, and if an error occurs, the block of upper bits (hereinafter referred to as MSB) causes significant deterioration of the original signal. (called a block) has
The lower bit block (hereinafter referred to as LSB) has a large error correction ability and does not cause much deterioration even if an error occurs.
(referred to as a block) is configured to have a small error correction capability. At this time, for example, if the recording signal is a video signal,
Since a large error correction code is added to the data on the MSB side, which significantly deteriorates the quality of the reproduced image due to errors that occur during reproduction, it is possible to suppress the deterioration of the reproduced image due to errors as much as possible and obtain a good reproduced image.

FIG. 5 shows a conventional digital VTR that records data with error correction codes added according to the importance of the data.
FIG. 2 is a block diagram showing the configuration of FIG. The configuration of FIG. 5 will be explained. Note that in this embodiment, 1
It is assumed that a composite signal of channels is handled. Figure 5
, 1 is a signal input terminal, 2 is an A/D conversion circuit that converts an analog signal into digital data, 3 is a recording signal processing circuit I that performs a first shuffling process etc. on the input digital data, and 4 is a After performing shuffling processing of 1, etc., the data dividing circuit I divides the digital data into an upper bit string and a lower bit string to form an MSB block and an LSB block. 5 is an error correction code circuit I that adds an error correction code C2' parity to the MSB block; 6 is an error correction code circuit II that adds an error correction code C2'' parity to the LSB block; 7 is an error correction code circuit I MSB from code circuit I 5
Recording signal processing circuits II and 8 which perform second shuffling processing etc. on blocks receive the LSB from the error correction code circuit II6.
This is a recording signal processing circuit III that performs second shuffling processing and the like on blocks. 9 is an error correction code circuit III that adds an error correction code C1' parity to the MSB block that has been subjected to the second shuffling process, and 10 is an error correction code circuit that adds an error correction code to the LSB block that has been subjected to the second shuffling process, etc. C1" is an error correction code circuit IV that adds parity. 11 is an MI that adds an ID signal, a synchronization signal, etc. after mixing the MSB block and LSB block.
This is the X circuit I. 12 is a digital modulation circuit that digitally modulates digital data to which an error correction code, an ID signal, and a synchronization signal are added; 13 is a recording amplifier that amplifies the digitally modulated recording signal; 14 is a recording head for recording the recording signal; 15 is a magnetic It's a tape.

Reference numeral 16 denotes a reproduction head for reading out the recording signal 14 recorded on the magnetic tape 15, 17 a head amplifier for amplifying the read reproduction signal, 18 a reproduction equalizer circuit for compensating the frequency characteristics of the reproduction signal, 19 is a data detection circuit that converts the reproduced signal into a reproduced digital signal;
20 is a PLL circuit that generates a clock synchronized with the reproduced digital signal. 21 is a digital demodulation circuit that demodulates the reproduced digital signal into reproduced digital data;
2 is an ID/synchronization separation circuit that separates an ID signal and a synchronization signal from reproduced digital data. 23 is a data division circuit II, 2 that separates the MSB block and LSB block.
4 is an error correction decoding circuit I that corrects and detects an error occurring in the MSB block using C1' parity, and 25 is an error correction decoding circuit II that corrects and detects an error occurring in the LSB block using C1'' parity. 26 is a reproduction signal processing circuit I that performs first deshuffling processing etc. on the MSB block.
, 27 is a reproduction signal processing circuit II that performs first deshuffling processing and the like on the LSB block. 28 is an error correction decoding circuit III that corrects and detects errors occurring in the MSB block with C2' parity, and 29 is LS with C2'' parity.
This is an error correction decoding circuit IV that corrects and detects errors occurring in the B block. 30 is a MIX circuit II, 3 which mixes the divided MSB block and LSB block.
Reference numeral 1 denotes a reproduction signal processing circuit III which performs second deshuffling processing and the like and adds a synchronization signal and the like. 32
3 is a D/A conversion circuit that converts digital data into an analog signal, and 33 is a signal output terminal.

FIG. 6 is a diagram showing the configuration of a conventional data division circuit. In the figure, 60 is an input terminal for inputting 8-bit digital data, and 61 is an S/P conversion circuit for converting input 8-bit serial digital data into 16-bit parallel digital data. 62a,
62b is a latch circuit that latches 8-bit MSB data and LSB data, respectively. 63a and 63b are output terminals that output MSB data and LSB data, respectively.

Next, the operation of FIG. 5 will be explained. The input signal is converted into digital data by the A/D conversion circuit 2, and then subjected to shuffling processing and the like by the recording signal processing circuit I3. Then, the data division circuit I4 divides the digital data into an upper bit string and a lower bit string, forming an MSB block and an LSB block.

In the data division circuit I4, the input 8-bit serial digital data (this digital signal is referred to as an8) is divided into 16 bits by the S/P conversion circuit 61.
Convert to bit parallel digital data. S/P
The conversion circuit 61 converts the output data into anh4 data (an
8 data MSB side 4 bits), anl4 data (a
4 bits on the LSB side of n8 data), a(n+1)h4
Data (MSB side 4 bits of a(n+1)8 data),
a(n+1)l4 data(a(n+1)8 L of data
4 bits on the SB side) are output as four data. These four signals are (anh4, a(n+1)h4), (an
l4, a(n+1)l4) and input them to the latch circuits 62a and 62b, and the 8-bit anh8 data that is a component of the MSB block and the 8-bit anl8 data that is a component of the LSB block are input to the latch circuits 62a and 62b. Configure.

The error correction code circuit I5 adds an error correction code C2' parity to the data of the MSB block, and the error correction circuit II6 adds an error correction code C2'' parity to the LSB block. Recording signal processing Circuit I
The recording signal processing circuit I7 performs shuffling processing, etc. within the MSB block, and the recording signal processing circuit III8 performs shuffling processing, etc. within the LSB block. Error correction code circuit III 9
adds error correction code C1' parity to the MSB block, and error correction code circuit IV10 adds error correction code C1'' parity to the LSB block.

FIGS. 7A and 7B are diagrams showing the structure of a conventional Reed-Solomon product code. In the same figure (a), the MSB
This is a block configuration diagram, in which the number of information data in the C1' direction is 85, and the number of error correction code data is 12 (dmin=13:
dmin=minimum Hamming distance). Also, the number of information data in the C2' direction is 64, and the number of error correction code data is 4 (d
min=5). Figure (b) is a configuration diagram of the LSB block, where the number of information data in the C1'' direction is 85, and the number of error correction code data is 4 (dmin = 5).
The number of information data in the 2'' direction is 64, and the number of error correction code data is 4 (dmin = 5).

MIX circuit I 11 has MSB block and L
After mixing the SB blocks, ID signals, synchronization signals, etc. are added. FIG. 8 shows the signal format of one sync block of digital data to which an ID signal, synchronization signal, etc. are added. MSB block 1', LSB block 1'
are data in the C1 direction of the MSB block and LSB block, respectively.

The digital modulation circuit 12 digitally modulates the mixed digital data. The recording signal is then amplified by a recording amplifier 13 and recorded on a tape 15 by a recording head 14.

The reproduction signal reproduced by the reproduction head 16 is
It is amplified by the head amplifier 17 and then sent to the reproduction equalizer circuit 18.
The frequency characteristics are compensated for by the data detection circuit 19, and the data is detected by the data detection circuit 19. The PLL circuit 20 generates a clock synchronized with detection data detected from the reproduced signal. The detected data is demodulated by the digital demodulation circuit 21, and the ID
- The synchronization separation circuit 22 separates the ID signal and synchronization signal from the reproduced digital data. The data division circuit II23 is I
D. The reproduced digital data is separated into MSB blocks and LSB blocks based on the synchronization signal separated by the synchronization separation circuit. The error correction decoding circuit I 24 corrects and detects errors occurring in the MSB block using C1' parity,
The error correction decoding circuit II 25 corrects and detects errors occurring in the LSB block using C1'' parity. The reproduced signal processing circuit I 26 performs intra-block deshuffling processing on the MSB block, and the reproduced signal processing circuit II 27 detects errors occurring in the LSB block. The error correction decoding circuit III 28 corrects and detects errors occurring in the MSB block with C2' parity, and the error correction decoding circuit IV 29 corrects and detects errors occurring in the LSB block with C2'' parity. Error correction and detection. MIX circuit I
I30 mixes the divided MSB block and LSB block data. The reproduced signal processing circuit III 31 performs deshuffling processing, etc., and after correcting errors in the data that could not be corrected, a synchronization signal etc. is added, and the data is converted into an analog signal by the D/A conversion circuit 32. Ru.

[0013] Generally, the above code structure is used in a digital signal recording/reproducing device for video signals, audio signals, etc.
An information symbol block is divided into multiple blocks such as an MSB block and an LSB block, and an error correction code with a different error correction ability is added to each block. The MSB block, which causes a large amount of signal deterioration, has a large error correction ability, and conversely, the LS block, which causes no large deterioration even if an error occurs, is used.
By reducing the error correction capability of the B block,
It is possible to minimize the deterioration of reproduced image quality due to errors that occur during reproduction, and to efficiently record and reproduce with a certain limited transmission capacity, but when considering the scale of the circuit, it is necessary to correct errors on the recording and reproduction sides. It is necessary to provide two circuits, one for MSB data and one for LSB data, for the circuit and error correction decoding circuit.

[0014]

[Problem to be Solved by the Invention] Since the conventional digital recording/reproducing device is configured as described above, there is a problem in that the circuit size inevitably becomes large, making it difficult to miniaturize the system. .

The digital recording/reproducing apparatus according to the present invention has been made to solve the above-mentioned problems, and it is possible to improve the image quality of each information bit when an error occurs when digitally recording/reproducing a video signal. By adding an error correction code with error correction capability according to the degree of importance with respect to deterioration, and taking image quality into consideration, it is possible to suppress deterioration of image quality as much as possible even when constrained by a certain limited transmission capacity. can be,
Another object of the present invention is to provide a digital signal recording and reproducing apparatus that can reduce the circuit scale by reducing the number of error correction code circuits and error correction decoding circuits from four to three.

[0016]

[Means for Solving the Problems] A digital signal recording/reproducing apparatus according to the present invention is capable of converting digital data in which one word is composed of a plurality of bit strings into an upper bit string (MSB bit string) and a lower bit string (LSB bit string) during recording. ), and a data reconstruction means that reconstructs the data of each channel outputted from the dividing means and converts it into digital data in which one word is composed of a bit string of N bits. and,
comprising sector division means for dividing the data of each channel output from the data reconstruction means into a plurality of sectors;
A first error correction code adding means for adding a first error correction code to the MSB sector side with high importance among the data blocks of the two channels; and an output of the first error correction code adding means and the LSB sector. and a second error correction code addition means for adding a second error correction code to the output of the sector reconstruction means. Further, error correction codes are added to the output of the sector reconfiguration means in at least two different directions.

[0017]

[Operation] With the above-described configuration, the digital VTR according to the present invention can reduce the circuit scale by reducing the error correction code circuit and error correction decoding circuit to three each, instead of four.

[0018]

【Example】

Example 1. Hereinafter, the present invention will be explained based on the drawings. Figure 1
1 is a block diagram showing the configuration of a digital signal recording and reproducing apparatus according to an embodiment of the present invention. FIG. In the figure, 1 to 4
, 12 to 22, and 30 to 33 are the same as in the conventional example, and their explanation will be omitted. 40 is an error correction circuit V that adds an error correction code C3 parity to the MSB block, 41 is a delay circuit I that delays the LSB block, and 42 is a MIX circuit I that mixes the data of the MSB block and the LSB block.
II. 43 is a recording signal processing circuit IV that performs a second shuffling process etc. on the mixed digital data block; 44 is an error correction code circuit that adds an error correction code C2 parity to the digital data block that has been subjected to the shuffling process etc. VI, 45 is a recording signal processing circuit V that performs third shuffling processing etc. on the digital data block, and 46 is an error correction code circuit VI that adds an error correction code C1 parity to the digital data block.
I, 47 is an ID/synchronization addition circuit that adds an ID signal, synchronization signal, etc. to the digital data block.

48 is an error correction decoding circuit V that corrects and detects errors occurring in the reproduced digital data block using an error correction code C1 parity; 49 is a reproduced signal processing circuit IV that performs deshuffling processing etc. on the reproduced digital data block; and 50 is a reproduced signal processing circuit The error correction decoding circuit VI, 51 that corrects and detects errors occurring in the reproduced digital data block using the error correction code C2 parity is a reproduced signal processing circuit V that performs deshuffling processing and the like on the reproduced digital data block. 52 is a data division circuit III that divides the reproduced digital data block into an MSB block to which an error correction code C3 parity is added and an LSB block to which no error correction code is added; The error correction code circuit VII, which performs correction and detection using C3 parity, is a delay circuit II that delays the LSB block.

Next, the operation will be explained. FIG. 2 is a flowchart of the configuration of a digital data block according to the present invention. The input signal is converted into digital data by the A/D conversion circuit 2. Shuffling processing and the like are performed by the recording signal processing circuit I3. Figure 2(a)
is a digital data block (block size: 170×64) constructed by the recording signal processing circuit I3. The data is divided into an upper bit string and a lower bit string by the data division circuit I4, and the data is divided into an MSB block and an LSB block (
In FIG. 2(b), the MSB block and LSB block sizes are both 85×64. ).

[0021] An error correction code circuit V is provided on the MSB block side.
40, the error correction code C3 parity (Figure 2(c): d
min = 5) is added. At this time, the LSB block side is delayed by the delay circuit I41 in order to match the timing with the MSB block. (Block size of MSB block: 89 x 64, block size of LSB block: 85 x 64)

Next, the data of the MSB block and the LSB block are mixed in the MIX circuit III 42 to form the digital data block shown in FIG. 2(d). (Block size is 174 x 64) Recording signal processing circuit I
Shuffling processing etc. within the digital data block is performed in V43, and error correction code C2 parity (dmin = 5) is added in error correction code circuit VI44.
The block configuration is shown in e). (Block size is 1
74×68) The recording signal processing circuit V 45 again performs shuffling within this digital data block, and the error correction circuit VII 46 adds an error correction code C1 parity (dmin = 9) to the digital data block. The block configuration is shown in (f). (Block size is 182x68)

Next, an ID signal, a synchronization signal, etc. are added to the digital data block by an ID/synchronization adding circuit 47, resulting in a block configuration as shown in FIG. FIG. 4 shows the signal format of one sync block when the digital data block is configured as shown in FIG. MSB block 1, LS
B block 1 is data of MSB block and LSB block, respectively. The digital data configured as described above is digitally modulated by the digital modulation circuit 12, amplified by the recording amplifier 13, and recorded on the tape 15 by the recording head 14 magnetically.

The recording signal is reproduced by the reproduction head 16 and amplified by the head amplifier 17. The frequency characteristics of the amplified reproduction signal are compensated by a reproduction equalizer circuit 18, and data is detected by a data detection circuit 19. The PLL circuit 20 generates a clock synchronized with detection data detected from the reproduced signal. The detected data is demodulated by a digital demodulation circuit 21, and an ID/synchronization separation circuit 22 separates an ID signal and a synchronization signal from the reproduced digital data. Error correction decoding circuit V48 is a reproduced digital data block IV4
9 performs deshuffling processing and the like within the reproduced digital data block. The error correction decoding circuit VI50 converts errors occurring in the reproduced digital data block into an error correction code C2.
Correct and detect by parity, reproduced signal processing circuit V 51
performs deshuffling processing within the reproduced digital data block.

The reproduced digital data block is then divided into an LSB block and an MSB block to which an error correction code C3 parity is added in the data division circuit III 52. The error correction decoding circuit VII 53 corrects and detects errors occurring in the MSB block using an error correction code C3 parity. Also, the delay circuit II has the LSB block and the MSB block.
Delay LSB blocks to align block timing. The data of the MSB block and the LSB block are mixed in the MIX circuit II 30, and subjected to deshuffling processing etc. in the reproduced signal processing circuit III 31, and after correcting errors in data that could not be corrected,
A synchronization signal and the like are added to the signal, and the signal is converted into an output signal by the D/A conversion circuit 32.

[0026] In a digital signal recording and reproducing apparatus that digitally records a video signal using such a method, the A/D
Convert digital data to MSB data block and L
The data is divided into SB data blocks, and an error correction code is added to the MSB data block, which is important for image quality, in advance.
LSB block and MSB to which the error correction code is added
After mixing blocks, LSB block and MSB
By adding an error correction code to a digital data block that has been mixed, it is possible to minimize the deterioration of reproduced image quality due to errors that occur during reproduction, and to efficiently record and reproduce with a certain limited transmission capacity. The number of correction code circuits and error correction decoding circuits can be reduced from four to three, respectively, and the overall circuit scale can be reduced.

Example 2. In this example, the above symbols,
Although the block configuration is performed using the code length, the present invention is not limited to this, and the same effect can be achieved using any information block size and any error correction code.

Example 3. In this embodiment, the delay circuit I
41, a delay circuit II54 is used, but the delay circuit is not necessarily necessary, for example, in a recording system, a recording signal processing circuit IV is used.
43. In the reproduction system, the reproduction signal processing circuit III 31 controls writing and reading of the memory, so that even if it is omitted, the same effect can be obtained. .

Example 4. In this embodiment, the format of one sync block as shown in FIG. 4 is defined, but the format is not limited to this. For example, a format of one sync block with only MSB or only LSB can have the same effect.

Example 5. In this embodiment, a triple Reed-Solomon error correction code in the product code format is used for the MSB block, and a double Reed-Solomon error correction code in the product code format is used for the LSB block, but the present invention is not limited to this. A similar effect can be achieved with a code format of an L-multiplex (M>N) error correction code in the LSB block.

In the above description, the present invention has been described in relation to video signals, but it goes without saying that it can also be applied to digital recording and reproducing devices for audio and the like.

[0032]

[Effects of the Invention] Since the present invention is constructed as described above, it produces the following effects.

[0033] First, an information symbol block is divided into two, an MSB block and an LSB block, an error correction code is added only to the MSB block side, and after mixing again, error correction codes are added in a plurality of different directions. It minimizes deterioration of reproduced image quality due to errors that occur during reproduction, enables recording and reproduction even with a certain limited transmission capacity, and reduces the number of error correction code circuits and error correction decoding circuits from 4 to 3.
Even if the circuit scale is reduced to 4, the same effect as when the number of error correction code circuits and error correction decoding circuits is four is obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a digital signal recording and reproducing apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart showing the configuration of a data block according to the present invention.

FIG. 3 is a diagram showing the configuration of a Reed-Solomon product code according to the present invention.

FIG. 4 is a diagram showing the structure of a sector format according to the present invention.

FIG. 5 is a block diagram showing a conventional digital signal recording/reproducing device.

FIG. 6 is a diagram showing the configuration of a conventional data division circuit.

FIG. 7 is a diagram showing the configuration of a conventional Reed-Solomon product code.

FIG. 8 is a diagram showing the structure of a conventional sector format.

[Explanation of symbols]

2 A/D conversion circuit 4 Data division circuit I 40 Error correction code circuit V 42 MIX circuit III 44 Error correction code circuit VI 46 Error correction code circuit VII

Claims (2)

[Claims] Claim 1: A digital signal recording and reproducing apparatus that converts an input signal into digital data, each word of which is composed of a bit string of N bits, and records and reproduces the data.
A dividing means for dividing the digital data in which one word is composed of a plurality of bit strings into two-channel data blocks of an upper bit string (MSB bit string) and a lower bit string (LSB bit string), and each channel output from the dividing means. data reconstruction means for reconstructing the data and converting it into digital data in which one word is composed of a bit string of N bits; and a sector for dividing the data of each channel outputted from the data reconstruction means into a plurality of sectors. a first error correction code adding means having a dividing means and adding a first error correction code to the MSB sector side having a high importance among the data blocks of the two channels; and the first error correction code adding means. A digital device comprising sector reconfiguration means for reconfiguring the output of the means and the LSB sector, and second error correction code adding means for adding a second error correction code to the output of the sector reconfiguration means. Signal recording and reproducing device. 2. The digital signal according to claim 1, wherein the second error correction code addition means adds error correction codes to the output of the sector reconfiguration means in at least two different directions. Recording and playback device.