JPH0437011A - A laminated ceramic capacitor - Google Patents
A laminated ceramic capacitorInfo
- Publication number
- JPH0437011A JPH0437011A JP14149890A JP14149890A JPH0437011A JP H0437011 A JPH0437011 A JP H0437011A JP 14149890 A JP14149890 A JP 14149890A JP 14149890 A JP14149890 A JP 14149890A JP H0437011 A JPH0437011 A JP H0437011A
- Authority
- JP
- Japan
- Prior art keywords
- dielectric
- ceramic
- substrate
- ceramic capacitor
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003985 ceramic capacitor Substances 0.000 title claims abstract description 51
- 239000000919 ceramic Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000003989 dielectric material Substances 0.000 claims abstract description 31
- 239000000463 material Substances 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 239000000126 substance Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 7
- 239000000203 mixture Substances 0.000 description 7
- 238000010438 heat treatment Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010304 firing Methods 0.000 description 3
- 238000010030 laminating Methods 0.000 description 3
- 239000000843 powder Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- VTYYLEPIZMXCLO-UHFFFAOYSA-L Calcium carbonate Chemical compound [Ca+2].[O-]C([O-])=O VTYYLEPIZMXCLO-UHFFFAOYSA-L 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- NUJOXMJBOLGQSY-UHFFFAOYSA-N manganese dioxide Chemical compound O=[Mn]=O NUJOXMJBOLGQSY-UHFFFAOYSA-N 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- XNWFRZJHXBZDAG-UHFFFAOYSA-N 2-METHOXYETHANOL Chemical compound COCCO XNWFRZJHXBZDAG-UHFFFAOYSA-N 0.000 description 1
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 description 1
- 229910020698 PbZrO3 Inorganic materials 0.000 description 1
- 239000004372 Polyvinyl alcohol Substances 0.000 description 1
- 101710162453 Replication factor A Proteins 0.000 description 1
- 102100035729 Replication protein A 70 kDa DNA-binding subunit Human genes 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 229910000019 calcium carbonate Inorganic materials 0.000 description 1
- 235000010216 calcium carbonate Nutrition 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000011812 mixed powder Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920002451 polyvinyl alcohol Polymers 0.000 description 1
- OGHBATFHNDZKSO-UHFFFAOYSA-N propan-2-olate Chemical compound CC(C)[O-] OGHBATFHNDZKSO-UHFFFAOYSA-N 0.000 description 1
- 238000010298 pulverizing process Methods 0.000 description 1
- 238000010992 reflux Methods 0.000 description 1
- 239000000344 soap Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、温度特性が優れた積層セラミックコンデンサ
に関する。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a multilayer ceramic capacitor with excellent temperature characteristics.
（従来の技術）
以前より、セラミック誘電体と電極とが交互に多数積層
されてなる積層セラミックコンデンサは広く知られてい
る。このような積層セラミックコンデンサに対しては、
誘電率等の電気的特性が優れていることが求められるの
は言うまでもないが、さらには広範囲な温度領域にわた
って安定な温度特性を要求される場合が多い。例えばＥ
ＩＡ（米国電子工業会）規格の１７Ｒ規格では、−５５
℃〜＋１２５℃の温度領域における容量の変化率が±２
２％以内と規定されている。(Prior Art) Multilayer ceramic capacitors in which a large number of ceramic dielectrics and electrodes are alternately stacked have been widely known. For such multilayer ceramic capacitors,
Needless to say, they are required to have excellent electrical properties such as dielectric constant, but they are also often required to have stable temperature characteristics over a wide temperature range. For example, E
According to the IA (Electronic Industries Association) 17R standard, -55
The rate of change in capacitance in the temperature range from ℃ to +125℃ is ±2
It is stipulated to be within 2%.
このような要求に対して、温度特性の異なる誘電体材料
からなるセラミック誘電体を積層することにより、積層
セラミックコンデンサの容量温度係数を平坦化せしめる
技術が報告されている。例えば特開昭４８−６５４４６
号公報には、温度特性の異なる誘電体材料からなる複数
種の誘電体生シートを別個に用意し、前記誘電体生シー
ト上に内部電極となる金属層を印刷した後、積層、一体
焼成を行なうことにより得られる積層セラミックコンデ
ンサが開示されている。しかしながら係る積層セラミッ
クコンデンサでは、前述したように異なる誘電体材料か
らなるセラミック誘電体が積層されているため、係るセ
ラミック誘電体間の熱膨張係数の相違に起因して、焼成
時や実装の際の加熱時にクラックを生じやすいという問
題があった。また、クラックを生じないまでも積層セラ
ミックコンデンサ内に大きな応力が残留するため、電気
的特性や機械的強度が低下するおそれがあり信頼性が乏
しかった。さらには、焼成時等に温度特性の異なる誘電
体材料からなるセラミック誘電体間で材料の拡散が発生
して、目的とする容量温度係数の平坦化が達成されない
場合も多かった。In response to such demands, a technique has been reported for flattening the capacitance temperature coefficient of a multilayer ceramic capacitor by laminating ceramic dielectrics made of dielectric materials having different temperature characteristics. For example, JP-A-48-65446
The publication discloses that multiple types of dielectric green sheets made of dielectric materials with different temperature characteristics are separately prepared, a metal layer to be an internal electrode is printed on the dielectric green sheets, and then laminated and integrally fired. A multilayer ceramic capacitor obtained by the above method is disclosed. However, in such multilayer ceramic capacitors, ceramic dielectrics made of different dielectric materials are laminated as described above, and therefore, due to the difference in thermal expansion coefficient between the ceramic dielectrics, there are problems during firing and mounting. There was a problem that cracks were likely to occur during heating. Furthermore, even if no cracks occur, large stress remains within the multilayer ceramic capacitor, which may lead to a decrease in electrical characteristics and mechanical strength, resulting in poor reliability. Furthermore, during firing or the like, material diffusion occurs between ceramic dielectrics made of dielectric materials with different temperature characteristics, and the desired flattening of the temperature coefficient of capacitance is often not achieved.
（発明が解決しようとする課題）
上述したように、積層セラミックコンデンサにおいては
温度特性が良好であることが求められているが、電気的
特性、機械的強度等を低下させることなく温度特性を向
上せしめる技術は、従来知られてはいなかった。(Problems to be Solved by the Invention) As mentioned above, multilayer ceramic capacitors are required to have good temperature characteristics, but it is necessary to improve the temperature characteristics without reducing electrical characteristics, mechanical strength, etc. The technology to do this was previously unknown.
本発明はこのような問題点に鑑みて、平坦な容量温度係
数を有して温度特性が良好であり、且つ電気的特性、機
械的強度も十分な信頼性の高い積層セラミックコンデン
サを提供することを目的としている。In view of these problems, the present invention provides a highly reliable multilayer ceramic capacitor that has a flat capacitance temperature coefficient, good temperature characteristics, and sufficient electrical characteristics and mechanical strength. It is an object.
（課題を解決するための手段）
本発明は、基板の上面及び下面にセラミック誘電体と前
記セラミック誘電体を介して対向する一対の内部電極と
が積層され、さらに前記一対の内部電極とそれぞれ電気
的に接続する一対の外部電極が積層体の両端部に形成さ
れてなる積層セラミックコンデンサにおいて、前記セラ
ミック誘電体の材料として温度特性の異なる誘電体材料
が基板の上面及び下面でそれぞれ用いられている積層セ
ラミックコンデンサである。すなわち本発明の積層セラ
ミックコンデンサは、温度特性の異なる誘電体材料から
なるセラミック誘電体間に基板が介在していることを特
徴としている。(Means for Solving the Problems) The present invention has a ceramic dielectric and a pair of internal electrodes facing each other via the ceramic dielectric, which are laminated on an upper surface and a lower surface of a substrate, and further electrically connected to the pair of internal electrodes, respectively. In a multilayer ceramic capacitor in which a pair of external electrodes that are electrically connected are formed at both ends of a laminate, dielectric materials having different temperature characteristics are used as the ceramic dielectric material on the top and bottom surfaces of the substrate, respectively. It is a multilayer ceramic capacitor. That is, the multilayer ceramic capacitor of the present invention is characterized in that a substrate is interposed between ceramic dielectrics made of dielectric materials having different temperature characteristics.
このような本発明の積層セラミックコンデンサの縦断面
図を第１図に示す。第１図に示されたように本発明の積
層セラミックコンデンサでは、基板■の上面及び下面に
内部電極■とセラミック誘電体（３−１，３−２）が交
互に積層され、基板■の上面に積層された第１のセラミ
ック誘電体（３−１）と基板■の下面に積層された第２
のセラミック誘電体（３−２）について、温度特性の異
なる誘電体材料が用いられる。さらに積層体の両端部に
は、セラミック誘電体（３−１，３−２）を介して対向
する内部電極■のいずれか一方と電気的に接続する一対
の外部電極に）が形成される。FIG. 1 shows a longitudinal cross-sectional view of such a multilayer ceramic capacitor according to the present invention. As shown in FIG. 1, in the multilayer ceramic capacitor of the present invention, internal electrodes (2) and ceramic dielectrics (3-1, 3-2) are alternately laminated on the upper and lower surfaces of the substrate (1), and A first ceramic dielectric (3-1) laminated on the substrate (3-1) and a second ceramic dielectric (3-1) laminated on the bottom surface of the
For the ceramic dielectric (3-2), dielectric materials having different temperature characteristics are used. Further, at both ends of the laminate, a pair of external electrodes are formed which are electrically connected to either one of the opposing internal electrodes (2) via the ceramic dielectric (3-1, 3-2).
さらに本発明では、基板■の上面及び下面で内部電極■
及びセラミック誘電体（３−１，３−２）を３層以上積
層して、積層セラミックコンデンサを多層化することも
できる。第２図に、このような積層セラミックコンデン
サの縦断面図を示した。Furthermore, in the present invention, the internal electrodes ■ are provided on the upper and lower surfaces of the substrate ■.
It is also possible to form a multilayer ceramic capacitor by laminating three or more layers of ceramic dielectrics (3-1, 3-2). FIG. 2 shows a longitudinal cross-sectional view of such a multilayer ceramic capacitor.
なお、第１図及び第２図に示した本発明の積層セラミッ
クコンデンサでは、第１のセラミック誘電体（３−１）
と第２のセラミック誘電体（３−２）の厚さ及び積層数
が等しくなっているが１本発明においては第１のセラミ
ック誘電体（３−１）と第２のセラミック誘電体（３−
２）の厚さ及び積層数が異なっていてもよい。本発明で
は、第１のセラミック誘電体と第２のセラミック誘電体
の厚さ、積層数を適宜変えることにより、積層セラミッ
クコンデンサの容量、容量温度係数等ｔｉ−調整するこ
とが可能であり、所望の特性を有する積層セラミックコ
ンデンサ登容易に得ることができる。In addition, in the multilayer ceramic capacitor of the present invention shown in FIGS. 1 and 2, the first ceramic dielectric (3-1)
The thickness and the number of laminated layers of the first ceramic dielectric (3-1) and the second ceramic dielectric (3-2) are the same, but in the present invention, the first ceramic dielectric (3-1) and the second ceramic dielectric (3-2)
The thickness and number of laminated layers in 2) may be different. In the present invention, by appropriately changing the thickness and the number of laminated layers of the first ceramic dielectric and the second ceramic dielectric, it is possible to adjust the capacitance, capacitance temperature coefficient, etc. of the multilayer ceramic capacitor as desired. Multilayer ceramic capacitors with these characteristics can be easily obtained.
本発明では、基板の厚さは２００Ｉｎａ以上１０００ｔ
Ｕ以下であることが好ましい。すなわち、本発明の積層
セラミックコンデンサにおいては、前記第１のセラミッ
ク誘電体と第２のセラミック誘電体との熱膨張係数の相
違に起因して、焼成時や実装時に発生する内部応力は、
基板に吸収される。従って。In the present invention, the thickness of the substrate is 200 Ina or more and 1000 T.
It is preferable that it is U or less. That is, in the multilayer ceramic capacitor of the present invention, the internal stress generated during firing or mounting due to the difference in thermal expansion coefficient between the first ceramic dielectric and the second ceramic dielectric is
absorbed by the substrate. Therefore.
従来の積層セラミックコンデンサのように内部応力がセ
ラミック誘電体に残存して、積層セラミックコンデンサ
の電気的特性を著しく低下させるおそれがない。しかし
ながらこのとき基板が薄すぎると、基板に前述したよう
な内部応力が吸収されたときに、基板自体の強度が小さ
いため基板においてクラックが発生するおそれがあり、
積層セラミックコンデンサの信頼性が低下してしまう。Unlike conventional multilayer ceramic capacitors, there is no risk of internal stress remaining in the ceramic dielectric and significantly deteriorating the electrical characteristics of the multilayer ceramic capacitor. However, if the substrate is too thin at this time, there is a risk that cracks will occur in the substrate when the substrate absorbs the above-mentioned internal stress because the strength of the substrate itself is low.
The reliability of the multilayer ceramic capacitor decreases.
逆に、基板が上記したような範囲を越えて厚いと、小型
で大容量の積層セラミックコンデンサを得ることが困難
となる。また係る基板には、前記第１のセラミック誘電
体及び第２のセラミック誘電体のいずれか一方と同一の
誘電体材料が用いられることが望ましい。この理由は、
基板とその上面又は下面に積層されたセラミック誘電体
とが同一材料からなれば、前述したように基板に吸収さ
れる内部応力が低減されるからである。このような本発
明で用いることのできる誘電体材料としては。On the other hand, if the thickness of the substrate exceeds the above range, it becomes difficult to obtain a small, large-capacity multilayer ceramic capacitor. Further, it is desirable that the same dielectric material as either the first ceramic dielectric or the second ceramic dielectric is used for such a substrate. The reason for this is
This is because if the substrate and the ceramic dielectric layered on the upper or lower surface of the substrate are made of the same material, the internal stress absorbed by the substrate is reduced as described above. Examples of dielectric materials that can be used in the present invention include:
Ｐ ｂｃＭｇｘ／ａ Ｎｂｚｔｚ＞Ｏｓ、Ｐｂ（Ｚｎｘ
／１Ｎｂｚｚａ）Ｏａ、Ｐｂ（ＦｅｚｚａＷｘｚ３）Ｏ
ａ、ＰｂＺｒＯ３等の鉛含有ヘロブスカイト型組成物や
ＢａＴｉ０．．５ｒＴｉＯ，、Ｎ ｄ Ｔ ｉ Ｏ３等
のチタン酸塩、さらにはこれらの置換体、複合体等が挙
げられる。さらに本発明では。P bcMgx/a Nbztz>Os, Pb(Znx
/1Nbzza)Oa,Pb(FezzaWxz3)O
a, lead-containing herovskite type compositions such as PbZrO3 and BaTi0. ．． Examples include titanates such as 5rTiO, N d Ti O3, and substituted products and complexes thereof. Furthermore, in the present invention.
第１のセラミック誘電体及び第２のセラミック誘電体に
構成元素は同じで組成の異なる誘電体材料を用いれば、
積層体の層間の整合性が良好となりより好ましい。If dielectric materials with the same constituent elements but different compositions are used for the first ceramic dielectric and the second ceramic dielectric,
This is more preferable since the consistency between the layers of the laminate is good.
本発明において、基板上に内部電極及びセラミック誘電
体を積層する方法としては、厚膜形成法、薄膜形成法の
いずれを利用することもできるが、より好ましくは、各
層の厚さを５−以下程度とすることが可能な薄膜形成法
を利用することが望ま積層されるセラミック誘電体の熱
処理を同時に一括して行なっても良いし、各層を形成す
る際に逐次熱処理を行なっても良い。さらにまず２枚の
基板を用意して、一方の基板には内部電極と第１のセラ
ミック誘電体とを交互に積層し、他方の基板には内部電
極と第２のセラミック誘電体とを交互に積層した後、こ
れらの基板を張り合わせても本Ｙ発明の積層セラミック
コンデンサを得ることができる。In the present invention, as a method for laminating internal electrodes and ceramic dielectrics on a substrate, either a thick film formation method or a thin film formation method can be used, but it is more preferable to set the thickness of each layer to 5 mm or less. It is preferable to use a thin film forming method that allows for the formation of a thin film at a certain level.The heat treatment of the laminated ceramic dielectrics may be performed all at once, or the heat treatment may be performed sequentially when forming each layer. Further, first, two substrates are prepared, and internal electrodes and a first ceramic dielectric are alternately laminated on one substrate, and internal electrodes and a second ceramic dielectric are alternately laminated on the other substrate. After lamination, the laminated ceramic capacitor of the present invention can also be obtained by bonding these substrates together.
（作用）
本発明の積層セラミックコンデンサにおいては、温度特
性の異なる誘電体材料からなる第１のセラミック誘電体
と第２のセラミック誘電体との間に基板が介在している
ために、第１のセラミック誘電体と第２のセラミック誘
電体との熱膨張係的特性が劣化することがなく、また積
層セラミックコンデンサの機械的強度が低下してクラッ
クが生じるおそれも少ない。さらに本発明の積層セラミ
ックコンデンサでは、前記第１のセラミック誘電体と第
２のセラミック誘電体との間で材料の拡散が起こるおそ
れがなく、容量温度係数の平坦化が有効に達成される。(Function) In the multilayer ceramic capacitor of the present invention, since the substrate is interposed between the first ceramic dielectric and the second ceramic dielectric made of dielectric materials having different temperature characteristics, the first The thermal expansion characteristics of the ceramic dielectric and the second ceramic dielectric do not deteriorate, and there is little risk of the mechanical strength of the multilayer ceramic capacitor decreasing and causing cracks. Furthermore, in the multilayer ceramic capacitor of the present invention, there is no fear of material diffusion occurring between the first ceramic dielectric and the second ceramic dielectric, and flattening of the temperature coefficient of capacitance is effectively achieved.
すなわち第３図は、本発明の積層セラミックコンデンサ
の温度特性を模式的に示す特性図であり、図中のＡ、Ｂ
、Ｃはそれぞれ第１のセラミック誘電体、第２のセラミ
ック誘電体及び得られる積層セラミックコンデンサの容
量変化率を示している。第３図に示されるように、本発
明の積層セラミックコンデンサでは、広い温度領域にわ
たって容量変化率の値が非常に小さく。That is, FIG. 3 is a characteristic diagram schematically showing the temperature characteristics of the multilayer ceramic capacitor of the present invention.
, C indicate the capacitance change rate of the first ceramic dielectric, the second ceramic dielectric, and the obtained multilayer ceramic capacitor, respectively. As shown in FIG. 3, in the multilayer ceramic capacitor of the present invention, the capacitance change rate is extremely small over a wide temperature range.
極めて安定した温度特性が得られている。Extremely stable temperature characteristics have been obtained.
（実施例） 以下に、本発明の実施例を示す。(Example) Examples of the present invention are shown below.
実施例１ まず所定量のＰｂＯ，ＣａＣＯ３、ＴｊＯ，。Example 1 First, predetermined amounts of PbO, CaCO3, TjO,.
Ｍ ｎ Ｏ２を秤量し、ボールミル等を用いて湿式にて
混合粉砕した。次いで、１５０°Ｃ１１７時間の乾燥を
行ない乾式にて粉砕した後、アルミナ製のサヤに入れ９
００℃で２時間仮焼した。仮焼した粉体をボールミルを
用いて湿式にて粒径０．５〜３ＩＩＪｒ１程度にまで粉
砕し、得られた粉体に対して５ｔｉｔ％のポリビニルア
ルコール水溶液を加えた後、５０ＩφＸ１５Ｉの成形体
とした。この成形体を通常のホットプレス法により１１
００℃、２時間焼成し、焼成体より２０ｍｎ Ｘ ２０
ｍａ Ｘ ０．５ｍｍの角板を切り出した。 さらに前
記角板の両面を鏡面まで研磨することにより、（Ｐ ｂ
ａ、ｔｓ Ｃａｏ、ｚｓ）（Ｔｌａ、ｓｑ Ｍｎ０．。MnO2 was weighed and wet mixed and pulverized using a ball mill or the like. Next, after drying at 150°C for 117 hours and dry-pulverizing, the powder was placed in an alumina pod for 9 hours.
It was calcined at 00°C for 2 hours. The calcined powder was wet-pulverized using a ball mill to a particle size of about 0.5 to 3IIJr1, and after adding a 5tit% polyvinyl alcohol aqueous solution to the obtained powder, it was made into a molded body of 50IφX15I. did. This molded body was heated to 11
00℃, 2 hours, 20mm x 20 from the fired body
A square plate of ma x 0.5 mm was cut out. Furthermore, by polishing both sides of the square plate to a mirror surface, (P b
a, ts Cao, zs) (Tla, sq Mn0.
、）０３なる組成を有するセラミック基板が得られた。, )03 was obtained.
次いで、係る基板の両面の所定の位置にスパッタリング
法により内部電極となる厚さ２０００人のｐｔ層を形成
した後、片面に基板と同一組成を有する厚さ約１趣の第
１のセラミック誘電体を以下に示Ｐト
す方法により形成した。まず、’ｆ、＆、Ｃａ、Ｍｎの
各酢酸塩及びＴｉイソプロポキシドを所定のモル比で秤
量、混合した後、混合物の２−メトキシエタノール溶液
を調製した。２時間の還流操作の後、係る溶液を基板上
にスピンコーティングし、続いて７５０℃、３０分間の
熱処理を行ない、結晶化したセラミックとした。その後
セラミック誘電体が所望の厚さになるまで、前述したよ
うな塗布及び熱処理の工程を繰り返した。次いで、得ら
れた第１のセラミック誘電体上の所定の位置にスパッタ
リング法により内部電極となる厚さ２０００人の ｐｔ
層を形成した。さらにこの上に、厚さ１．０陣の第１の
セラミック誘電体を前述したような方法と同様にして形
成した。Next, after forming a PT layer with a thickness of 2,000 layers to serve as internal electrodes at predetermined positions on both sides of the substrate by sputtering, a first ceramic dielectric layer having a thickness of about 1 layer and having the same composition as the substrate is formed on one side. was formed by the method shown below. First, each acetate of 'f, &, Ca, Mn and Ti isopropoxide were weighed and mixed at a predetermined molar ratio, and then a 2-methoxyethanol solution of the mixture was prepared. After a reflux operation for 2 hours, the solution was spin-coated onto a substrate, followed by heat treatment at 750° C. for 30 minutes to form a crystallized ceramic. Thereafter, the coating and heat treatment steps described above were repeated until the ceramic dielectric had the desired thickness. Next, a 2000 pt thick film, which will become an internal electrode, is deposited on a predetermined position on the obtained first ceramic dielectric by sputtering.
formed a layer. Furthermore, a first ceramic dielectric having a thickness of 1.0 mm was formed thereon in the same manner as described above.
次に、基板の反対側の面に（Ｐ ｂａ、４ｓ Ｃａｏ、
、、）（Ｔｌｏ、＊ｓＭｎｏ、ｏｘ）０３からなる厚さ
１．０μｓの第２セラミック誘電体、厚さ２０００人の
ｐｔ層及び厚さ１、ＯＩｓの第２のセラミック誘電体を
同様にして順次形成した。さらに得られた積層体の両端
部をダイヤモンド・ソープで切断した後、この面にｐｔ
−Ａｇペーストを７００℃で焼き付は一対の外部電極を
形成して、本発明の積層セラミックコンデンサを得た。Next, on the opposite side of the substrate (P ba, 4s Cao,
,, )(Tlo,*sMno,ox)03, a second ceramic dielectric of thickness 1.0 μs, a pt layer of thickness 2000 and a second ceramic dielectric of thickness 1, OIs. Formed sequentially. Furthermore, after cutting both ends of the obtained laminate with diamond soap, this surface was coated with PT.
-Ag paste was baked at 700° C. to form a pair of external electrodes to obtain a multilayer ceramic capacitor of the present invention.
得られた積層セラミックコンデンサの電気的特性を測定
したところ、容量０．０５μＦ、誘電損失１．１％であ
り、容量変化率は一５５〜＋１２５℃の温度範囲で±２
％以内であった。さらに機械的強度も充分であり、係る
積層セラミックコンデンサが優れた特性を有しているこ
とが確認された。When the electrical characteristics of the obtained multilayer ceramic capacitor were measured, the capacitance was 0.05μF, the dielectric loss was 1.1%, and the capacitance change rate was ±2 in the temperature range of -55 to +125℃.
It was within %. Furthermore, the mechanical strength was sufficient, and it was confirmed that the multilayer ceramic capacitor had excellent characteristics.
実施例２
基板の材料として
Ｐ ｂ［（Ｍｇｉｚａ Ｎｂ２ｚｉ ）ｏ 、 ｓ Ｔ
１０ 、 ｘ １０ ａ＋０．Ｅｖ＋ｏｆｆｉ％Ｍｎ
Ｏ１第１のセラミック誘電体の材料として
Ｐｂ［（Ｍｇｚｚａ Ｎｂｚ／ｘ）ｏ、ｔｓ Ｔｉｏ、
ｚＪＯｉ 十〇−５１１０４％ＭｎＯ，第２のセラミッ
ク誘電体の材料として（Ｐ ｂｏ、ｓｓ Ｂ ａｏ 、
ｏｓ）［（Ｍｇｚｚａ Ｎｂ２／３）Ｏ、ｓ Ｔ ｌｏ
、ｘ ］ Ｏａ＋０．１ｍａｉ１％Ｍ ｎ Ｏを用い
て、実施例１と同様の方法で本発明の積層セラミックコ
ンデンサを得た。Example 2 Pb[(Mgiza Nb2zi)o, sT as the material of the substrate
10, x 10 a+0. Ev+offi%Mn
O1 As the material of the first ceramic dielectric, Pb[(Mgzza Nbz/x)o, ts Tio,
zJOi 10-51104% MnO, as the material of the second ceramic dielectric (P bo, ss Bao,
os) [(Mgzza Nb2/3)O,s T lo
, x] A multilayer ceramic capacitor of the present invention was obtained in the same manner as in Example 1 using Oa+0.1mai1%MnO.
得られた積層セラミックコンデンサの電気的特性は、容
量１．０μＦ、誘電損失１．９％で、容量変化率は一２
５〜＋８５℃の温度範囲で±１０％以内であった。The electrical characteristics of the obtained multilayer ceramic capacitor are as follows: capacitance: 1.0 μF, dielectric loss: 1.9%, capacitance change rate: -2
It was within ±10% in the temperature range of 5 to +85°C.
さらに機械的強度も充分であり、係る積層セラミックコ
ンデンサは優れた特性を有していることが確認された。Furthermore, the mechanical strength was sufficient, and it was confirmed that the multilayer ceramic capacitor had excellent characteristics.
実施例３
まず、実施例１と同様の基板両面の所定の位置に、ＲＦ
マグネトロンスパッタリング法により内部電極として厚
さ５０００人のｐｔ層を形成した。次いで前記Ｐｔ層の
形成された基板の両面に、ＰｂＴｉ０．、Ｐｂ０．Ｃａ
ｏ、ＭｎＯの混合粉体をターゲットとして、Ａｒ： Ｏ
，＝９６： ４の混合ガス雰囲気、エネルギー１．５Ｗ
／ｄ、基板温度６００℃、成膜速度４０人／分、圧力Ｉ
Ｐａの条件で、ＲＦマグネトロンスパッタリング法によ
り厚さ１．Ｏｔｍの第１のセラミック誘電体及び第２の
セラミック誘電体を形成した。このとき、それぞれター
ゲットの組成を変えることにより、第１のセラミック誘
電体の組成を（Ｐ ｂｏ、ｔｚ Ｃａｏ、ｚｓ）（Ｔｌ
ｏ、ｉｉＭｎｏ、ａｔ）Ｏａ、第２のセラミック誘電体
の組成を
（Ｐｂ（１，５［１ｃａａ、５ｏ）（Ｔｉｏ、ｓｓＭｎ
ａ、ａ、）ｏａとした。Example 3 First, in the same way as in Example 1, an RF
A PT layer with a thickness of 5000 nm was formed as an internal electrode by magnetron sputtering. Next, PbTi0. , Pb0. Ca
Ar: O, using a mixed powder of MnO as a target.
,=96: 4 mixed gas atmosphere, energy 1.5W
/d, substrate temperature 600°C, deposition rate 40 people/min, pressure I
The thickness is 1.5 mm by RF magnetron sputtering under conditions of Pa. Otm first and second ceramic dielectrics were formed. At this time, by changing the composition of each target, the composition of the first ceramic dielectric is changed to (P bo, tz Cao, zs) (Tl
o, iiMno, at) Oa, the composition of the second ceramic dielectric is (Pb (1,5 [1caa, 5o) (Tio, ssMn
a, a, ) oa.
この後上述したような内部電極及びセラミック誘電体の
形成を繰り返して、本発明の積層セラミックコンデンサ
を得た。ただし、セラミック誘電体の積層数は、第１の
セラミック誘電体、第２のセラミック誘電体とも、最上
層及び最下層に形成されたカバーシートとなるセラミッ
ク誘電体を除いて、各４層とした。Thereafter, the formation of internal electrodes and ceramic dielectrics as described above was repeated to obtain a multilayer ceramic capacitor of the present invention. However, the number of laminated ceramic dielectrics was 4 for each of the first ceramic dielectric and the second ceramic dielectric, excluding the ceramic dielectric that forms the cover sheet formed on the top and bottom layers. .
得られた積層セラミックコンデンサの電気的特性は、容
量０．０１μＦ、誘電損失２．０％で、容量変化率は一
３０〜＋８５℃の温度範囲で±５％以内であった。さら
に機械的特性も充分であり、係る積層セラミックコンデ
ンサは優れた特性を有していることが確認された。The electrical characteristics of the obtained multilayer ceramic capacitor were a capacitance of 0.01 μF, a dielectric loss of 2.0%, and a capacitance change rate within ±5% in the temperature range of -30 to +85°C. Furthermore, the mechanical properties were also sufficient, and it was confirmed that the multilayer ceramic capacitor had excellent properties.
以上詳述したように、本発明によれば温度特性が優れ、
しかも電気的特性、機械的強度も良好で極めて信頼性の
高い積層セラミックコンデンサを提供することができる
。As detailed above, according to the present invention, the temperature characteristics are excellent,
Furthermore, it is possible to provide a highly reliable multilayer ceramic capacitor with good electrical properties and mechanical strength.
第１図は本発明の積層セラミックコンデンサの一態様を
示す縦断面図、第２図は本発明の積層セラミックコンデ
ンサの他の態様を示す縦断面図、第３図は本発明の積層
セラミックコンデンサの温度特性を示す特性図である。
１・・・基板
２・・・内部電極
３−１゜
３−２・・・セラミック誘電体
４・・・外部電極FIG. 1 is a longitudinal sectional view showing one embodiment of the multilayer ceramic capacitor of the present invention, FIG. 2 is a longitudinal sectional view showing another embodiment of the multilayer ceramic capacitor of the present invention, and FIG. 3 is a longitudinal sectional view of the multilayer ceramic capacitor of the present invention. FIG. 3 is a characteristic diagram showing temperature characteristics. 1...Substrate 2...Internal electrode 3-1゜3-2...Ceramic dielectric 4...External electrode
Claims (1)
ラミック誘電体を介して対向する一対の内部電極とが積
層され、さらに前記一対の内部電極とそれぞれ電気的に
接続する一対の外部電極が形成されてなる積層セラミッ
クコンデンサにおいて、前記セラミック誘電体の材料と
して温度特性の異なる誘電体材料が基板の上面及び下面
でそれぞれ用いられていることを特徴とする積層セラミ
ックコンデンサ。(1) A ceramic dielectric and a pair of internal electrodes facing each other via the ceramic dielectric are laminated on the upper and lower surfaces of the substrate, and further a pair of external electrodes are formed, each electrically connected to the pair of internal electrodes. 1. A multilayer ceramic capacitor comprising a multilayer ceramic capacitor, characterized in that dielectric materials having different temperature characteristics are used as the ceramic dielectric material on the upper surface and the lower surface of the substrate, respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14149890A JPH0437011A (en) | 1990-06-01 | 1990-06-01 | A laminated ceramic capacitor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14149890A JPH0437011A (en) | 1990-06-01 | 1990-06-01 | A laminated ceramic capacitor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0437011A true JPH0437011A (en) | 1992-02-07 |
Family
ID=15293343
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14149890A Pending JPH0437011A (en) | 1990-06-01 | 1990-06-01 | A laminated ceramic capacitor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0437011A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008535274A (en) * | 2005-03-31 | 2008-08-28 | インテル・コーポレーション | Integrated thin film capacitors with optimized temperature characteristics |
| JP2014033241A (en) * | 2010-06-24 | 2014-02-20 | Tdk Corp | Chip thermister and manufacturing method therefor |
-
1990
- 1990-06-01 JP JP14149890A patent/JPH0437011A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008535274A (en) * | 2005-03-31 | 2008-08-28 | インテル・コーポレーション | Integrated thin film capacitors with optimized temperature characteristics |
| JP2014033241A (en) * | 2010-06-24 | 2014-02-20 | Tdk Corp | Chip thermister and manufacturing method therefor |
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