JPH04369266A - Ccd solid-state image sensor - Google Patents

Abstract

PURPOSE:To avoid a phenomenon of overflowing signal charge in a horizontal register, to prevent a decrease in a dynamic range of a photodetector having knee characteristics, and to suppress deterioration of quality of an image on a monitor screen. CONSTITUTION:An overflow drain region 10 by an N-type impurity diffused region is formed at an upper stage side from a narrow width part of particularly a second vertical transfer electrode 8 of a space Sp between vertical registers 2, and an overflow control gate 11 of an offset OS formed between one end 10a of the region 10 and one end 8a of the electrode 8, is formed. An overflow control gate electrode 12 is formed on an overflowing part 5 made of the region 10 and the gate 11, a control potential to be applied to the electrode 12 is controlled to regulate a maximum handling charge amount of a final stage of the register 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CCD solid-state image pickup device, and more particularly to a CCD solid-state image pickup device using, for example, an interline transfer method and having a vertical register and a horizontal register made up of CCDs.

0002

[Prior Art] Conventional CC of interline type, for example.
As shown in FIG. 5, in the D solid-state image sensor, light receiving sections 21 made up of photodiodes are arranged in a matrix in the horizontal and vertical directions, and the light receiving sections 21 are arranged on a common vertical line.
1, and a horizontal register 23 that is commonly provided for each vertical register 22.

[0003] During the charge accumulation period, the light receiving section 21
The signal charges accumulated in the last stage of the vertical register 22 are read out to the vertical register 22 in the next read period, and the signal charges are transferred row by row in the horizontal blanking period, and the signal charges accumulated in the final stage of the vertical register 22 are read out to the vertical register 22. Transfer to register 23. Then, the next horizontal output period (TV 1
(corresponding to the horizontal scanning period), the horizontal register 23
The above signal charges are sequentially transferred to the output section 24 side, and the output section 24
The operation of extracting the image signal S from the image signal S is performed.

0004

[Problems to be Solved by the Invention] However, in the conventional CCD solid-state image pickup device, since the signal charge from the vertical register 22 is directly transferred to the horizontal register 23, for example, the maximum handling of the horizontal register 23 is If the amount of charge is smaller than the maximum amount of charge that can be handled by the vertical register 22, when the signal charge read out from the light receiving section 21 just before the maximum amount of charge that can be handled by the vertical register 22 is transferred to the horizontal register 23, the horizontal register 22 23, a phenomenon occurs in which signal charges overflow. Horizontal register 23
If the signal charge overflows, the image quality will deteriorate on the monitor screen, with the image appearing to flow to the right at the area where the high-intensity light source is being imaged.

[0005] Further, the photoelectric conversion characteristics of the light receiving section 21 include the structure of the light receiving section 21, which causes a difference in the readout signal.
There is a phenomenon called the knee characteristic. If there is a knee characteristic,
The amount of signal charge read out from the light receiving section 21 has linear characteristics with respect to the amount of light when the amount of light is small, but becomes nonlinear when the amount of light exceeds a certain amount. This nonlinear characteristic portion is an area that cannot be used as an image signal.

Incidentally, since it is necessary that the vertical register 22 and the horizontal register 23 do not overflow even with signal charges in this region of nonlinear characteristics, the light receiving section 21 is adjusted in accordance with the amount of charge handled by the horizontal register 23. The linear region of the photoelectric conversion characteristics must be set low. This leads to a reduction in the dynamic range of the light receiving section 21, resulting in extremely unstable characteristics.

By the way, some conventional CCD solid-state imaging devices have an overflow drain region formed at the last stage of the vertical register 22, as shown in Japanese Patent Laid-Open No. 63-105578, for example. In this example, before the signal charges are transferred to the horizontal register 23, the vertical register 23 is
2, false signal charges such as smear that exist in the overflow drain region are accumulated in the overflow drain region, and excess charges (false signal charges) that exceed the amount of charge handled in the region are absorbed into the substrate by the vertical overflow drain structure and swept away. be.

However, in this example, all false signal charges such as smear are simply swept out before signal charge transfer, so during actual signal charge transfer, this overflow drain region simply drains the charge. It only constitutes a transfer stage. In other words, when the above operation is performed when transferring signal charges, the signal charges themselves are absorbed by the substrate,
This is because a disadvantage arises in that the signal charge cannot be transferred to the horizontal register. Therefore, even in this example, the above-mentioned overflow phenomenon of signal charges on the horizontal register 23 and a reduction in the dynamic range of the light receiving section 21 having knee characteristics are unavoidable.

The present invention has been made in view of the above-mentioned problems, and its purpose is to reduce the amount of charge that can be handled by the horizontal register even when the maximum amount of charge that can be handled by the horizontal register is smaller than the maximum amount of charge that can be handled by the vertical register. A CCD solid-state image sensor that can prevent the phenomenon of signal charges overflowing in registers, prevent a decrease in the dynamic range of a light receiving section with knee characteristics, and prevent deterioration of image quality on a monitor screen. Our goal is to provide the following.

0010

[Means for Solving the Problems] The present invention provides a CCD having a vertical register 2 and a horizontal register 3 configured with a CCD.
In the solid-state image sensor, an overflow control gate 11 to which a predetermined potential Vc is applied to the final stage of the vertical register 2, and the overflow control gate 1
An overflow portion 5 is formed and constituted by an overflow drain region 10 from which a predetermined amount or more of signal charges from the vertical register 2 is swept out by applying the predetermined potential Vc to the vertical register 1. .

[0011]

[Operation] According to the configuration of the present invention described above, the vertical register 2
Since the overflow control gate 11 and the overflow drain region 10 are present in the final stage of the overflow control gate 11, the height of the potential barrier 11P under the overflow control gate 11 can be adjusted by controlling the potential Vc applied to the overflow control gate 11. Thus, for example, the maximum amount of charge handled by the last stage of the vertical register 2 can be made equal to the maximum amount of charge handled by the horizontal register 3. Therefore, for example, vertical register 2
Even if the maximum amount of charge handled by the horizontal register 3 is smaller than the maximum amount of charge handled by the horizontal register 3, it is possible to prevent the phenomenon of signal charges overflowing in the horizontal register 3.

Furthermore, among the signal charges from the light receiving section 1 having the knee characteristic, the signal charges in the nonlinear characteristic region can be swept out to the overflow drain region 10. There is no need to reduce the size according to the amount of charge. Therefore, even if the dynamic range of the horizontal register 3 is small, the dynamic range of the horizontal register 3 can be used efficiently.

Furthermore, since there is no need to provide a dedicated overflow drain region for sweeping out false signal charges such as smear, the degree of freedom in design is increased.

[0014]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 4. FIG. 1 is a schematic plan view showing the configuration of a CCD solid-state image sensor according to this embodiment.

In this CCD solid-state image sensing device, light receiving sections 1 composed of photodiodes are arranged in a matrix in the horizontal and vertical directions, and the light receiving sections 1 are arranged on a common vertical line.
A vertical register 2 is provided in common for each vertical register 2, and a horizontal register 3 is provided in common for each vertical register 2.

Then, the signal charge accumulated in the light receiving section 1 during the charge accumulation period is read out to the vertical register 2 during the next readout period, and during the horizontal blanking period,
The signal charges are transferred row by row, and the signal charges accumulated in the final stage of the vertical register 2 are transferred to the horizontal register 3. Then, in the next horizontal output period (corresponding to one horizontal scanning period of a television), the signal charges on the horizontal register 3 are sequentially transferred to the output section 4 side, and in this output section 4,
The signal charge is subjected to charge-voltage conversion and taken out as a voltage signal (imaging signal) S from the output terminal φout.

In this example, an overflow section 5, which will be described later, is provided at the final stage of the vertical register 2.

Next, the specific structure of the overflow section 5 will be explained with reference to FIGS. 2 to 4.

FIG. 2 is an enlarged plan view showing the vicinity of the final stage of the vertical register 2. As shown in FIG. In this FIG. 2, the diagonally shaded area a
The part indicated by the dotted line is the vertical register 2, and the part indicated by the diagonally shaded area b is the horizontal register 3. In particular, vertical register 2
is wide at its final stage. still,
The portion indicated by width CS is the channel stopper region 6.

Further, on the vertical register 2, there are first, second and third vertical transfer electrodes 7, 8 for charge transfer in the horizontal direction.
and 9 are formed, among these vertical transfer electrodes 7, 8 and 9, the first and third vertical transfer electrodes 7 and 9 are formed in a band shape, and the second vertical transfer electrode 8 is formed on the vertical register 2. The width is wide, and the width is narrow in areas other than those above the vertical register 2. In the figure, the first vertical transfer electrode 7 is indicated by a solid line, the second vertical transfer electrode 8 is indicated by a broken line,
The third vertical transfer electrode 9 is indicated by a two-dot chain line.

In this example, vertical register 2
In the space Sp between them, an overflow drain region 10 made of an N-type impurity diffusion region is formed (indicated by a broken line frame), particularly on the upper side of the narrowed portion of the second vertical transfer electrode 8. This region 10 is formed to overlap the wide part of the vertical register 2, and is between the vertical register side end 10a of this region 10 and the overflow drain region side end 8a of the wide part of the second vertical transfer electrode 8. An offset is formed with a width OS. This offset OS portion constitutes an overflow control gate 11, and this overflow control gate 11 and the overflow drain region 10 constitute an overflow portion 5.

[0022] Then, an overflow control gate electrode 12 (indicated by a dashed line) extending horizontally is formed on a region including this overflow portion 5. At this time, the first and third vertical transfer electrodes 7 and 9 are formed from the first polycrystalline silicon layer, and the second vertical transfer electrode 8 is formed from the second polycrystalline silicon layer. , an overflow control gate electrode 12 is formed of a third polycrystalline silicon layer.

A cross section of the overflow portion 5 is shown in FIG. 3A and 3B are cross-sectional views taken along the line AA and line BB in FIG. 2, respectively. In these cross-sectional views,
Although the silicon substrate 13 is shown as N-type, there is no problem even if a P-type silicon substrate is used and the N-type and P-type in other impurity diffusion regions, such as the vertical resistor 2 or the channel stopper region 6, are replaced. . In addition, in these cross-sectional views, C
Although the CD is shown as a buried channel type CCD, it is also a surface channel type CCD that does not use impurities in the vertical register 2.
The same thing can be said when using a CD. However, the following description of the forming method in this example will be based on these cross-sectional views.

First, a P-type well region 14 and an N-type vertical resistor 2 are formed on an N-type silicon substrate 13. This P-type well region 14 is for compressing the smear. Next, a channel stopper region 6 made of a P-type impurity diffusion region is formed next to the vertical register 2 . Thereafter, first and third vertical transfer electrodes 7 and 9 are formed using a first polycrystalline silicon layer with a gate insulating film 15 interposed therebetween, and then a second polycrystalline silicon layer is formed with an interlayer insulating film 16 interposed therebetween. The second vertical transfer electrode 8 is formed by the following method.

Thereafter, N-type impurity ions are implanted into the portion indicated by the broken line frame in FIG. 2 to form the overflow drain region 1.
0, this overflow drain region 10
An overflow control gate electrode 12 made of a third polycrystalline silicon layer is formed thereon via a gate insulating film 15 to obtain a CCD solid-state imaging device according to this example. Note that an interlayer insulating film 17 is interposed between the overflow control gate electrode 12 and the second vertical transfer electrode 8. Further, an overflow control gate 11 is configured in a portion indicated by a width (offset) OS. Further, in FIG. 3, reference numeral 18 indicates a horizontal transfer electrode formed on the horizontal register 3.

Here, the impurity concentrations of the vertical register 2, the P-type well region 14, and the channel stopper region 6 are set to normally used impurity concentrations. Further, the impurity concentration of the overflow drain region 10 is set to such an extent that the surface thereof is depleted by the potential applied to the overflow control gate electrode 12. Note that the overflow drain region 10
The ion implantation of N-type impurities for forming may be performed before forming the second vertical transfer electrode 8.

Next, the operation of the overflow section 5 according to this example will be explained with reference to the potential diagram shown in FIG.

First, as shown in FIG. 4A, the control potential V applied to the overflow control gate electrode 12 is
c is adjusted to control the height of the potential barrier 11P under the overflow control gate 11 configured by the offset OS shown in FIGS. 2 and 3. That is, in this example, the maximum handling charge amount of the signal charges accumulated under the second vertical transfer electrode 8 in the final stage of the vertical register 2 is set to be slightly smaller than the maximum handling charge amount of the horizontal register 3 (for example, (approximately 90% of the maximum charge amount handled by the horizontal register 3), the height of the potential barrier 11P below the overflow control gate 11 is adjusted.

At this time, overflow drain region 1
0, the impurity concentration is sufficiently high, so the substrate potential V
Fixed to sub. Therefore, the upper vertical register 2
When a signal charge whose amount is larger than the maximum amount of charge handled by the horizontal register 3 is transferred to the final stage of the vertical register 2, at this final stage, the signal charge becomes 90% of the maximum amount of charge handled by the horizontal register 3. The cut signal charge is swept out over the overflow control gate 11 into the overflow drain region 10, and further flows into the substrate 13 through the overflow drain region 10, as shown by the arrow in FIG. 3A. That is, an overflow operation of signal charges is performed in the overflow section 5.

In FIGS. 4A and 4B, among the potentials formed under the second vertical transfer electrode 8, the potential Pa indicated by a solid line is a state in which no signal charge is accumulated under the second vertical transfer electrode 8. The potential Pb shown by a broken line indicates that a small amount of signal charge is accumulated under the second vertical transfer electrode 8, and the potential Pc shown by a dashed dotted line indicates that the signal charge overflows to a certain amount of signal charge. (90% of the maximum charge amount handled by horizontal register 3)
%). Also, V1, V2
and V3 indicate drive pulse potentials applied to the first, second and third vertical transfer electrodes, respectively, and H indicates a drive pulse potential applied to the horizontal transfer electrodes.

Therefore, signal charges of 90% or more of the maximum amount of charge handled by the horizontal register 3 are not transferred, and the phenomenon of signal charges overflowing in the horizontal register 3 is avoided.

As described above, according to this example, for example, the horizontal register 3
Even when the maximum amount of charge that can be handled is small, it is possible to prevent the phenomenon of signal charges overflowing on the horizontal register 3, and it is possible to suppress deterioration of image quality due to overflow of signal charges on the horizontal register 3. .

Furthermore, due to the structure of the light receiving section 1 shown in FIG.
When the photoelectric conversion characteristic has a knee characteristic, the control potential V applied to the overflow control gate electrode 12
By adjusting c, the signal charges in the nonlinear characteristic region can be discarded to the substrate 13 via the overflow drain region 10, so that only the signal charges in the linear characteristic region are transferred to the horizontal register 3. The characteristics of the CCD solid-state image sensor can be stabilized. Moreover, the light receiving section 1
Since there is no need to reduce the dynamic range of the horizontal register 3 in accordance with the maximum amount of charge handled by the horizontal register 3, the dynamic range of the horizontal register 3 can be used efficiently even if the dynamic range of the horizontal register 3 is small.

Furthermore, since there is no need to provide a dedicated overflow drain region for sweeping out false signal charges such as smear, the degree of freedom in design is increased.

In the above embodiment, when the signal charge is accumulated under the second vertical transfer electrode 8, it is caused to overflow, but in addition, the second and third vertical transfer electrodes 8
It is also possible to overflow when signal charges are accumulated under 9 and 9.

Furthermore, in the above embodiment, the overflow drain region 10 is formed so as to overlap the wide portion of the vertical register 2, but of course, the overflow drain region 10 is formed to overlap the wide portion of the vertical register 2. Alternatively, the width of the offset OS may be expanded by forming the offset OS.

[0037]

Effects of the Invention According to the CCD solid-state image sensor according to the present invention, even when the maximum amount of charge handled by the horizontal register is smaller than the maximum amount of charge handled by the vertical register, there is a phenomenon in which signal charges overflow in the horizontal register. In addition, it is possible to prevent a decrease in the dynamic range of a light receiving section having knee characteristics, and it is also possible to prevent deterioration of image quality on a monitor screen.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view showing the configuration of a CCD solid-state image sensor according to this embodiment.

FIG. 2 is an enlarged plan view showing the vicinity of the final stage of the vertical register of the CCD solid-state image sensor according to the present embodiment.

FIG. 3A is a sectional view taken along line A-A in FIG. 2; B is a sectional view taken along line B-B in FIG. 2.

FIG. 4A is a potential diagram in FIG. 3A. B is
Potential diagram in FIG. 3B.

FIG. 5 is a schematic plan view showing the configuration of a conventional CCD solid-state image sensor.

[Explanation of symbols]

1 Light receiving section 2 Vertical register 3 Horizontal register 4 Output section 5 Overflow section 6 Channel stopper region 7 First vertical transfer electrode 8 Second vertical transfer electrode 9 Third vertical transfer electrode 10 Overflow drain region 11 Overflow control gate 12 Overflow control gate electrode 13 Silicon substrate

Claims (1)

[Claims] 1. A CCD solid-state image sensing device having a vertical register and a horizontal register configured with a CCD, an overflow control gate to which a predetermined potential is applied to the final stage of the vertical register, and an overflow control gate to which a predetermined potential is applied to the overflow control gate. A CCD solid-state image pickup device, characterized in that an overflow region is formed, and an overflow region is formed in which a predetermined amount or more of signal charges from a vertical register is swept out by applying a potential of .