JPH04369029A - System for minimizing transmission delay time - Google Patents

Abstract

PURPOSE:To set up the transmission delay time of a completed system to a minimum value in this transmission delay time minimizing system for a device for executing stuff multiplication/separation of an asynchronous signal. CONSTITUTION:The transmission delay time minimizing system is provided with a writing address counter part 1 for executing variable counting operation by the 1st selection signal, a writing decoding part 2 for outputting a write enable signal to a memory part 6 by the 1st selection signal, a reading address counter part 3 for executing various counting operation based upon a stuff request signal and the 1st selection signal, a reading decoder part 4 for outputting a reading enable signal to the memory part 6 by the 1st selection signal, and a phase comparator 5 for comparing the phase of one of read enable signals with that of a write enable signal based upon the 2nd selection signal and constituted so as to set up the optimum of the memory part 6.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for minimizing transmission delay time in an apparatus for stuff multiplexing/separating certain asynchronous signals.

0002

2. Description of the Related Art A transmission delay time system for an asynchronous signal will be explained below using the circuit shown in FIG. In FIG. 5, 11 and 12 are writing side circuits, 11 is a first counter,
12 is a first decoder. Note that 13 and 14 are read-out side circuits, 13 is a second counter, and 14 is a second decoder. Further, 15 is a phase comparator, and 16 is a memory section.

In FIG. 5, a first counter 11 constituting, for example, an 8-bit counter performs a fixed count in response to a write clock, and outputs a count address value (Q0 to Q15) consisting of, for example, 8 bits. The first decoder 12 receives this count address value (Q0 to Q15
) is converted into 16 fixed write enable signals (WEN0 to WEN15) in which one pulse exists between 16 write clocks, and these signals (WEN0 to WEN15) are applied to the memory section 6. .

Similarly, the second counter 13 and the second decoder 14 operate in the same way as the first counter 11 and the first decoder 12, and are enabled and controlled by the stuffing request signal from the phase comparator 15. A fixed count address value (Q0 to Q15) is output by the second decoder 1.
4 decodes the count address value (Q0 to Q15) to convert it into 16 fixed read enable signals (REN0 to REN15) in which one pulse exists between 16 read clocks, and outputs the signal. (REN
0 to REN15) are added to the memory section 16.

The memory section 16 stores write data using the above fixed write enable signals (WEN0 to WEN15), and stores write data using the fixed read enable signals (WEN0 to WEN15).
The write data stored in REN0 to REN15) is read out.

The phase comparator 15 compares the phases of, for example, the write enable signal (WEN0) outputted by the first decoder 12 and the read enable signal (REN0) outputted from the second decoder 14, and converts the stuff request signal to the first one at a timely manner. 2 counter 13.

[0007] The capacity of the memory section 16 in the above-described conventional system is determined by, for example, the write enable signal (WEN0).
It is determined by the phase difference (transmission delay time) between the read enable signal (REN0) and the read enable signal (REN0).

The method for determining the capacity of the memory section 16 in the conventional stuff multiplexing/demultiplexing device is as follows: - Deviation due to insertion of service signals (frame synchronization signal, stuffing control output, etc.) - Deviation due to insertion of stuffing signal - Stuffing request Calculate the jitter (jitter waiting time) due to the delay time that occurs from when the data is sent until the stuffing is performed, the fluctuation range of the stuffing rate, the jitter of the low-order group transmission path, etc., and calculate the sum of them, and add a margin to this sum. The memory capacity was also increased.

[0009] However, this calculation method is rough, and since a margin is provided, this memory capacity does not minimize the transmission delay time of the system.

0010

[Problem to be Solved by the Invention] Therefore, in the conventional method, if various types of jitter do not occur as calculated when the system is completed, the memory capacity cannot be arbitrarily varied; In addition, even if various jitters occur as calculated, the memory capacity is determined with a margin.
There is a problem in that the transmission delay time of the system is not minimized.

An object of the present invention is to enable the transmission delay time of the system to be set to the minimum when the system is completed.

0012

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an apparatus for stuff multiplexing/demultiplexing of asynchronous data, which includes a memory section 6 for writing and reading out the asynchronous data, and a first memory section 6 for writing and reading out the asynchronous data. A write address counter section 1 whose count-up value can be changed by applying a selection signal, and an output of the write address counter section 1 is decoded by adding the first selection signal, and a write operation is performed in the memory section 6. a write decoder section 2 that outputs an enable signal; a read address counter section 3 whose enable control is performed by a stuff request signal and whose count-up value can be changed by adding a first selection signal; A read decoder section 4 decodes the output of the read address counter section 3 by adding a selection signal to output a read enable signal for the memory section 6; A phase comparison section 5 is provided which selects one of the enable signals and compares the phase of the selection result with the write enable signal, so that the optimum capacity of the memory section 6 can be determined and the transmission delay of the system can be reduced. Configure to minimize.

[0013]

[Operation] As shown in FIG. 1, the present invention includes selectors in the write address counter section 1 and the read address counter section 3 that output count address values on the write or read side, respectively, and the first selection signal is set to the write address. The count output is made variable by adding it to the counter section 1 and the read address counter section 3, and the count result is added to the write decoder 2 and the read decoder section 4 for decoding, thereby making the write enable variable for the memory section 6. I am trying to get a signal and a read enable signal. Furthermore, by providing the phase comparison section 5 with a selector, the comparison timing of the read enable signal is changed by the second selection signal, and the phase comparison position for writing and reading in the memory section 6 can be varied. .

Therefore, the capacity of the memory section 6 can be determined optimally for the system by setting the first selection signal and the second selection signal, and the transmission delay time can be minimized.

[0015]

Embodiments Hereinafter, embodiments of the present invention will be explained with reference to FIGS. 2 to 4. FIG. 2 is a circuit diagram, FIG. 3 shows the operation on the writing side, and FIG. 4 shows the operation of the phase comparator.

In FIG. 2, 1 and 2 are circuits on the write side, 1 is a write address counter section having a first selector 1a and a first counter 1b, and 2 is a second selector 2a.
and a first decoder 2b.

Note that 3 and 4 are readout side circuits;
4 is a read address counter section having a third selector 3a and a second counter 3b, and 4 is a read decoder section having a fourth selector 4a and a second decoder 4b.

Further, 5 is a fifth selector 5a and a phase comparator 5.
b is a phase comparator section, and 6 is a memory section. The first counter 1b and the second counter 3b are constituted by, for example, an 8-bit Johnson counter having a function of changing the count value by external control.

In FIG. 2, when the first select signal (TST1, TST2) is input, the first select signal (TST1, TST2) is input.
The selector 1a applies control corresponding to the set of the signals TST1 and TST2 to the first counter 1b. The first counter 1b constituting the 8-bit Johnson counter has a first
A write clock counter value is determined in accordance with the control output from the selector 1a, and, for example, a count address value (Q0 to Q15) on the write side is output.

The write decoder section 2 is composed of a circuit that decodes, for example, the count address value (Q0 to Q15) on the write side from the write address counter section 1, and decodes the select signal (TST1) input to the second selector 2a.
, TST2), the write-side count address value (Q0 ~
Write enable signal (W
EN0 to WEN15) are output and added to the memory section 6.

That is, as shown in FIG. 3, for example, TST
1=0, TST2=0, the first counter 1b operates as an 8-bit Johnson counter, and the first decoder 2
16 write enable signals (WEN0 to WEN0) with one pulse between 16 write clocks from
EN15) is output and added to the memory section 6.

[0022] Furthermore, if TST1=1 and TST2=1, then
The first counter 1b operates as a 5-bit Johnson counter, and outputs 10 write enable signals (WEN0 to WEN9) with one pulse between 10 write clocks from the first decoder 2b and adds them to the memory section 6. .

As described above, the number of enable signals is varied depending on the set of select signals (TST1, TST2). Similarly to the above, the read address counter section 3 and the read decoder section 4 operate almost the same as the write address counter section 1 and the write decoder section 2. For example, if TST1=0 and TST2=0, 2 counter 3b operates as an 8-bit Johnson counter,
The read side count address value (Q0 ~
Q15), and the second decoder 4b outputs 16 read enable signals (REN0 to REN15) in which one pulse is output during 16 read clocks and adds them to the memory section 6. Note that, similar to the write enable signal, the number of read enable signals depends on the select signal (
TST1, TST2).

The memory section 6 stores write data in response to the write enable signal, and reads out the stored write data in response to the read enable signal. The phase comparator 5 uses, for example, a write enable signal (WEN0) output from the first decoder 2b and a read enable signal (REN0 to REN0) output from the second decoder 4b.
REN15) and sends out a stuffing request signal from the phase comparator 5b, as shown in FIG. Three inputs to 5a: TST3, TST4, and TST5. By setting the timing select signal, WEN0 and R
The phase comparison timing with each of EN0 to REN7 is changed, and the writing and reading phases of the memory section 6 are made variable to prevent data slip of read data.

[0025]

[Effects of the Invention] As is clear from the above explanation, according to the present invention, by setting a plurality of select signals,
The memory capacity and phase comparison can be varied, the transmission time of the system can be minimized when the system is completed, and the effect is that it greatly contributes to improving the performance of the stuff multiplexing/demultiplexing device.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a diagram showing an embodiment of the circuit of the present invention.

FIG. 3 is a diagram showing the write side operation of the circuit of the present invention.

FIG. 4 is a diagram showing the operation of the phase comparator section of the circuit of the present invention.

FIG. 5 is a diagram showing an example of a conventional circuit.

[Explanation of symbols]

1 is the write address counter section 2 is the write decoder section 3 is the read address counter section 4 is the reading decoder section 5 is a phase comparison section 6 is the memory part

Claims (1)

[Claims] [Claim 1] A device for stuff multiplexing/separating asynchronous data, including a memory unit (6) for writing and reading the asynchronous data, and a count-up value that can be changed by adding a first selection signal. and the write address counter section (1) by adding the first selection signal.
a write decoder section (6) that decodes the output of the memory section (6) and outputs a write enable signal for the memory section (6);
2) and a read address counter section (3) whose enable control is performed by the stuff request signal and whose count-up value can be changed by adding the first selection signal.
and a read decoder section (4) that decodes the output of the read address counter section (3) by applying the first selection signal and outputs a read enable signal for the memory section (6). , a phase comparator (5) that selects one of the read enable signals using the second selection signal and compares the phase of the selection result with the write enable signal; A method for minimizing transmission delay time, which is characterized by minimizing the transmission delay time of the system by determining the optimal capacity.