JPH0436860B2 - - Google Patents

Info

Publication number
JPH0436860B2
JPH0436860B2 JP57055024A JP5502482A JPH0436860B2 JP H0436860 B2 JPH0436860 B2 JP H0436860B2 JP 57055024 A JP57055024 A JP 57055024A JP 5502482 A JP5502482 A JP 5502482A JP H0436860 B2 JPH0436860 B2 JP H0436860B2
Authority
JP
Japan
Prior art keywords
phase
signal
input
sine wave
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57055024A
Other languages
Japanese (ja)
Other versions
JPS58171967A (en
Inventor
Toshuki Iwazawa
Hiroyuki Naito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP5502482A priority Critical patent/JPS58171967A/en
Publication of JPS58171967A publication Critical patent/JPS58171967A/en
Publication of JPH0436860B2 publication Critical patent/JPH0436860B2/ja
Granted legal-status Critical Current

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04541Specific driving circuit
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B41PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
    • B41JTYPEWRITERS; SELECTIVE PRINTING MECHANISMS, i.e. MECHANISMS PRINTING OTHERWISE THAN FROM A FORME; CORRECTION OF TYPOGRAPHICAL ERRORS
    • B41J2/00Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed
    • B41J2/005Typewriters or selective printing mechanisms characterised by the printing or marking process for which they are designed characterised by bringing liquid or particles selectively into contact with a printing material
    • B41J2/01Ink jet
    • B41J2/015Ink jet characterised by the jet generation process
    • B41J2/04Ink jet characterised by the jet generation process generating single droplets or particles on demand
    • B41J2/045Ink jet characterised by the jet generation process generating single droplets or particles on demand by pressure, e.g. electromechanical transducers
    • B41J2/04501Control methods or devices therefor, e.g. driver circuits, control circuits
    • B41J2/04586Control methods or devices therefor, e.g. driver circuits, control circuits controlling heads of a type not covered by groups B41J2/04575 - B41J2/04585, or of an undefined type

Landscapes

  • Particle Formation And Scattering Control In Inkjet Printers (AREA)

Description

【発明の詳細な説明】 本発明はインクジエツトヘツド等のプリンター
ヘツドの駆動回路に関するものであり、同相信号
と逆相信号を加えることによつて従来の半分の電
圧で、ヘツドを駆動できる回路を提供するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a drive circuit for a printer head such as an inkjet head, and is a circuit that can drive the head with half the voltage of a conventional printer by adding an in-phase signal and a reverse-phase signal. It provides:

従来のヘツド駆動回路では、第1図のように、
駆動信号を、+V0,−V0を印加された大電圧増幅
器1に入力し、その出力を、回路のアースを基準
としたヘツド2に印加していた。この場合、V0
が100〜200Vの高圧である大電圧増幅器1として
は特殊なアンプが必要となり、コスト的に不利で
あつた。またV0のレギユレータも大きくなり、
スペース的・熱的・コスト的にも問題となつてい
た。
In the conventional head drive circuit, as shown in Figure 1,
A drive signal was input to a large voltage amplifier 1 to which +V 0 and -V 0 were applied, and its output was applied to a head 2 with respect to the ground of the circuit. In this case, V 0
Since the high voltage amplifier 1 has a high voltage of 100 to 200 V, a special amplifier is required, which is disadvantageous in terms of cost. Also, the regulator of V 0 becomes larger,
There were also problems in terms of space, heat, and cost.

本発明は、かかる問題点を解決すべくなされた
ものである。以下実施例にもとづき本発明を詳細
に説明する。
The present invention has been made to solve these problems. The present invention will be described in detail below based on Examples.

第2図は本発明によるプリンターヘツド駆動回
路の一実施例を示すブロツク図、第3図は第2図
の各部の信号波形図である。この実施例はヘツド
に加えられる駆動信号が第3図Aに示すように間
欠的な信号である場合の実施例である。このよう
な間欠的な信号はキヤリア信号自体を断続させれ
ば容易に作ることが出来る。第3図Aで示される
ような波形の信号を+V0/2,−V0/2の電圧を印加
している増幅器3,4にそれぞれ入力する。増幅
器3には 出力と入力が同期となるように、増幅
器4には 逆相となるように入力する。
FIG. 2 is a block diagram showing an embodiment of the printer head driving circuit according to the present invention, and FIG. 3 is a signal waveform diagram of each part of FIG. This embodiment is an embodiment in which the drive signal applied to the head is an intermittent signal as shown in FIG. 3A. Such an intermittent signal can be easily created by intermittent the carrier signal itself. A signal having a waveform as shown in FIG. 3A is input to amplifiers 3 and 4 applying voltages of +V 0/2 and -V 0/2 , respectively. The output and input are input to amplifier 3 so that they are synchronized, and the input to amplifier 4 is input so that they are in opposite phase.

それ故、ヘツド2の入力端子B,Cに入力され
る電圧波形は、第3図B,Cのように最大振巾±
V0/2まで振られ、互いに逆相となる。よつて、
ヘツド入力端子B,C間に印加される電圧は、入
力端子Bに印加された電圧から、入力端子Cに印
加された電圧を減じたB−Cとなり、第3図Dの
ように、最大振幅±V0の波形となる。このよう
に駆動信号としての入力波形を従来の半分の電圧
が印加された同相、逆相出力用の増幅器3,4に
それぞれ印加することによつて、ヘツド2には実
質的にピークが±V0の電圧波形を加えることが
できる。
Therefore, the voltage waveforms input to the input terminals B and C of head 2 have a maximum amplitude ±
They are swung up to V 0 /2 and have opposite phases to each other. Then,
The voltage applied between head input terminals B and C is B-C, which is the voltage applied to input terminal B minus the voltage applied to input terminal C, and the maximum amplitude is as shown in Figure 3D. The waveform is ±V 0 . In this way, by applying the input waveform as a drive signal to the in-phase and anti-phase output amplifiers 3 and 4, to which half the voltage of the conventional one is applied, the head 2 has a substantially peak of ±V. 0 voltage waveform can be added.

この実施例からわかるように、本発明において
は増幅器3,4に加えられる電圧が従来の1/2で
よいので、増幅器3,4がとり扱いやすく、また
安価に作ることができる。
As can be seen from this embodiment, in the present invention, the voltage applied to the amplifiers 3 and 4 can be reduced to 1/2 of the conventional voltage, so the amplifiers 3 and 4 are easy to handle and can be manufactured at low cost.

第4図は本発明の他の一実施例を示す。この実
施例は、ヘツドの駆動を第2図の場合のようにキ
ヤリアの断続で制御するのではなく、キヤリアは
常に出したままにしておき、2つの増幅器出力を
ヘツドを駆動させないときは同相になるように、
駆動したいときは逆相になるように印加するもの
である。第4図の各部の波形を示す第5図ととも
に動作を説明する。
FIG. 4 shows another embodiment of the invention. In this embodiment, the drive of the head is not controlled by intermittent carriers as in the case of Fig. 2, but the carrier is always left on, and the two amplifier outputs are in phase when the head is not being driven. So that
When driving is desired, the voltage is applied so that the phase is reversed. The operation will be explained with reference to FIG. 5 showing waveforms of each part in FIG. 4.

第4図において、発振器5より出力される発振
信号(第5図Aの波形)は、±V0/2を印加した
増幅器13の同相入力端子に入力する。又、同時
にアナログスイツチ回路10,11に入力する。
一方、第5図Bで示される制御信号をアナログス
イツチ回路11のゲートに入力し、同時にこの制
御信号をインバータ9で反転させた信号をアナロ
グスイツチ回路10のゲートに入力すると、アナ
ログスイツチ回路10,11の出力波形は夫々第
5図のC,Dとなる。ここで、±V0/2を印加し
た増幅器12の同相入力端子に、アナログスイツ
チ回路10の出力信号を、逆相入力端子にアナロ
グスイツチ回路11の出力信号を入力すれば、増
幅器12の出力信号は、第5図Eのように、制御
信号Bが“0”のときは同相波形、“1”のとき
は逆相波形となる。
In FIG. 4, the oscillation signal (waveform in FIG. 5A) output from the oscillator 5 is input to the in-phase input terminal of the amplifier 13 to which ±V 0 /2 is applied. The signal is also input to analog switch circuits 10 and 11 at the same time.
On the other hand, if the control signal shown in FIG. The output waveforms of 11 are C and D in FIG. 5, respectively. Here, if the output signal of the analog switch circuit 10 is input to the in-phase input terminal of the amplifier 12 to which ±V 0 /2 is applied, and the output signal of the analog switch circuit 11 is input to the negative-phase input terminal, the output signal of the amplifier 12 As shown in FIG. 5E, when the control signal B is "0", it is an in-phase waveform, and when it is "1", it is an anti-phase waveform.

増幅器13の出力信号Fは、第5図Fのよう
に、発振信号Aと同相で最大振巾±V0/2であ
るから、ヘツド8の入力端子F,Eに印加される
電圧は、入力端子Eに印加される電圧から、入力
端子Fに印加される電圧を減じることによつて得
られるので、第5図G=F−Eのような±V0
駆動波形となる。
As shown in FIG. 5F, the output signal F of the amplifier 13 is in phase with the oscillation signal A and has a maximum amplitude of ±V 0 /2, so the voltage applied to the input terminals F and E of the head 8 is This is obtained by subtracting the voltage applied to the input terminal F from the voltage applied to the terminal E, resulting in a drive waveform of ±V 0 as shown in FIG. 5, G=FE.

今、発振信号Aを正弦波とすると、第4図E端
子に印加される電圧は、 V0/2sin ωt:(制御信号Eが“0”のとき) V0/2sin(ωt+π):(制御信号Eが“1”のと き) となり、G端子に印加される電圧は、V0/2sin ωt であるから、 制御信号Eが“0”のとき:VF-E=0 “1”のとき:VF-E=V0/2sin ωt −V0/2sin(ωt+π) =V0sin ωt となり、低電圧で駆動する増幅器を使用すること
によつて高電圧駆動の増幅器を使用した場合と同
じ駆動波形を得ることができる。
Now, assuming that the oscillation signal A is a sine wave, the voltage applied to the E terminal in Fig. 4 is V 0 /2sin ωt: (when the control signal E is “0”) V 0 /2sin (ωt + π): (control When the signal E is "1"), the voltage applied to the G terminal is V 0 /2sin ωt, so when the control signal E is "0": V FE = 0 When "1": V FE = V 0 /2sin ωt −V 0 /2sin(ωt+π) =V 0 sin ωt, and by using an amplifier driven at a low voltage, the same drive waveform as when using a high voltage driven amplifier can be obtained. be able to.

以上のように、本発明はプリンターヘツドの駆
動増幅器を2つに分割し、2つの増幅器の出力電
圧の差をプリンターヘツドに印加するようにした
プリンターヘツド駆動回路であり、低電圧用部品
が使用できるので増幅器のとり扱いが容易であ
り、安価となる。また、増幅器に加える電圧が従
来の1/2の電圧でよいので電源回路が小さく廉価
になる。
As described above, the present invention is a printer head drive circuit that divides the printer head drive amplifier into two and applies the difference between the output voltages of the two amplifiers to the printer head, and uses low voltage components. This makes the amplifier easy to handle and inexpensive. Additionally, since the voltage applied to the amplifier can be half of the voltage of the conventional one, the power supply circuit becomes smaller and cheaper.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のプリンターヘツド駆動回路を示
すブロツク図、第2図は本発明によるプリンター
ヘツド駆動回路の実施例のブロツク図、第3図は
第2図のブロツク図の要部波形図、第4図は本発
明によるプリンターヘツド駆動回路の実施例のブ
ロツク図、第5図は第4図のブロツク図の要部波
形図である。 2,8……プリンターヘツド、3,4,12,
13……増幅器、5……発振器、9……インバー
タ、10,11……アナログスイツチ。
FIG. 1 is a block diagram showing a conventional printer head drive circuit, FIG. 2 is a block diagram of an embodiment of the printer head drive circuit according to the present invention, and FIG. 3 is a waveform diagram of the main part of the block diagram of FIG. FIG. 4 is a block diagram of an embodiment of the printer head driving circuit according to the present invention, and FIG. 5 is a waveform diagram of a main part of the block diagram of FIG. 4. 2, 8...Printer head, 3, 4, 12,
13... Amplifier, 5... Oscillator, 9... Inverter, 10, 11... Analog switch.

Claims (1)

【特許請求の範囲】[Claims] 1 常時正弦波信号を発生する正弦波信号発生手
段と、前記正弦波信号発生手段から出力される正
弦波信号を入力信号とし、駆動用デジタル制御信
号をゲート入力とする逆相用アナログスイツチ回
路と、前記制御信号の論理値を反転させる為のイ
ンバータと、前記正弦波信号を入力信号とし、前
記インバータの出力信号をゲート入力とする同相
用アナログスイツチ回路と、前記正弦波信号発生
手段の出力端子を同相用入力端子に接続し、逆相
用入力端子が接地された第1の増幅器と、前記同
相用アナログスイツチ回路の出力端子を、抵抗を
介して接地されている同相用出力端子に接続し、
前記逆相用アナログスイツチ回路の出力端子を、
抵抗を介して接地されている逆相用入力端子に接
続した第2の増幅器とを有し、前記駆動用デジタ
ル制御信号により制御されながら、前記第1及び
第2の増幅器の出力の各々をプリンターヘツドに
送出し、前記第1及び第2の増幅器のいずれか一
方の出力電圧から他方の電圧を減じた出力電圧を
前記プリンタヘツドに印加するプリンターヘツド
駆動回路。
1. A sine wave signal generating means that constantly generates a sine wave signal, and an anti-phase analog switch circuit whose input signal is the sine wave signal output from the sine wave signal generating means and whose gate input is a driving digital control signal. , an inverter for inverting the logical value of the control signal, an in-phase analog switch circuit using the sine wave signal as an input signal and an output signal of the inverter as a gate input, and an output terminal of the sine wave signal generating means. is connected to the in-phase input terminal, and the first amplifier whose negative-phase input terminal is grounded and the output terminal of the in-phase analog switch circuit are connected to the in-phase output terminal which is grounded via a resistor. ,
The output terminal of the anti-phase analog switch circuit is
a second amplifier connected to a negative phase input terminal that is grounded via a resistor, and outputs each of the outputs of the first and second amplifiers to the printer while being controlled by the driving digital control signal. A printer head driving circuit that applies to the printer head an output voltage obtained by subtracting the output voltage of one of the first and second amplifiers from the output voltage of the other.
JP5502482A 1982-04-01 1982-04-01 Printer head drive circuit Granted JPS58171967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5502482A JPS58171967A (en) 1982-04-01 1982-04-01 Printer head drive circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5502482A JPS58171967A (en) 1982-04-01 1982-04-01 Printer head drive circuit

Publications (2)

Publication Number Publication Date
JPS58171967A JPS58171967A (en) 1983-10-08
JPH0436860B2 true JPH0436860B2 (en) 1992-06-17

Family

ID=12987092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5502482A Granted JPS58171967A (en) 1982-04-01 1982-04-01 Printer head drive circuit

Country Status (1)

Country Link
JP (1) JPS58171967A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6059394A (en) * 1988-04-26 2000-05-09 Canon Kabushiki Kaisha Driving method for ink jet recording head

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5597677A (en) * 1979-01-16 1980-07-25 Seiko Epson Corp Driving circuit for ink jet printer head
JPS57105361A (en) * 1980-12-24 1982-06-30 Seiko Epson Corp Driving method of on demand type ink jetting head

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5597677A (en) * 1979-01-16 1980-07-25 Seiko Epson Corp Driving circuit for ink jet printer head
JPS57105361A (en) * 1980-12-24 1982-06-30 Seiko Epson Corp Driving method of on demand type ink jetting head

Also Published As

Publication number Publication date
JPS58171967A (en) 1983-10-08

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