JPH0436631B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a malfunction prevention circuit in a device that displays a superimposed screen of a television screen and an internal (personal computer) screen.

[Conventional technology]

On a personal computer (personal computer)
Internal screen (computer screen) on CRT display
The on-air or VTR TV screen is displayed on top of the other (superimposed). To explain this with reference to FIG. 3, 10 is a video signal output terminal of a television receiver or video tape recorder, and the video (TV) signal from this terminal is sent to a monitor (CRT display) through a selection gate 14 on the PC side. The internal (PC) screen signals stored in the screen memory (video RAM, VRAM) 30 are also sent to the monitor through the selection gate 14, and the monitor superimposes these signals (superimposes the PC screen on the TV screen). display).

Synchronization is required to display both screens overlappingly, and the clock stop gate 24 and the like are circuits for this purpose. That is, the television signal from the terminal 10 is also supplied to the synchronization separation circuit 12, where the horizontal synchronization signal EH and the vertical synchronization signal EV are separated and input to the phase comparison circuits 16 and 18. On the other hand, the clock oscillator 20 generates a clock CLK which becomes the dot clock of the CRT display, supplies this clock to the counter 22, causes the counter to count this clock, and is used as the horizontal synchronizing signal HS and vertical synchronizing signal EV of the television signal. Create horizontal synchronization signal HS and vertical synchronization signal VS with the same period (slightly shorter).
Counter 22 is clocked via gate 24.
Upon receiving CLK, it outputs the signals HS and VS, and also generates an address for accessing the screen memory 30. When the memory 30 is read at the address generated by the counter 22, it simultaneously outputs data for a plurality of dots, which is stored in the shift register 28 and sequentially output (parallel/serial converted) by the clock CLK to form an image signal. becomes (see here for details)
HS, VS added). The clock CLK is also supplied to a central processing unit CPU, etc., and the CPU writes image data to the memory 30 and the like.

Synchronization between the TV screen and the computer screen is performed as follows. That is, if the internal horizontal synchronizing signal HS generated on the personal computer side is generated earlier than the external horizontal synchronizing signal EH separated from the television signal, the phase comparison circuit 16 produces an output, which is passed through the OR gate 26 to the clock stop gate (AND gate) 24. counter 22 of the clock CLK.
Prohibit input to . When the external horizontal synchronizing signal EH is input, the phase comparison circuit 16 releases the clock stop, and the counter 22 starts counting the clock CLK. Since the period of the internal horizontal synchronization signal HS generated on the personal computer side is slightly shorter than the period of the external horizontal synchronization signal EH, the signal HS arrives slightly earlier than EH, so the clock is stopped and when the signal EH arrives. Clock stop is released. And so on, and thus the internal horizontal sync signal
HS is synchronized to external horizontal synchronization signal EH. Internal vertical synchronization signal VS is similarly synchronized with external vertical synchronization signal EV.

The selection gate 14 is controlled by a control signal (not shown).
TV signal from terminal 10, shift register 28
Select one of the computer screen signals from and output it. For example, as shown in FIG.
To superimpose the computer screen 34 on the screen 2, for the horizontal scanning line l, start from the starting point S.
The signal up to _P1 may be a television signal, the line from point _P1 to point _P2 may be a personal computer signal, and the line from point _P2 to terminal E may be a television signal, and the gate 14 performs this switching.

[Problem that the invention seeks to solve]

By the way, when switching channels on a television receiver, although the period of the horizontal/vertical synchronizing signal of each station is the same, the phase is different, so when switching channels, the period of the horizontal/vertical synchronizing signal becomes abnormally long. It becomes shorter. Also, with VTRs, signal dropouts may occur.
In this case, the horizontal and vertical synchronization signals are temporarily
EH and EV will no longer be obtained. This results in a clock
If an abnormality occurs in the CLK, a runaway program may occur in the central processing unit CPU, and data stored in the screen memory 30 may be destroyed. i.e. clock
CLK also serves as the CPU clock and determines its cycle time, but since there is a minimum allowable value for this, if the clock period temporarily falls below the allowable minimum value due to a clock abnormality, normal operation cannot be maintained and the program will run out of control. etc. will occur. The memory 30 is a dynamic RAM, and reading is performed by, for example, precharging the bit line, selecting the word line, opening the transfer gate, connecting the memory cell to the bit line, applying a potential difference, and driving the sense amplifier. Enlarging the potential difference to drive the data bus and rewrite the memory cell,
This takes a certain amount of time, and if this time is not secured due to a clock error, the data stored in the cell will be destroyed.

The present invention improves this point, and when the synchronization signal of the television signal is abnormal, especially when the period of the vertical synchronization signal becomes abnormally short, the vertical synchronization signal with the abnormally short period is transmitted to the internal circuit (computer circuit). The aim is to prevent the above problem from occurring by preventing the above problem from occurring.

[Means for solving problems]

The present invention provides an apparatus for inputting a television signal and an internal screen signal obtained by reading a screen memory into a display and displaying a superimposed screen of the television screen and the internal screen on the display. In a circuit that prevents malfunctions caused by an abnormally short period of the vertical synchronization signal, a monostable is triggered by the vertical synchronization signal separated from the television signal and produces an output with a pulse width slightly shorter than the normal period of the vertical synchronization signal. circuit and
The present invention is characterized in that it has a gate circuit which receives the vertical synchronizing signal and the output of the monostable circuit and passes only the vertical synchronizing signal having a normal period or a period close to the normal period.

[Effect]

By using this circuit to cut out the vertical synchronization signal having an abnormally short period, the occurrence of the above problem can be avoided.

〔Example〕

FIG. 1 shows an embodiment of the present invention, in which 12 is the aforementioned synchronization separation circuit, and the video (TV) signal from the terminal 10 is
Receives the signal, separates and outputs external horizontal synchronization signal EH and external vertical synchronization signal EV. 42 is a monostable circuit (single shot), and 44 is an AND gate. In the conventional circuit, the vertical synchronization signal EH separated by the synchronization separation circuit 12 was used as it is in the personal computer circuit, but in the present invention, the vertical synchronization signal EV' passed through the gate 44 is used.

The operation will be explained with reference to FIG. 2. Since the period of the vertical synchronization signal of the television signal is 16.6 mS, the signal EV appears at intervals of t ₁ =16.6 mS. The one-shot circuit 42 is triggered by the falling edge of the signal EV and produces an output with a constant pulse width. The output (which is referred to as CS) is applied to the AND gate 44, and therefore, when the signal EV passes, the gate 44 is closed for a time t ₂ (the above-mentioned constant pulse width). However, since we have selected t ₁ > t ₂ +W, the next signal EV
The gate 44 is open at the time when the signal occurs, and there is no problem in passing the signal. Here, W is the pulse width of the signal EV, and t ₂ +W is approximately 90% of t ₁ .
Of course, it is preferable to set this value close to 100% because the noise removal range will expand, but if it is too close to it, there is a risk that a part of the normal vertical synchronization signal will be cut out with a slight fluctuation, so it is recommended to set it to an appropriate value. good. The above is the normal operation, and the output EV of the synchronous separation circuit is equal to the output EV' of the AND gate 44.

On the other hand, if multiple vertical synchronization equivalent signals occur within one normal period (16.6 mS) of the vertical synchronization signal during an abnormal situation such as when the channel is switched on the TV receiver or when noise is mixed in, A signal within 90% of the period cannot pass through the gate 44 and is cut off. In this way, only vertical synchronizing signals having an interval equivalent to one cycle can pass through the AND gate 44, and vertical synchronizing signals having an abnormally short cycle are prevented from being input into the personal computer.

There is also a method of performing vertical synchronization by clearing a counter as shown in FIG. The phase comparator circuit 16 operates in the same manner as in FIG. 3 to stop and release the clock, but in this circuit, the phase comparator circuit 18 for the vertical synchronization signal is not provided, so there is no clock stop from the circuit 18. . Instead, in this circuit, the external vertical synchronization signal EV is input to the counter 22 to clear the counter and set the address for accessing the screen memory 30 to 00... In this case, if the external vertical synchronization signal is frequently input due to channel switching, etc., the counter 2
2 is cleared frequently, and the refresh timing of the screen memory 30 may not be satisfied. The present invention is also effective in such a system.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to prevent runaway and destruction of stored contents due to vertical synchronization abnormalities in the superimposition circuit between the television screen and the internal (personal computer) screen, which is extremely effective.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a time chart for explaining the operation, Fig. 3 is a circuit diagram of the main part of superimpose, Fig. 4 is an explanatory diagram of the superimpose screen, FIG. 5 is a block diagram showing another example of a synchronization circuit. In the drawing, 30 is a screen memory, EV is a vertical synchronization signal, 42 is a monostable circuit, and 44 is a gate circuit.

Claims (1)

[Scope of Claims] 1. A device that inputs a television signal and an internal screen signal obtained by reading a screen memory to a display and displays a superimposed screen of the television screen and the internal screen on the display, from the television signal. In a circuit that prevents malfunctions caused by an abnormally short period of the separated vertical sync signal, it is triggered by the vertical sync signal separated from the TV signal and produces an output with a pulse width slightly shorter than the normal period of the vertical sync signal. A malfunction prevention circuit comprising: a monostable circuit; and a gate circuit that receives the vertical synchronization signal and the output of the monostable circuit and passes only the vertical synchronization signal having a normal period or a period close to the normal period.