JPH08205091A - Synchronizing signal processing circuit - Google Patents

Abstract

PURPOSE: To prevent the vertical vibration of a display image from being caused resulting from a vertical synchronizing signal VD and a pseudo vertical synchronizing signal VD' outputted by special reproduction of a VTR. CONSTITUTION: Signals VD/VD' from a VTR are given to a 1H pulse generating circuit 1, in which a pulse (1) of 1H width is generated based on a signal HD (horizontal synchronizing signal) from the VTR, the 8H shift circuit 2 shifts the phase of the pulse (1) by 8H the result is fed to an ANd circuit 3, where the signals VD/VD' are ANDed with the resulting pulse to provide the output of a signal (3), and it is fed to counters 4, 5. The counter 4 is reset by the signal (3) to count the HD and provides the output of a signal (4) at 16 counts. The counter 5 starts the output of a signal (mask pulse) (5) with the count 1 of the signal (3) and stops the output (mask pulse) with the signal (4) from the counter 4. The mask pulse is fed to the vertical synchronizing signal processing circuit of a display device to mask the VD and to apply synchronization with the VD'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal processing circuit, and more particularly to a vertical synchronizing signal processing circuit for eliminating vertical vibration of an image during special reproduction of a VTR (video tape recorder).

[0002]

2. Description of the Related Art A VTR is provided with a vertical sync signal V as shown in FIG. 3 in special reproduction such as still reproduction or fast-forward reproduction.
In addition to D, the pseudo vertical synchronizing signal VD 'is output. This is because the video head diagonally crosses the video track on the video tape during special playback, and noise is generated. If this noise overlaps VD, the vertical synchronization of the playback image is disturbed and the screen becomes difficult to see. In order to prevent this, a pseudo VD (VD ') is inserted before the original VD, and the VD' is used for vertical synchronization. This VD 'is, for example, VH
In the case of the S system, the video head is switched 6.5H ± 1.5H before VD and VD ′ is inserted within 5H after that. However, since VD and VD 'exist in the vertical blanking period, depending on the signal processing circuit of the display device (for example, one that converts a video signal into a digital signal and processes it), this VD and VD There may be two start points of the field due to ′, and the displayed image may vibrate vertically.

In order to solve this, there is a method in which a mask pulse for masking VD 'is generated and this mask pulse is applied to a synchronizing circuit to mask VD'. FIG. 4 shows an example of a circuit for generating this mask pulse. The 1H pulse generation circuit 11 is reset by VD, a pulse of 1H width is generated based on HD (horizontal synchronization signal), and the counter 12 and the counter are generated by this 1H pulse. 13 is reset, the required number of HDs are respectively counted, the mask pulse generation circuit 14 is set by the RC output (count-up signal) of the counter 12, the mask pulse is raised, and the mask pulse is reset by the RC output of the counter 13. It is a circuit to do. Therefore, since the counter 13 counts 200 or more HDs, a counter having a large number of bits is required, and if the mask pulse width is narrow, VD 'is not masked and the mask pulse width is too wide. And VTR normal playback V
When the frequency of D is unstable, there is a problem that only one VD is masked and synchronization is lost.
There is a problem that it is difficult to set a mask pulse that surely masks D '.

[0004]

As described above, the VTR
Since the VD 'is always output prior to the VD during the special reproduction of, the use of this VD' for the vertical synchronization and masking the VD does not hinder the operation of the subsequent circuits. In view of such a point, the present invention can generate a mask pulse with a counter having a smaller number of bits than before and can perform VD during special reproduction.
Is to make sure to mask.

[0005]

In order to solve the above problems, the present invention provides a 1H pulse generation circuit for generating a pulse having a 1H (1H is 1 horizontal scanning time) width synchronized with a vertical synchronizing signal, and a 1H pulse generation. For example, a shift circuit that shifts the phase of the pulse from the circuit by 8H, a logical product circuit that performs a logical product operation of the vertical synchronizing signal and the signal from the shift circuit, and a signal from the logical product circuit are reset, and a horizontal synchronizing signal is generated. For example, a first counter that counts 16 and a second counter that starts signal output when the signal from the AND circuit is 1 count and stops signal output when a count-up signal from the first counter is output. And applying the signal from the second counter to the vertical synchronizing signal processing circuit of the synchronizing circuit,
The present invention provides a synchronizing signal processing circuit that masks the vertical synchronizing signals other than one in each vertical blanking period.

[0006]

With the above-described structure, the sync signal processing circuit according to the present invention is capable of performing VTR special reproduction during VTR special reproduction.
The vertical synchronizing signals other than the pseudo vertical synchronizing signal output by the masking device are masked, and only the pseudo vertical synchronizing signal is applied to the vertical synchronizing signal processing circuit of the display device.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the synchronizing signal processing circuit according to the present invention will be described in detail below. FIG. 1 is a block diagram of essential parts of an embodiment of a synchronizing signal processing circuit according to the present invention. In the figure,
Reference numeral 1 denotes a 1H pulse generation circuit, which is composed of a D-type flip-flop circuit or the like, inputs a synchronizing signal by special reproduction of a VTR, and receives a vertical synchronizing signal VD or a pseudo vertical synchronizing signal VD '.
Pulse of 1H width synchronized with is generated. Reference numeral 2 denotes an 8H shift circuit, which sets the phase of the pulse from the 1H pulse generation circuit 1 to 8
H shift. 3 is an AND circuit (AND gate), and 8
The signal from the H shift circuit 2 and the vertical synchronizing signal VD or VD 'from the VTR are logically ANDed. Reference numeral 4 denotes a counter, which counts the signal from the AND circuit 3 and outputs the signal at 1 count. A counter 5 is set by the signal from the counter 4, counts the signal from the AND circuit 3, resets at 16 counts, and outputs a pulse between set and reset.

Next, the operation of the synchronizing signal processing circuit according to the present invention will be described with reference to the time chart shown in FIG. VT
R is for special playback such as still playback or fast forward playback,
As shown in FIG. 2, the pseudo vertical synchronizing signal VD 'is output before the vertical synchronizing signal VD. In the case of the VHS system, this VD 'is inserted within 8H before VD (Fig. 2 shows 6H of VD).
This is an example in which VD 'is inserted before). These VD and VD 'are applied to the 1H pulse generation circuit 1, and a pulse having a width of 1H, that is, VD /
Generate a 1H pulse synchronized with VD '. This 1H pulse is applied to the 8H shift circuit 2, shifted 8H (), and applied to the AND circuit 3. A logical product circuit 3 performs a logical product operation of this 8H shift signal and VD / VD 'from the VTR and outputs a signal. Therefore, the signals output from the AND circuit 3 are 3 to 4 when the VTR is the special reproduction (VD and VD 'are output) (FIG. 2 shows the signals from the 8H shift circuit 2). This is an example in which one overlaps with VD and the number of output signals of the AND circuit 3 becomes three, but when the interval between VD and VD ′ is narrow and the signal does not overlap with VD, four are output. This signal is applied to the counter 4 and the counter 5, respectively. The counter 4 is reset by inputting a signal (counting by the counter 5) and outputs a signal when 16 counts are reached. The counter 5 starts outputting a mask pulse at one count of the signal, and the counter 5 outputs The mask pulse is stopped by the signal.

As described above, the counter 4 can be configured with a small 4-bit type since it is only necessary to count 16, and the counter 5 has a maximum number of 4 signals as described above, and therefore 3 bits. Can consist of And VD '
The VD input after is reliably masked even if there is a variation in the interval with VD ', and it is possible to eliminate the vertical vibration of the display image due to the two VDs in the vertical blanking period. The mask pulse from the counter 5 and VD from the VTR may be ORed by an OR circuit (not shown) and output. Further, when the number of output signals of the AND circuit 3 is 3 (counted by the counter 4) or more, switching may be performed so as to output the mask pulse.

[0010]

As described above, according to the synchronizing signal processing circuit of the present invention, the vertical synchronizing signal outputted from the VTR is surely supplied to the vertical synchronizing signal processing circuit of the display device during the special reproduction of the VTR. Since the masking is performed and only the pseudo vertical synchronizing signal is applied, the vertical vibration of the image due to the two vertical synchronizing signals is eliminated. Moreover, the counter used for generating the mask pulse of the vertical synchronizing signal may be a 3-bit type or a 4-bit type, and can be configured with a small circuit.
The cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts of an embodiment of a synchronization signal processing circuit according to the present invention.

FIG. 2 is a time chart for explaining the operation of the synchronization signal processing circuit according to the present invention.

FIG. 3 is a time chart for explaining the operation of a conventional synchronization signal processing circuit.

FIG. 4 is a principal block diagram of an example of a conventional synchronization signal processing circuit.

[Explanation of symbols]

 1 1H pulse generation circuit 2 8H shift circuit 3 AND circuit (AND gate) 4 counter (3 bits) 5 counter (4 bits)

Claims (7)

[Claims] 1. A 1H pulse generation circuit that generates a pulse having a horizontal scanning time width synchronized with a vertical synchronization signal, a shift circuit that shifts a phase of a pulse from the 1H pulse generation circuit for a required time, the vertical synchronization signal, and A logical product circuit for performing a logical product operation of the signals from the shift circuit, a first counter which is reset by the signal from the logical product circuit and counts the required number of horizontal synchronizing signals, and a required number of signals from the logical product circuit. And a second counter that starts signal output and stops signal output by a count-up signal from the first counter. The signal from the second counter is applied to the vertical synchronizing signal processing circuit of the synchronizing circuit, and each vertical A synchronizing signal processing circuit in which a vertical synchronizing signal other than one is masked during the blanking period. 2. The synchronizing signal processing circuit according to claim 1, wherein a logical sum circuit is provided, and the vertical synchronizing signal and the signal from the second counter are calculated and applied to the vertical synchronizing signal processing circuit of the synchronizing circuit. 3. The synchronization signal processing circuit according to claim 1, wherein the shift circuit shifts the phase of the pulse from the 1H pulse generation circuit by 8 horizontal scanning times. 4. The first counter outputs a horizontal synchronization signal 16 times.
The synchronization signal processing circuit according to claim 1, 2 or 3, which is configured to count. 5. The synchronization signal according to claim 1, wherein the second counter starts signal output with one count of the signal from the AND circuit. Processing circuit. 6. A reproduction signal processing circuit of a video tape recorder, wherein the special reproduction is determined based on the signal from the AND circuit, and the signal from the second counter is output. The synchronization signal processing circuit according to claim 1, claim 2, claim 3, claim 4, or claim 5. 7. The synchronization signal processing circuit according to claim 6, wherein when the number of signals from the AND circuit is 3 or more, it is determined that the special reproduction is performed.