JPS639383A - Pulse generating circuit for field reproducing device - Google Patents

Abstract

PURPOSE:To stabilize a character display at the time of muting by inputting a muting signal to the reset terminal of a counter through an OR gate circuit in addition to a pulse generator signal. CONSTITUTION:At the time of reproducing on the unrecorded track of media, a muting signal is outputted from a microcomputer, and the output signals (a) of an OR gate circuit 5 becomes the state of continuous H level irrespectively of the state of a pulse generator PG signal. Thereby, counters 3, 4 are not reset, and accordingly, the deviation of 0.5H is not generated in the output of an FH counter. Thus, at the time of such muting, the signals of continuous 1H signals free from deviation of 0.5H can be obtained by generating pseudo synchronizing signals at the time of muting in an FH counter based on a reference pulse from an oscillator 1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pulse generation circuit for a field reproduction device in a video device or the like.

2. Description of the Related Art In general, video devices such as TV photo systems record video signals on each track of the media.
By moving the head onto a specific track and rotating the media, the image on that track is displayed as a still image on the cathode ray tube. Even in such a case, it is basically an application of television technology, and one screen has 262 scanning lines.
Five fields are repeated twice, resulting in a tree with 525 scanning lines. In such a field reproducing device, the V rate timing pulse for vertical synchronization and the FH (horizontal synchronization frequency pulse) which is a clock pulse for this V rate timing pulse must be reset for each field. For this reason, conventionally,
The rate timing pulse counter and the FH counter are reset.

Here, if these counters are reset for each field, the horizontal synchronizing signal will not be in IH order as shown in Figure 2 between one field and the next field of the FH multiplied signal which is a clock pulse, and will be 0 In order to cause a period shift of .5H, in the case of normal image display, the horizontal scanning start position is set to 0.5H between one field and the next field.
It is shifted by 58.

Problems to be Solved by the Invention However, in the above-mentioned TV photo system, etc., when playing an unrecorded track of the media, a mute signal is required to erase the video in order to display various information from the microcomputer as characters. Even in devices equipped with a mute function such as those designed to output , 5H cannot be synchronized on the television side, resulting in skew distortion and difficult-to-read character display.

In other words, in the case of the conventional technology, even if the FH multiplied signal, which is the clock pulse of the rate timing pulse counter, has the same period as the horizontal synchronization signal, it cannot be used as a pseudo synchronization signal during muting, and it cannot be used separately. It is necessary to create this pseudo synchronization signal using a counter.

Means for solving the problem An oscillator that generates a reference pulse, a first counter that counts the reference pulse to create a clock pulse FH, and a rate that counts the clock pulse FH output from this first counter. The basic configuration includes a second counter that creates a timing pulse, and inputs a pulse generator signal generated every rotation of the media and a mute signal output from the microcomputer at an H level when the media is not recording. The OR gate circuit thus prepared is connected to the reset terminals of the first counter and the second counter. Then, when the mute signal is output, a mute pseudo synchronization signal is generated from the first counter based on the key pulse from the oscillator.

Operation: In normal field reproduction, the mute signal is not output as an H level, and the output of the OR gate circuit follows the pulse generator signal. This allows the first
The counter and the second counter are reset at the timing according to the pulse generator signal, and a rate timing pulse necessary for image reproduction is output. On the other hand, during muting in which the mute signal is input to the OR gate circuit as an H level, the output of this OR gate circuit takes an H level regardless of the pulse generator, so the first counter and the second counter are not reset.

Then, during muting as shown in step 2, a pseudo synchronization signal during muting is generated from the first counter based on the basic pulse from the oscillator, and this signal is LH! It becomes a state of relaxation.

Example An embodiment of the present invention will be described based on FIG.

First, an oscillator 1 is provided which generates a reference pulse Ck. This oscillator 1 is a crystal oscillator mainly composed of a crystal oscillator 2. Base pulse C from this oscillator 1
An FH counter 3 serving as a first counter for counting k is connected to the oscillator 1 and provided. The FH counter 3 counts the reference pulse Ck to generate an FH multiplied signal as a clock pulse, that is, a pulse signal having the frequency of horizontal synchronization. Furthermore, a rate pulse counter 4 as a second counter is connected to the rear stage of the FH counter 3. This V rate pulse counter 4 is
By counting the FH multiplied signal from the H counter 3, it is used to create a rate timing pulse. These counters 3 and 4 constitute a pulse generator for video signal processing, and both counters 3 and 4 are reset at the rising edge of a signal input to the reset terminal.

Therefore, the pulse generator signal PC that generates one pulse every time the media rotates once is input to the reset terminals of the counters 3 and 4, but in this embodiment, such a PG multiplied signal O with mute signal
The output side of the OR gate circuit 5 is inputted to the reset terminals of the counters 3 and 4. Here, the mute signal is sent to a microcomputer (not shown) when playing an unrecorded track on the media.
It is output at H level from 1 to 3, and is used to display characters, etc.

Further, the FH counter 3 is set to output a mute pseudo synchronization signal created based on the FH multiplied signal.

In such a configuration, the mute signal from the microcomputer is at L level during normal playback.

As a result, the output signal a of the OR gate circuit 5 matches the pulse generator PG signal. Since the counters 3 and 4 are both reset at the rising edge of the pulse signal, in such a state they are reset at the rising edge of the pulse generator PG signal. As a result, during normal playback, the V rate pulse counter 4 outputs field-type rate timing pulses in accordance with the pulse generator PC signal, which outputs one pulse for each rotation of the media.

On the other hand, when playing back on an unrecorded track of the medium, the microcomputer outputs a mute signal at H level. As a result, the output signal a of the OR gate circuit 5 remains at the H level regardless of the state of the pulse generator PC signal. With such a continuous H level output from the OR gate circuit 5, the counters 3 and 4 are not reset. In other words, FH counter 3
When a reset is applied according to the pulse generator PC signal, a deviation of 0.5H occurs between certain fields, but
Since it is not reset, the output of FH counter 3 is 0.5.
No H deviation occurs. Therefore, during such muting, the FH counter 3 generates a pseudo synchronization signal at the time of muting based on the reference pulse from the oscillator 1, thereby making it possible to generate IH-aligned signals without a deviation of 0.5H.

Since characters, etc. are displayed in accordance with such IH-aligned pseudo synchronization signals, the display state of characters on the cathode ray tube becomes stable. In order to achieve such an effect, there is no need to use a separate counter in addition to the counters 3 and 4, and it can be achieved easily and inexpensively by simply adding one OR gate circuit 5.

Effects of the Invention The present invention has a basic configuration in which an oscillator, first and second counters are provided as described above to create an FH multiplied signal V rate timing pulse as a clock pulse, and a pulse generator is connected to the reset terminal of these counters. Since not only the signal but also the mute signal is input through the OR gate circuit, 1) During normal playback, the rate timing pulse required for image playback is generated according to the field method, but when muting, these counters generate the pulse generator signal. Therefore, it is possible to output a pseudo synchronization signal at the time of mute without a deviation of 0.5H from the first counter, and therefore, the character display during mute can be made stable. It can be constructed at low cost by simply adding one OR gate circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is an explanatory diagram of a synchronization signal. 1... Oscillator, 3... FH counter (first counter), 4... V rate pulse counter (second counter)
, 5...OR gate circuit

Claims (1)

[Claims] an oscillator that generates a reference pulse; a clock pulse FH that is generated by counting the reference pulse; and an oscillator that generates a reference pulse from the oscillator when a mute signal is output from the microcomputer at an H level when the media is not recorded. A first counter that creates a pseudo synchronization signal at mute based on the timing pulse, and a second counter that counts the clock pulse FH output from this first counter to create a V rate timing pulse, which is generated every rotation of the media. The OR gate circuit into which the pulse generator signal and the mute signal are input is connected to the first counter and the second counter.
A pulse generating circuit for a field reproducing device, characterized in that the pulse generating circuit is connected to a reset terminal of a counter.