JPH04365143A - Program evaluating device - Google Patents

Abstract

PURPOSE:To present a device which automatically evaluates the matchability related to the processing bit range of a source program or the like generated by an instruction which designates bit ranges processed in parallel by a microprocessor. CONSTITUTION:An extracted source list generating means 3 is provided which extracts all instructions including processing bit range designating information, all branch instructions, and information related to their branch destinations from the source program or the like to generate an extracted source list. A processing bit range matchability discriminating means 4 is provided which discriminates matchability between the processing bit range designated at present and that related to the instruction to be next executed based on the generated extracted source list.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a source program, etc. created using instructions containing processing bit range specification information that specifies the bit range to be actually processed with respect to the maximum bit length that can be processed in parallel by a microprocessor. The present invention relates to a program evaluation device that evaluates consistency regarding the processing bit range of a program.

0002

2. Description of the Related Art A microprocessor is provided with processing bit range information storage means for storing information specifying a bit range to be processed, and based on the processing bit range information, data is processed even if the same machine language instruction is used. Microprocessors with different bit ranges have been put into practical use.

[0003] This microprocessor can handle more instructions than the types of instructions determined by the number of bytes, etc., without increasing the number of bytes or bits of machine language instructions. Therefore, the limited program RO
It becomes possible to realize more functions within M capacity, and is often effective in developing devices using, for example, a one-chip CPU with a built-in mask ROM or the like.

For example, an Oki Electric microprocessor (model name MSM66301) uses a flag called a data descriptor (hereinafter referred to as DD) to indicate the attribute of data stored in an accumulator (hereinafter referred to as ACC). When DD is 1, 16 bits of ACC data are considered valid, and when DD is 0, ACC data is determined to be 16 bits valid.
Determine the bit as valid. Operation instructions with ACC and ACC
For instructions that refer to the DD when executing a transfer instruction from , when DD is 1, word-by-word operations and transfers are performed using 16 bits as a processing unit, and when DD is 0, 8 bits are used as a processing unit. Operations and transfers are performed in byte units.

[0005] Setting and resetting of the DD are performed simultaneously when a data transfer command to the ACC is executed. DD is set to 1 when a word type load instruction to the ACC is executed, and DD is reset to 0 when a byte type load instruction is executed to the ACC. The load instruction to ACC is executed and D
When D is changed, if the next instruction refers to a DD, the newly changed DD is referenced and executed. Furthermore, the DD can also be changed by direct commands.

[0006]

[Problem to be Solved by the Invention] In developing a program in which instructions with different processing bit ranges coexist, in addition to checking logical consistency in a normal program,
It is necessary to check the consistency of the processing bit range. However, actual programs often have complex processing procedures, such as multiplexing of branch processing based on various branch instructions and module processing such as subroutines. Checking on paper is extremely inefficient in development.

The present invention has been made to solve the above problems, and its purpose is to provide a device that automatically checks the consistency of processing bit ranges.

[0008]

[Means for Solving the Problem] In order to solve the above problem, a program evaluation device according to claim 1 verifies the consistency between the currently specified processing bit range and the processing bit range related to the next instruction to be executed. The present invention is characterized by comprising processing bit range consistency determining means for determining. The program evaluation device according to claim 2 includes an excerpt list generating means for generating an excerpt list by extracting all instructions including processing bit range designation information, all branch instructions, and information regarding their branch destinations from the program. The present invention is characterized by comprising processing bit range consistency determining means for determining consistency between the currently specified processing bit range and the processing bit range related to the next instruction to be executed based on the generated excerpt list. .

[0009] The processing bit range consistency determining means is as follows:
Branch processing bit range storage means for storing the processing bit range when branching to each branch destination, and consistency determination after the branch when branching to the same branch destination with the same processing bit range specified. A double check prohibition means may be provided to omit the double check.

[0010] Furthermore, the processing bit range consistency determining means includes:
It includes a branch check execution history storage means for storing whether or not consistency judgment has been executed for all branch destinations, and also includes a branch check execution history storage means for storing whether or not consistency judgment has been executed for all branch destinations. It is preferable to include means for checking all branch routes to check consistency.

The program evaluation device according to claim 5 includes a module extracting means for extracting all modules such as subroutines from a program, and a bit range to be processed at the time of calling specified when the module is called, and the processing at the time of the call. A call/return processing bit range storage means for storing a processing bit range for each module in association with a processing bit range when receiving a bit range, executing processing in that module, and returning to the calling program; When a call is made again with the same calling conditions as those already stored in the return processing bit range storage means, the consistency determination within that module is omitted and the processing bit range storage means stores the return processing bit range storage means. The present invention is characterized by comprising intra-module double check prohibition means for reading out the processing bit range at the time of return and continuing the consistency determination between the read processing bit range and the processing bits related to the instruction after the return.

The program evaluation device according to claim 6 includes a module extracting means for extracting all modules such as subroutines from a program, and a call processing bit required for each extracted module when the module is called. A call/return processing bit range search means for searching a range and a return processing bit range when returning from the module to the calling program based on preset instruction rules, and the call/return processing bit range search. A module call/return processing bit range storage means that stores the output of the means in association with each module, and each processing bit range stored in the module call/return processing bit range storage means and the calling program. The present invention is characterized by comprising inter-module consistency determining means for determining consistency with a processing bit range.

[0013]

[Operation] The program evaluation device according to claim 1 is provided with processing bit range consistency determining means for determining consistency between the currently specified processing bit range and the processing bit range related to the next instruction to be executed. Therefore, a check regarding the processing bit range specification can be automatically performed. The program evaluation device according to claim 2 performs processing bit range consistency determination after creating an excerpt list in which only instructions related to processing bit range designation, branches, and branch destination information are extracted from the program. Since the means checks the consistency of the processing bit range step by step based on the excerpt list, it is possible to accurately evaluate the check related to the specification of the processing bit range in accordance with the execution order of the program in a short time.

[0014] Note that the processing bit range when jumping to a branch destination is memorized for each branch destination, and when branching to the same branch destination again under the same conditions, the consistency check after that branch can be omitted. , it is possible to shorten the evaluation time of a program that has many branches to the same branch destination.

[0015] Furthermore, by providing execution history storage means for storing the execution of consistency determination for each branch destination, and means for executing consistency determination for branch routes that have not been executed, it is possible to can be evaluated thoroughly.

In the program evaluation device according to claim 5, the module extraction means extracts each module from the program, and the call/return processing bit range storage means stores the results of consistency determination for each module. do. If a module is called again under the same call conditions as those already stored, the intra-module double check prohibition means reads out the already stored return processing bit range without checking within the module. Continues to determine consistency with processing bits related to the instruction after return.

[0017] In the program evaluation device according to claim 6, each module is extracted from the program by the module extraction means, and the call/return processing bit range search means is required for each module when the module is called. The processing bit range and the processing bit range at the time of return are searched, and the processing bit range storage means at the time of call/return stores the search results. Then, the inter-module consistency determining means determines the consistency between the processing bit range of the calling program and the processing bit range stored in the processing bit range storage means at the time of calling/returning. Therefore, the consistency can be determined for each module.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of a program evaluation device according to claims 1 and 2. This program evaluation device 1 evaluates a source program written in an assembler language or the like, and includes an input section 2, an excerpt source list generation means 3 as an excerpt list generation means, and a processing bit range consistency determination means (hereinafter referred to as It consists of a consistency determining means (simply referred to as consistency determining means) 4 and an evaluation result output section 5.

The source program input unit 2 inputs a source program S created by a program development device (not shown) or the like.
is read and temporarily stored in the input device 2a and RA.
The source program storage unit 2b is configured using M or the like. When inputting the source program S via a recording medium such as a floppy disk or magnetic tape, the input device 2a includes a floppy disk drive device and a magnetic tape playback device. When the source program S is directly input from a program development device (not shown) or the like via a data bus or serial transmission path, the input device 2a includes an interface circuit for this purpose.

[0020] Note that in the case of a configuration in which the source program evaluation device 1 is built into the program development device and the source program stored in the storage section of the program development device is read out and evaluated, the source program input section 2 may not be provided. You can.

The excerpt source list generating means 3 includes a read control section 31 for reading out the source program stored in the source program storage section 2b, line by line, for example, and a read out source program SS based on preset rules. Program line number information 32a, instruction information 32b, jump destination specification information 32c, and jump destination information 32
a disassembly unit 32 that disassembles the instruction information 32b into commands to be extracted; an instruction matching unit 33 that determines whether the instruction information 32b is an instruction to be extracted; and an extraction instruction specifying unit 34 in which information related to a plurality of instructions to be extracted is registered in advance. Based on the extraction command 33a output from the command matching unit 33, each decomposition output 3 of the decomposition unit 32 is sent to the excerpt source list storage unit 35 configured using a RAM or the like.
A write control unit 36 is provided for writing 2a to 32d in correspondence with each other.

[0022] When there is only one type of CPU to be developed and the development language of the source program is fixed, the extraction instruction specifying section 34 may be configured with a ROM or the like that stores information related to the instruction group to be extracted in advance. Good, RAM and this R
It may also be provided with a write control means for the AM, so that information related to commands to be extracted from the outside can be arbitrarily registered.

[0023] The readout control unit 31 receives an excerpt start command 31.
When a is given, the read address counter in the read control unit 31 is set to the initial state, a read command 31b including the read address is output, and the first line of the source program is read from the source program storage unit 2b. When the read control unit 31 receives an extraction unnecessary command 33b from the instruction matching unit 33 or receives a write completion signal 36a from the write control unit 36, the read control unit 31 controls a read address counter (not shown) provided in the read control unit 31. etc., and reads the next line of the source program.

[0024] The write control unit 36 sends an excerpt start command 31
When a is received, the excerpt source line number counter provided in the write control section 36 is set to the initial state, and the count value of the counter is output as excerpt list line number information 36a. Upon receiving the extraction command 33a, the write control unit 36 writes each piece of information 32a, 32b, 32c, and 33d to a write address that has been associated in advance based on the count value of the excerpt source line number counter, and a series of write processing is performed. The configuration is such that a write completion signal is output to the read control section 31 when the write is completed. Furthermore, upon receiving a new extraction command 33a, the write control unit 36 increments the excerpt source line number counter. The code 36c is
This is a write command that includes a write address.

The excerpt source list storage section 35 is composed of a RAM and its peripheral circuits. Information to be memorized 32a~
32d and 36a are each provided with a RAM, and the information 32a to 32d and 36a are simultaneously written based on the address corresponding to the line number information 36a of the source list. Note that each piece of information 32a to 3 is stored in one set of RAM.
2d and 36a may be sequentially stored at different addresses. In this case, the write control unit 36 performs writing while sequentially specifying a plurality of addresses that are previously associated with each piece of information for one row number.

The consistency determining means 4 checks the consistency of the specification regarding the processing bit range from the beginning to the end of the excerpt source list over all branch paths, and checks the consistency of the specification regarding the processing bit range. A checking means 70 is provided.

Based on the inconsistency detection output 70a output from the consistency check means 70, the evaluation result output unit 5
Line number information 32 of the source program determined to be inconsistent
a, a mismatch information management unit 51 that temporarily stores the command information 32b, information B related to the processing bit range, etc., and a monitor display that displays the stored mismatch information on a CRT or the like, or an output device such as a printer that prints it out. 52.

FIG. 2 is a block diagram showing a specific example of the processing bit range consistency determining means 4. As shown in FIG. The execution order control unit 60 includes a read control unit 61 that provides a read command 61a including a read address to the excerpt source list storage unit 35, a branch condition detection unit 62 that detects whether the read instruction is a branch instruction, and a branch condition detection unit 62 that detects whether the read instruction is a branch instruction or not. Line number information of the excerpt source list related to the jump destination when the specified information 35c is input (corresponding to address information of the excerpt source list storage unit 35)
63b (hereinafter referred to as jump destination information), and a branch check execution history storage section 65 based on various branch instruction detection outputs 62b and 62c output from the branch instruction detection section 62. an execution history management means 64 for writing various information related to the execution history into the execution history, and a double check prohibition means 66 for preventing the consistency check from being performed again on the same branch route under the same processing bit range specification conditions; It also includes an all-branch route check execution means 67 that executes a consistency check of unchecked routes based on the check execution history in the branch check execution history storage unit 65.

The jump destination-to-line information correspondence means 63 executes the execution of the excerpt source list from the first line to the last line via the read control unit 61 based on the conversion table creation command 63a given before the start of the consistency check. The jump destination information 35c and the row number information 35e of the excerpt source list related to the jump destination (excerpt source list line number information issued by the write control unit 36 in the source list generation means 3 shown in FIG. 1) are read out sequentially in numerical order. 36a) is generated in the form of a conversion table, for example, and is temporarily stored. Note that the correspondence table between the jump destination information 35c and the line number information 35e of the excerpt source list may be generated at the time of creating the excerpt source list.

The branch condition detection unit 62 includes a branch instruction-branch condition correspondence table in which a list of branch instructions and information as to whether each branch instruction is an unconditional branch or a conditional branch are registered in advance. Note that this branch instruction-branch condition correspondence information may be configured to be writable from the outside, or may be configured to be writable from the outside.
A ROM or the like that stores branch condition correspondence information may be configured to be replaceable. Then, the branch condition detection unit 62 detects the input instruction information 3 based on the branch instruction-branch condition correspondence table.
It is configured to determine whether 5b is an unconditional branch instruction or a conditional branch instruction, output corresponding detection outputs 62b and 62c, and output a non-branch instruction detection output 62a if it is other than a branch instruction. are doing.

When the readout control unit 61 receives the consistency check start command 61b, it first reads out the first line from the excerpt source list storage unit 35. When the read control unit 61 receives the non-branch instruction detection output 62a,
The read line counter is incremented by +1, and the consistency comparison unit 73
When the comparison completion signal 73b is output from , the next row is read.

When the jump destination information-line information correspondence means 63 receives the unconditional branch instruction detection output 62b, the jump destination information-line information correspondence means 63 converts the jump destination information 35 currently read out from the excerpt source list storage section 35.
c is read, and the line number information 63b of the excerpt source list specified by the read destination information 35c is supplied to the readout control unit 61.

When the readout control unit 61 receives the unconditional branch instruction detection output 62b, the readout control unit 61 executes the jump destination-line information correspondence means 6.
The line number information 63b output from 3 is read and set in the line counter, and the comparison completion signal 7 is sent from the consistency comparison unit 73.
Wait until 3b is given. When the read control unit 61 receives the conditional branch instruction detection output 62c, it increments the read line counter of the excerpt source list by +1 and waits until a comparison completion signal 73b is provided from the consistency comparison unit 73.

When the execution history management means 64 receives the unconditional branch instruction detection output 62b, the execution history management means 64 receives the jump destination designation information 35c of the branch destination and the current processing bit range information (the processing bit range before moving to the jump destination). 72a and branch execution information 64J indicating that the consistency check of the branch route has been executed.
and written into the branch check execution history storage unit 65 in association with each other. When the execution history management means 64 receives the conditional branch instruction detection output 62c, the execution history management means 64 stores the jump destination designation information 35c of the branch destination.
, the current processing bit range information 72a, and branch unexecuted information 64M indicating that the consistency check of the branch route has not been performed yet are written into the branch check execution history storage unit 65 in association with each other. Reference numeral 64c is a write command including a write address.

When the various branch instruction detection outputs 62b and 62c are input, the double check prohibition means 66 checks the jump destination information 3 currently read from the excerpt source list storage section 35.
5c and the current processing bit range information 72a, the branch check execution history storage unit 65 is searched based on the read information 35c and 72a, and based on the branch execution information J or the branch non-execution information M, It is determined whether or not the branch route has been checked, and if the branch route has been checked, the checked output 66a is output to the all branch route check execution means 67.

The all branch path check execution means 67 monitors each of the detection outputs 62a to 62c or the consistency comparison completion output 73b of the branch condition detection unit 62, and for example, even if a predetermined period of time elapses, a new output is not detected. When it is detected that a series of consistency checks have been completed by not occurring, or when it is detected that a series of consistency checks has been completed based on the checked output 66a output from the double check prohibition means 66. is the branch check execution history storage unit 6
Start checking the consistency of the unchecked routes listed in 5.

The all-branch route check execution means 67 reads out unchecked jump destination information 65a based on the branch unexecuted information M in the branch check execution history storage section 65, and sends it to the jump destination-line information correspondence means 63. Unchecked destination information 6
7a, and reads processing bit range designation information 65b before jumping to the branch destination from the branch check execution history storage section 65, and supplies this to the current processing bit range storage section 72 as processing bit range designation information 67b. Make me remember. Next, all branching road check execution means 67
reads the unbranched route check command 67c and the control unit 6
1 to start a consistency check, and at the same time, branch unexecuted information M in the branch check execution history storage section 65 is rewritten to branch execution information J.

[0038] Furthermore, the all branch road check execution means 67
Checked output 66a from double check prohibition means 66
When receiving the command, after supplying an interruption command 67d to the reading control unit 61 to interrupt reading of the excerpt source list,
Branch unexecuted information M in branch check execution history storage unit 65
Search for. The all-branch road check execution means 67 is configured to generate an all-branch road check end output 67e when the branch unexecuted information M is no longer detected.

When the readout control section 61 receives the unbranched route check command 67c, it reads the jump ahead information 63b outputted from the jump destination-line information correspondence means 63, and performs the jump ahead information 63b corresponding to the line number information. It is configured to read out various kinds of stored information 35a to 35e.

Next, the configuration of the consistency check means 70 will be explained. The consistency check means 70 includes an instruction-processing bit correspondence means 71 and a current processing bit range storage section 7.
2 and a consistency comparison unit 73.

The instruction-processing bit correspondence means 71 includes a conversion or correspondence table between various types of instruction information 35b and information 71a relating to the processing bit range assigned to the instruction information 35b. The conversion or correspondence table is constructed using a decoding circuit, ROM, RAM, etc. The instruction-processing bit correspondence means 71 provides information 71a related to the processing bit range of the input instruction information 35b to the consistency comparison section 73.

The current processing bit range storage unit 72 stores the RA
It consists of M or parallel multiple bit latch circuits and their peripheral circuits. The current processing bit range storage unit 72 is
When the consistency check start command 61b is given, the target CPU is initialized to the processing bit range of the initial state set by resetting or the like.

The current processing bit range storage section 72 also stores the next processing bit range setting information 7 from the consistency comparison section 73.
Processing bit range information 73 given when 3c is output
c is stored, and when the processing bit range designation information 67b is output from the all branch road check execution means 67, the designation information 6
Remember 7b. The current processing bit range storage unit 72 is
It is configured to always output the stored processing bit range information 72a.

The consistency comparison section 73 compares the current processing bit range information 72a given from the current processing bit range storage section 72 and the processing bit range related to the next instruction output from the instruction-processing bit range correspondence means 71. It inputs the information 71a and checks its consistency, and includes a judgment table set or registered in advance. If the processing bit range requested by the next instruction is inconsistent with the current processing bit range information 72a, the consistency comparison unit 73 outputs a mismatch detection output 73a, and then outputs a comparison completion signal 73b. Output.

If the next instruction is an instruction to set a processing bit range, the consistency comparison unit 73 uses the processing bit range information requested by that instruction as the next processing bit range setting information 73c for the current processing. Bit range storage section 7
2, a comparison completion signal 73b is output. The consistency comparator 73 is configured to simply output a comparison completion signal 73b when the compatibility is compatible.

FIG. 3 is a block diagram of the evaluation result output section 5. As shown in FIG. The inconsistency information management section 51 includes an inconsistency information storage section 53 configured with a RAM or the like;
A write/read control unit 54 that controls writing and reading to and from an output device 52P specified based on an output command 55a from an input device 55 such as a keyboard.
, 52D is provided.

The output device 52 includes a printer 52P, a monitor display 52D, and the like.

With the above configuration, the program evaluation apparatus 1 according to claims 1 and 2 is configured such that the excerpt source list generation means 3 generates program information necessary for evaluation with respect to the source program S read from the source program input section 2. The consistency determining means 4 determines the consistency of all execution paths in the excerpt source list, and the evaluation result output unit 5 outputs information on locations where the specification regarding the processing bit range is inconsistent. can do.

[0049] The program evaluation device 1 according to claims 1 and 2 shown in Figs. The extracted program is executed, the processing bit range information 71a related to the extracted instruction is obtained via the instruction-processing bit correspondence means 71, and the consistency check of the processing bit range is performed.

With this configuration, when only the type of branch instruction to be extracted is different or only the processing bit range information corresponding to a specific instruction is changed, the extraction instruction specifying section 34 or the instruction-processing bit This can be handled by changing only the information registered in the handling means 71. Furthermore, with such a configuration, the excerpt source list generated by the excerpt source list generation means 3 can be output to another evaluation device and used for evaluating whether the execution order of each module is appropriate or not. Is possible.

On the other hand, without storing the instruction information 35a in the excerpt source list storage section 35, the processing bit range information (output 71 of the instruction-processing bit correspondence means 71) corresponding to the instruction is stored.
It is also possible to store the processing bit range information (corresponding to 71a) and directly supply the read processing bit range information (corresponding to 71a) to the consistency comparison unit 73.

Hereinafter, in a configuration in which processing bit range information corresponding to an instruction is stored in the excerpt source list storage section 35, a configuration for a CPU that can switch between word-based processing and byte-based processing based on the above-mentioned DD flag will be described. The operation of the main parts of the program evaluation apparatus 1 according to claims 1 and 2 will be explained using a developed source program as an example.

FIG. 4 is an explanatory diagram showing a part of the source program. This source program S is written in assembly language, and line number information 3 of the source program S
2a, instruction information 32b, jump destination designation information 32c, jump destination information (label) 32d, and operands. The source program S may include various comments.

FIG. 5 is an explanatory diagram showing a part of the commands registered in the extraction command designation section. The extraction command designation section 34 includes D.
Instructions related to the D flag and instructions related to branching are recorded in association with the functions of the instructions.

The internal code shown in FIG.
It means the CPU processing condition for b, and WS is D
Setting the D flag to 1 indicates that the BS resets the DD flag to 0. DD flag=1 indicates processing in units of words, and DD flag=0 indicates processing in units of lower bytes. BR in the internal code means an instruction to be executed when DD1=0, and WR means an instruction to be executed when DD=1. JP in the internal code performs an unconditional jump (unconditional branch), JC
means a conditional jump (conditional branch). In the internal code, CA means subroutine call, RT means return from subroutine, and ED means end of processing, return from interrupt processing, and restart instruction.

The 1-bit information following the internal code is DD
This shows the correspondence between flags and operands. 0 in this 1-bit information indicates that the word or byte unit specified by the DD flag is processed regardless of the operand, and 1 in this 1-bit information indicates that the operand is Indicates that processing is performed based on the designation of the DD flag only when an accumulator is designated.

By providing the information shown in FIG. 5 in the extraction instruction specifying section 34, the instruction matching section 33 shown in FIG. Command information 3 obtained by
2b determines whether the instruction should be extracted, and if the instruction is to be extracted, the internal code shown in FIG. 5 can be provided to the excerpt source list storage section 35 instead of the instruction information 32a.

FIG. 6 is an explanatory diagram showing a part of the excerpt source list. By performing the above-described operation for all lines of the source program S, the excerpt source list shown in FIG. 6 can be generated in the excerpt source list storage section 35. Reference numeral 36a is the line number of the excerpt source list issued by the write control unit 36 shown in FIG. 1, reference numeral 32d is jump destination information, and reference numeral 32a is line number information of the original source program. The information following the internal code is destination specification information 3
It is 2c. Note that the line number information 32a of the original source program is stored in order to output the line number of the original source program when there is an inconsistency, and the line number information of the original source program is stored in the evaluation result output section. If it is not output from 5, there is no need to store it.

FIG. 7 is an explanatory diagram showing the correspondence between jump destination information and line numbers of the excerpt source list. In FIG. 2, after creating the excerpt source list, the jump destination-line information correspondence means 63 in the execution order control means 60 generates and stores the correspondence table shown in FIG. 7, but this jump destination information and The line number correspondence table of the excerpt source list may be created at the same time as the excerpt source list is generated.

FIG. 8 is a flowchart showing the operation of the processing bit range consistency determining means 4. S1 and S2 in Figure 8
...indicates a step in the flowchart. When a consistency check start command 61b is given from a control unit or an input unit (not shown) (the input device 55 in the mismatch information management unit 51 shown in FIG. 3 may be used) (S1), the readout control unit 61 One line of the excerpt program is read from the excerpt source list storage section 35 (S2).

The processing bit range information 72a in the current processing bit range storage section 72 shown in FIG. 2 is set to the initial state of the target CPU based on the consistency check start command 61b. If the CPU has a configuration in which the initial value is given by an instruction, the current processing bit range storage unit 72
The processing bit range information 72a within is information (N) indicating that it is undefined.

If the read instruction is not a branch instruction, the process moves to one of steps 4 to 7 based on the type of the instruction (S3).

[0063] When the processing bit range information 71a related to the instruction in that line sets processing in byte units (internal code BS), the consistency comparison unit 73 compares the information (B) related to byte units with the current one. is set in the processing bit range storage unit 72 (S4). Similarly, when processing is to be set in word units (internal code WS), information (W) related to word units is set (S5).

Further, when the processing bit range information 71a related to the instruction in the row is an instruction to be executed in byte units or word units (internal codes BR, WR), the storage unit 7
It is determined whether or not they match the current processing bit range information 72a set to 2 (S6), and if they do not match, a mismatch detection output 73a is generated (S7).

[0065] Then, add 1 to the next row number to read,
The process moves to step 2 (S8).

If the read instruction is a branch instruction (S
3) Proceed to any one of steps 9 to 12 based on the type of branch instruction.

When inheriting the processing bit range when returning from a subroutine or interrupt processing (internal code RT)
, returns to the calling program without changing the processing bit range in the current processing bit range storage unit 72 (S
9). After returning from a subroutine or interrupt processing,
If it is necessary to newly specify the processing bit range (internal code ED), the consistency comparison unit 73 sets information (N) indicating that the processing bit range is undefined (S10).
.

In the case of a conditional branch instruction (internal code JC), the double check prohibition means 66 determines whether or not the consistency check of the branch path has already been performed (S11). Even if it is unchecked, the branch check execution history storage unit 65 does not immediately branch to the branch destination.
Information regarding the branch destination is written to the branch destination, and branch unexecuted information M is also written (S13). If you have already checked,
The process moves to step 20, which will be described later.

Then, a consistency check of the processing bit range specification is performed (S14), and when a mismatch is detected, a mismatch detection output 73a is generated (S15), and the process proceeds to step S8.
Move to. That is, it is assumed that the branch condition is not satisfied, and the process moves on to checking the consistency of the next line of the excerpt source program.

In the case of an unconditional branch instruction (internal code JP), it is determined in step S12 whether or not a consistency check for the branch destination has already been performed. If the consistency has not been checked, set the line number of the unconditional branch destination (S16
), writes information related to the branch destination to the branch check execution history storage unit 65, and writes branch execution information J (S
17).

Then, a consistency check is performed on the specified processing bit range (S18), and when a mismatch is detected, a mismatch detection output 73a is generated (S19), and the process proceeds to step S2.
Move to.

If it is determined in step S12 that the consistency check for the branch destination has already been completed, the process moves to step S20.

In step 20, the all branch route check execution means 67 determines whether there is any branch route for which consistency check has not been executed yet. If there is an unchecked branch destination, the line number of the branch destination is set (S21), and the processing bit range information 73c before jumping to the branch destination is stored in the current processing bit range storage section 7.
2 (S22), and register execution information J for that branch destination (S23).

When it is determined in step 20 that there are no unexecuted branch paths, a series of consistency checks is completed (S24).

[0075] Here, as a specific example of specifying the processing bit range, processing in units of words and processing in units of lower bytes based on the DD flag was given, but the specification of the processing bit range can be specified in units of words, upper bytes, and lower bytes. , each of the first to fourth 4-bit units, or any bit unit, or a combination of multiple types thereof may be used.

Next, a program evaluation device according to claim 5 will be explained. FIG. 9 is an overall block configuration diagram of a program evaluation device according to a fifth aspect. A program evaluation device 101 according to a fifth aspect is for evaluating a source program written in an assembly language or the like, and includes a source program input section 2, an excerpt source list generation means 130,
Module extraction means 110 and module execution management section 1
20, processing bit range consistency determining means (hereinafter referred to as consistency determining means) 140, evaluation result output section 5, and evaluation data switching means 102.

The configurations of the source program input section 2 and the evaluation result output section 5 are the same as those shown in FIG.

[0078] The excerpt source list generation means 130 is shown in FIG.
The decomposition outputs 32a to 32d of the decomposition means 32 shown in FIG. , and other configurations are almost the same as the excerpt source list generation means 3 shown in FIG.

The configuration of the consistency determining means 140 is basically the same as that of the consistency determining means 4 shown in FIG. When the branch condition detection section 162 (see FIG. 10) in this consistency determination means 140 detects a call instruction to a subroutine or module, it outputs a module call instruction detection output 14.
0a and, when a return instruction is detected, a return instruction detection output 140b to the module execution management unit 120, and also performs the task of reading out the excerpt source list via the readout control unit 61 shown in FIG. It is configured to be suspended until a restart command 120a is given from the execution management unit 120.

The consistency determining means 140 also supplies the comparison completion signal 73b and the current processing bit range information 72a to the module execution management unit 120, and also supplies the processing bit range at the time of return from the module execution management unit 120. When the specified information 120b is given, the information 120
b as the current processing bit range storage unit 172 (see FIG. 10)
It is configured to be set to

The evaluation data switching means 102 switches the data D to be supplied to the consistency determination means 140 and the evaluation result output section 5, and is composed of an electronic switch circuit such as a bus selector.
The configuration is such that each read data 110D from the module extraction means 110 is selected based on the switching command 120c output from the module extraction means 110 while the extracted module is being evaluated.

Note that if the excerpt source list storage section 35 and the module storage section 114 (to be described later) are configured so that their outputs can take a high impedance state, the evaluation data switching means 102 is not provided and each storage section 35, 114
Data may be switched by controlling the output state of.

FIG. 10 is a block diagram showing a specific example of module extraction means and module execution means. The module extraction means 110 includes a module name detection/storage means 111, a module extraction control means 112, a module write control section 113, and a module storage section 114 composed of a RAM or the like.

The module name detection/storage means 111 includes a module call command table in which all module call commands used in the source program to be evaluated are registered in advance, a RAM, and a write/read control unit thereof. Module name detection/storage means 111
monitors the command information 32b output from the excerpt source list generation means 130, and when it detects a module call command registered in advance, it determines that the jump destination designation information 32c related to that command is the name of the calling module. Then, the jump destination designation information 32c is stored as a module name.

The module extraction control means 112 extracts the jump destination information 3 output from the excerpt source list generation means 130.
2d matches the module name stored in the module name detection/storage means 111,
If they match, an excerpt interruption command 110a is given to the excerpt source list generation means 130, and a module extraction command 112a is given to the module writing control section 113.

[0086] Furthermore, this module extraction control means 112
is equipped with a return command table in which all return command information (for example, return commands, etc.) from modules used in the source program to be evaluated is registered in advance, and the return command table is registered in advance with all the return command information (for example, return commands, etc.) used in the source program to be evaluated. When it is detected that the information has been output, the return command information is written into the module storage section 114, and then the output of the extraction interruption command 110a is stopped, and the output of the module extraction command 112a is also stopped.

While the module extraction command 112a is being given, the module writing control section 113 writes each piece of information 32a to 32d output from the decomposition means 32 in the excerpt source list generation means 130 to the module storage section 114. , gives a write completion signal 113a to the read control section 131 in the excerpt source list generation means 130.

Note that the module write control section 113 writes the module storage section 11 in correspondence with the module name.
4, and the module name can be specified later and read from the module execution management section 120 side.

The write control section 136 in the excerpt source list generating means 130 is configured to stop writing to the excerpt source list storage section 35 while the excerpt interruption command 110a is given. The read control section 131 in the excerpt source list generation means 130 is configured to read the next line of the source program upon receiving the write completion signal 113a from the module write control section 113.

The module execution management section 120 includes a module execution control means 121 and a module execution history storage section 1.
22, and intra-module double check prohibition means 123.

When the module execution control means 121 receives the module call instruction detection output 140a from the branch condition detection section 162 in the consistency determination means 140, it reads the jump destination specification information 32c corresponding to the instruction, and
The current processing bit range information 72a provided from the current processing bit range storage section 72 in the consistency determining means 140 is read, and each piece of information 32c, 72a is provided to the intra-module double check prohibition means 123.

[0092] Intra-module double check prohibition means 123
searches the execution history information in the module execution history storage unit 122 based on the given information 32c and 72a, and determines whether the called module has already been checked by referring to the execution flag described later. . Inside module 2
Heavy check prohibition means 123 issues a check command 123a if the called module has not yet been executed.
is given to the module execution control means 121, and if it has already been executed, return processing bit range designation information 123b, which will be described later, is read from the module execution history storage section 122 and given to the module execution control means 121.

Upon receiving the check command 123a, the module execution control means 121 writes the module name 32c and the processing bit range information 72a when entering the module into the module execution history storage section 122, and also writes the execution bit range information 72a corresponding to the module. Set flag F to check execution state.

Next, the module execution control means 121:
A switching command 120c is output, and then a module read command 121a is output to read the first line of the called module from the module storage section 114. As a result, the data 110D read from the module storage section 114 is transferred to the evaluation data switching means 102 shown in FIG.
The data is supplied to the consistency determining means 140 via.

When the comparison completion signal 73b is output from the consistency comparator 73, the module execution control means 121 reads the data 110D of the next row of the module. Further, upon receiving the return instruction detection output 140b from the branch condition detection unit 162, the module execution control unit 121 converts the processing bit range information 72a output from the current processing bit range storage unit 172 into the processing bit range information at the time of return ( 1
23b), it is stored in the module execution history storage unit 122 in association with the module name. Then, the module execution control means 121 outputs a restart command 120a to continue the consistency check of the extracted source program that had been suspended up to that point.

Module call instruction detection output 140a
When the jump destination designation information 32c and the current processing bit range information 172a are supplied to the intra-module double check prohibition means 123 in response to the above, the check command 123a is not output from the intra-module double check prohibition means 123. When the return processing bit range designation information 123b is output, the module control execution means 121 supplies and sets it to the current processing bit range storage unit 172 as the return processing bit range designation information 120b. Then, the module execution control means 121 outputs a restart command 120a to continue the consistency check of the extracted source program that had been suspended up to that point.

Note that the control for interrupting the check of the excerpt source program is performed by the read control unit 61 shown in FIG.

With the above configuration, the source program evaluation apparatus 101 according to claim 5 has the module extracting means 110 at the same time that the excerpt source list generating means 130 extracts the program necessary for checking the consistency of the processing bit range. extracts module names such as subroutines. Then, when the module extraction means 110 detects a module description line in the source program whose destination information (label) 32d is the extracted module name, it interrupts the extraction source list creation work and extracts the modularized program part. Extract and memorize.

When a module such as a subroutine is called when checking the consistency of the processing bit range, the consistency determining means 140 interrupts reading of the excerpt source list. If the consistency check of the module has already been completed using the processing bit range information 72a when the module is called, the module execution management unit 120 uses the processing bit range information 12 when returning from the module.
0b is returned to the consistency determining means 140 to continue checking after returning from the module.

[0100] If the consistency check of the called module has not been completed yet, the module execution management unit 120 sequentially reads the programs related to the module from the module storage unit 114 and supplies them to the consistency determination means 140 to check the consistency. Perform a sex check. Further, the module execution management unit 120 stores the processing bit range information 120b when returning from the module in the module execution history storage unit 122, and sets the check execution flag F of the module.

Therefore, the source program evaluation apparatus 101 according to claim 5 does not check the same module multiple times even if the source program uses many modules such as subroutines, thereby reducing the checking time. can be achieved.

FIG. 11 is an overall block diagram of a program evaluation apparatus according to claim 6. This program evaluation device 201 uses the input device 20 based on the input command 201a.
The source program S read through 2a is stored in the storage unit 2.
a source program input unit 202 to be stored in 02b;
module extraction means 210, call/return processing bit range search means 220, call/return processing bit range storage means 230, inter-module consistency determination means 240, source program consistency determination means 250,
Inconsistency information 2 output from each determination means 240, 250
The evaluation result output unit 205 includes an inconsistency information management unit 205b that manages storage and reading of the data 40c and 250c, and an output device 205a.

When the source program input section 202 receives the read command 210a from the module extraction means 210, it outputs information SJ related to the source program in the storage section 202b to the module extraction means 210, and the source program consistency determination means 250 Read command 250a from
When receiving the information, the information SJ related to the source program in the storage section 202b is output to the source program consistency determining means 250.

[0104] Note that each read command 210a, 250a
Further, each readout output SJ, SJ may be configured to perform input/output in a time-sharing manner via a common bus or the like.

The module extracting means 210 has means for accessing the storage section 202b in the source program input section 202 and reading out the stored contents, and for extracting module names such as subroutines and the modules described therein based on preset rules. The program includes means for determining the area of the source program, storage means such as RAM, and writing control means for the storage means. When the module extraction unit 210 receives the extraction command 201b, it sequentially reads the source program SJ from the storage unit 202b in the source program input unit 202, and extracts source program parts related to modules such as subroutines based on preset rules. , are extracted in association with the calling name (label) of the module, and are stored in a RAM or the like.

When the call/return processing bit range search means 220 is given the search command 201c, it outputs a read command 220a to read out the module 210D stored in the storage section in the module extraction means 210, and the Means for executing the read module 210D based on a set procedure in a simulated manner to search for transitions in the processing bit range; information on the processing bit range required when the module is called from the result of the simulated execution;
and means for writing processing bit range information 220D when returning from the module to the calling program into the calling/returning processing bit range storage means 230 in association with each module name (label).

The call/return processing bit range storage means 230 is constituted by a temporary storage circuit such as a RAM.

The inter-module consistency determining means 240 includes means for outputting a read command 240a to read out the call processing bit range information and return processing bit range information 230D related to a specific module, and the source program consistency determining means 250. A means for determining consistency with processing bit range information 250b when transferring processing to the module given along with information 250e related to the called module name, and outputting inconsistency information 240c when the determination is inconsistent. and means for replying processing bit range information 240b to the source program determining means 250 when returning from the called module.

The source program consistency determining means 250 includes means for accessing the storage section 202b in the source program input section 202 based on the check start command 201d and reading out the stored contents, and a means for reading out the stored contents of the source program input section 202 based on the check start command 201d. means for executing in a simulated manner and checking the consistency of the processing bit range, means for outputting inconsistency information 250c, and processing for passing information 250e related to the name of the called module and the module to that module when a module call command is detected. and means for outputting the bit range information 250b to the inter-module consistency determining means 240.

[0110] This source program consistency determining means 25
0 accesses the inter-module consistency determination means 240 when a module call instruction is detected, and returns processing bit range information 24 when the module processing is completed.
0b, and continues checking consistency with the next process based on the received information 240b.

Next, the operation of the program evaluation device 201 according to claim 6 will be explained. Source program input section 20
2 is an input device 202 when an input command 201a is given.
The source program S is read through the storage unit 20
2b. When the module extraction means 210 receives the extraction command 201b, the module extraction means 210 extracts the source program from the source program input section 20.
2 reads the source program SJ from the storage unit 202b, extracts all modules such as subroutines,
It is stored in the storage unit in the module extracting means 210 in association with the module name.

When the call/return processing bit range search means 220 receives the search command 201c, it sequentially reads out the module data 210D in the module extraction means 210 and executes the read module in a simulated manner. Then, determine the processing bit range information necessary when the module is called and the processing bit range information when returning from this module to the calling program,
It is stored in the call/return processing bit range storage means 230 in association with the module name.

A specific example of processing bit range search at the time of call/return will be explained using a source program in which the above-mentioned word-by-word processing and byte-by-byte processing are combined. The processing bit range search unit 220 at the time of call/return performs a consistency check on the module, assuming that the processing bit range information when the module is called is in word units, and then checks the consistency of the module when the module is called next time. The check is performed assuming that the processing bit range information of is in byte units.

[0114] As a result of the check, if it is found that the condition is that the module is called in a specific processing unit, the call/return processing bit range search means 220 performs the processing in FIG. 12(a) or (b). ), as shown in
The module name, the processing bit range information at the time of calling, and the processing bit range information at the time of return are associated and stored in the processing bit range storage means 230 at the time of calling/returning. In the case of a module that operates without contradiction to the processing bit range specification when called under any conditions, as shown in Figure 12(b), the processing bit range information at the time of calling and the processing bit range information at the time of return are associated. and memorize each.

When the source program consistency determining means 250 is given the check start command 201d, it starts checking the consistency of the source program S, and when it detects a contradiction in the processing bit range specification, it outputs inconsistency information 250c. Once a mismatch occurs, the mismatch information 250c is output for each row until an instruction for setting the processing bit range is detected. The source program consistency determining means 250
When a module call instruction is detected, the call module information 250e is sent to the inter-module consistency determining means 240.
and gives processing bit range information 250b at the time of calling.

The inter-module consistency determining means 240 receives the calling processing bit range read from the calling/returning processing bit range storage means 230 based on the calling module information 250e from the source program consistency determining means 250. Call processing bit information 2
50b, the inconsistency information 240c is output, and the processing bit range information 2 at the time of return read from the processing bit range storage means 230 at the time of call/return
40b to the source program consistency determining means 250 to continue checking the calling program. When the processing bit range information at the time of module calling is compatible, the inter-module consistency determining means 240 outputs the processing bit range information 240b at the time of return corresponding to the time of calling.

By performing the above operations over the entire source program, the consistency check is completed.

[0118]

[Effects of the Invention] The program evaluation device according to claim 1 has the following features:
Since it is equipped with a processing bit range consistency determination means that determines the consistency between the currently specified processing bit range and the processing bit range related to the next instruction to be executed, checks related to the processing bit range specification can be automatically performed. can be done. The program evaluation device according to claim 2 performs processing bit range consistency determination after creating an excerpt list in which only instructions related to processing bit range designation, branches, and branch destination information are extracted from the program. Since the means checks the consistency of the processing bit range step by step based on the excerpt list, it is possible to automatically, quickly and accurately evaluate the check related to the specification of the processing bit range in accordance with the execution order of the program.

Note that the processing bit range when jumping to a branch destination is memorized for each branch destination, and when branching to the same branch destination again under the same conditions, the consistency check after that branch can be omitted. , it is possible to shorten the evaluation time of a program that has many branches to the same branch destination.

[0120] Furthermore, by providing execution history storage means for storing the fact that consistency determination has been executed for each branch destination, and by providing means for executing consistency determination for branch routes that have not been executed, it is possible to can be evaluated thoroughly.

[0121] In the program evaluation device according to claim 5, the module extraction means extracts each module from the program, and the call/return processing bit range storage means stores the results of consistency determination for each module. do. If a module is called again under the same call conditions as those already stored, the intra-module double check prohibition means reads out the already stored return processing bit range without checking within the module. Continues to determine consistency with processing bits related to the instruction after return. Therefore, even if the program uses many modules such as subroutines, the evaluation time can be shortened.

[0122] In the program evaluation device according to claim 6, each module is extracted from the program by the module extraction means, and the call/return processing bit range search means is required for each module when the module is called. The processing bit range and the processing bit range at the time of return are searched, and the processing bit range storage means at the time of call/return stores the search results. Then, the inter-module consistency determining means determines the consistency between the processing bit range of the calling program and the processing bit range stored in the processing bit range storage means at the time of calling/returning. Therefore, the consistency can be determined for each module.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of a program evaluation device according to claims 1 and 2.

[Fig. 2] Block configuration diagram showing a specific example of processing bit range consistency determination means

[Figure 3] Block configuration diagram of evaluation result output section

[Figure 4] Explanatory diagram showing part of the source program

[Fig. 5] Explanatory diagram showing a part of the commands registered in the extraction command specification section

[Figure 6] Explanatory diagram showing part of the excerpt source list

[Figure 7]
Explanatory diagram showing the correspondence between destination information and line numbers of the excerpt source list

FIG. 8 is a flowchart showing the operation of the processing bit range consistency determination means.

FIG. 9 is an overall block configuration diagram of a program evaluation device according to claim 5.

FIG. 10 is a block configuration diagram showing a specific example of module extraction means and module execution means in the program evaluation device according to claim 5;

FIG. 11 is an overall block configuration diagram of a program evaluation device according to claim 6.

FIG. 12 is an explanatory diagram showing the storage contents of the processing bit range storage means at the time of call/return

[Explanation of symbols]

1,101,201...Program evaluation device, 2,202
...Source program input section, 3,130...Excerpt source list generation means (excerpt list generation means), 4,140...(
processing bit range) consistency determining means, 5, 205... evaluation result output section, 32... decomposition means, 33... instruction matching section, 34...
Extraction command designation section, 35...excerpt source list storage section, 60
...Execution order control means, 62... Branch condition detection unit, 63... Jump destination-line information correspondence means, 64... Execution history management means, 65
...Branch check execution history storage unit, 66...Double check prohibition means, 70...Consistency check means, 71...Instruction-processing bit correspondence means, 72...Current processing bit range storage unit,
73... Consistency comparison section, 110... Module extraction means, 1
11...Module name detection/storage means, 112...Module extraction control means, 113...Module writing control unit,
114...Module storage section, 120...Module execution management section, 121...Module execution control means, 122...Module execution history storage section, 123...Intra-module double check prohibition means, 210...Module extraction means, 220...
Call/return processing bit range search means, 230... Call/return processing bit range storage means, 240... Inter-module consistency determining means, 250... Source program consistency determining means.

Claims (6)

[Claims] Claim 1: A program evaluation device that evaluates the consistency of the processing bit range specification of a program created using an instruction that includes information specifying the bit range to be processed by a microprocessor, the method comprising: 1. A program evaluation device comprising processing bit range consistency determining means for determining consistency between a processing bit range of a currently executed instruction and a processing bit range of an instruction to be executed next. 2. A program evaluation device for evaluating the consistency of a processing bit range specification of a program created using an instruction including information specifying a bit range to be processed by a microprocessor, the program Excerpt list generating means for generating an excerpt list by extracting all instructions including the processing bit range designation information and all branch instructions and information regarding their branch destinations from the extract list;
A program comprising processing bit range consistency determining means for determining consistency between a currently specified processing bit range and a processing bit range related to an instruction to be executed next based on a generated excerpt list. Evaluation device. 3. The processing bit range consistency determining means includes branch processing bit range storage means for storing processing bit ranges specified when branching to each branch destination for all branch destinations; A double check prohibition means is provided for omitting consistency determination after the branch when the same processing bit range is specified to the same branch destination based on the memory contents of the processing bit range storage means and the branch is made again. The program evaluation device according to claim 1 or 2, characterized in that: 4. The processing bit range consistency determination means includes branch check execution history storage means for storing whether or not consistency determination has been performed for all branch destinations, and the branch check execution history storage means 3. The program evaluation apparatus according to claim 1, further comprising an all-branch route check execution means for executing consistency determination of branch routes for which consistency determination has not been performed based on stored contents. 5. A program evaluation device for evaluating the consistency of a processing bit range specification of a program created using an instruction including information specifying a bit range to be processed by a microprocessor, the program A module extracting means for extracting all modules such as subroutines from the module, a call processing bit range specified when each module was called, and a processing within the module executed and called based on the call processing bit range. A call/return processing bit range storage means that associates and stores the processing bit range when returning to the original program, and a call condition that is the same as that already stored in the call/return processing bit range storage means. When a call is made again in , the consistency judgment within that module is omitted, the processing bit range at return stored in the above-mentioned call/return processing bit range storage means is read out, and the read processing bit range and the return processing bit range are read out. A program evaluation device comprising intra-module double check prohibition means for continuing determination of consistency with processing bits related to subsequent instructions. 6. A program evaluation device for evaluating the consistency of a processing bit range specification of a program created using an instruction including information specifying a bit range to be processed by a microprocessor, the program module extracting means for extracting all modules such as subroutines from , and for each extracted module, the processing bit range required when that module is called, and the processing bit range required when returning from that module to the calling program. A call/return processing bit range search means for searching a return processing bit range based on a preset rule, and a module call that stores the output of the call/return processing bit range search means in association with each module.・Inter-module consistency judgment for determining the consistency between each processing bit range stored in the return processing bit range storage means and the module calling/return processing bit range storage means and the processing bit range of the calling program. A program evaluation device characterized by comprising means.