JPH04364785A - Manufacture of vertical mos semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method for manufacturing a vertical MOS semiconductor device, which can realize a complete depletion without restriction by a limit of a miniaturization by a photolithography and a reactive ion etching. CONSTITUTION:A first opening A is formed at an SiO2 film 2 by a photolithography and a reactive-ion etching. A recess 4a covering an inner wall of the opening A is formed by depositing an SiO2 film. After the recess 4a is buried with a W film 5a, with the W film 4a as a mask SiO2 films 2, 4a present on the periphery of the mask are removed by etching, a substrate 1 is then etched up to a depth of a source region 3, and a fine silicon post 1a to become a channel is formed. After the film 5a, an SiO2 film 4b are removed, an SiO2 film 6 having a second opening B is provided, and a gate electrode is provided at a gap . Arsenic is ion implanted in the upper part of the post 1a to form a drain region.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a vertical MOS semiconductor device in which a channel is provided in a direction perpendicular to the surface of a semiconductor substrate.

0002

2. Description of the Related Art In a planar MOS semiconductor device having a channel in a direction horizontal to the surface of a semiconductor substrate, when reducing the area occupied by individual elements in order to improve the degree of integration, the channel length may be shortened or the channel length may be shortened. It is necessary to narrow the width. However, in such a case, many problems arise, such as short channel effects, deterioration due to hot carriers, and a decrease in current drive capability. Therefore, attempts have been made to reduce the area occupied by the device by using a vertical MOS semiconductor device having a channel in a direction perpendicular to the surface of the semiconductor substrate. Vertical MOS semiconductor devices have channels perpendicular to the surface of the semiconductor substrate, so the occupied area can be reduced without shortening the channel length or narrowing the channel width, which increases the degree of integration. can be improved.

Conventionally, vertical MOS semiconductor devices have been manufactured, for example, in the following manner. First, as shown in FIG. 12A, boron ions are implanted into the surface of a silicon substrate 101 to form a p-type impurity layer 102 with a depth of 6 μm. Next, as shown in FIG. 5B, both surface portions of the p-type impurity layer 102 are removed by RIE (reactive ion etching) to form a layer with a height of 1 μm and a width of 0.5 μm. A silicon pillar 105 is formed. Next, as shown in the same figure (c), 20 nm was formed by thermal oxidation.
A gate oxide film 107 is formed to a thickness of . Next, Figure 13
As shown in (d), after depositing polycrystalline silicon 108 with a thickness of 0.6 μm, as shown in (e) of the same figure, the polycrystalline silicon 108 is etched back using a sidewall technique. The portion existing in the flat portion is removed, while the portion adhering to the side surface of the silicon pillar 105 is left with a thickness of 0.3 μm in the horizontal direction to form the gate electrode 109. Finally, as shown in FIG. 3(f), arsenic ions are implanted using the gate electrode 109 as a mask.
3 μm deep drain region 110 and source region 1
03 is formed to complete the fabrication. Note that the drain region 110 and source region 103 may be replaced with each other. Further, in this structure, channels (in a direction perpendicular to the surface of the silicon substrate 101) are formed on both side surfaces of the silicon pillar 105, respectively. In this way, by providing two gate electrodes 109, 109, controllability of drain current can be improved compared to a single gate.

0004

[Problem to be solved by the invention] By the way, thin film SOI
(Silicon on insulator) M formed on the substrate
It is known that in an OS type semiconductor device, the device characteristics are improved because the substrate portion is completely depleted. Even in the above vertical MOS semiconductor device, device characteristics can be improved if complete depletion of the channel region can be achieved. However, in the conventional manufacturing method, the thickness of the silicon pillar 105 serving as the channel region cannot be reduced to 0.5 μm or less because it is restricted by the limitations of microfabrication of photolithography and reactive ion etching. Therefore, there is a problem that complete depletion of the channel region cannot be achieved.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a vertical MOS semiconductor device that can realize complete depletion without being restricted by the limitations of microfabrication of photolithography and reactive ion etching. It is in.

[0006]

Means for Solving the Problems In order to achieve the above object, a method for manufacturing a vertical MOS semiconductor device according to the invention of claim 1 provides a method for manufacturing a vertical MOS semiconductor device in which a channel is provided in a direction perpendicular to the surface of a semiconductor substrate. The manufacturing method includes providing a first film with a predetermined thickness on the surface of the substrate, and performing photolithography and reactive ion etching to form a first film substantially perpendicular to the surface of the substrate. first penetrating
forming an opening, and using the first film as a mask, ions are implanted through the first opening to form a first layer that will become a source or drain into the substrate at a predetermined depth from the substrate surface. forming a conductive region; depositing a second film on the substrate to form a recess covering an inner wall of the opening with the second film; depositing the substrate and the first film in the recess; , embedding a third film made of a material that can be selectively etched with respect to the second film;
Using the third film embedded in the recess as a mask, the first and second films existing around this mask are etched and removed, and then the substrate is moved to the depth of the first conductive region. forming a semiconductor pillar made of a part of the substrate and connected to the first conductive region to serve as a channel under the mask; and a third semiconductor pillar left on the semiconductor pillar. , After removing the second film, a fourth film having insulating properties is deposited on the substrate, and photolithography and reactive ion etching are performed to form the semiconductor pillars on the fourth film. forming a surrounding second opening, forming a gap between a side wall of the semiconductor pillar and an inner wall of the opening; and applying gate insulation to the surface of the first conductive region in the opening and the side wall of the semiconductor pillar. a step of forming a film, a step of forming a gate electrode in the gap between the side wall of the semiconductor column and the inner wall of the opening, and a step of forming a gate electrode on the surface of the substrate.
The method is characterized in that it includes a step of performing ion implantation using the fourth film as a mask to form a second conductive region to serve as a drain or a source on the top of the semiconductor pillar.

A method for manufacturing a vertical MOS semiconductor device according to a second aspect of the invention is a method for manufacturing a vertical MOS semiconductor device in which a channel is provided in a direction perpendicular to the surface of a semiconductor substrate, the method comprising: forming a first opening in the first film that penetrates substantially perpendicularly to the substrate surface by performing photolithography and reactive ion etching; , performing ion implantation through the first opening using the first film as a mask to form a first conductive region to serve as a source or drain on the surface of the substrate; depositing a second film made of a material that can be selectively etched with respect to the film, and forming a recess covering an inner wall of the opening with the second film; depositing the second film on the substrate; After depositing a third film made of a material that can be selectively etched with respect to the film to fill the recess, etching back is performed to remove the portions of the third and second films that exist on the flat part. while leaving the recess of the second film and the part of the third film inside the recess, and removing the part of the second film that forms the side wall of the recess. The film of No. 3 is selectively etched and removed down to the substrate surface to form a pair of gaps between the inner wall of the opening of the first film and the remaining third film. a step of exposing the first conductive region; a step of forming in the gap a semiconductor pillar made of the same material as the substrate and connected to the surface of the substrate to serve as a channel; and a step of performing photolithography and etching to selectively removing each of the films existing on the conductive region to form a second opening surrounding the semiconductor pillar to provide a gap between a side wall of the semiconductor pillar and an inner wall of the opening; , forming a gate insulating film on the surface of the first conductive region in the opening and the side wall of the semiconductor pillar; forming a gate electrode in the gap between the semiconductor pillar side wall and the inner wall of the opening; A step of implanting ions into the surface of the substrate using the first film left around the opening as a mask to form a second conductive region serving as a drain or a source on the top of the semiconductor pillar. It is characterized by

Further, the semiconductor pillar has a prismatic shape, and the opening inner wall surrounding the semiconductor pillar is in contact with two of the four side walls of the semiconductor pillar that are opposite to each other,
It is desirable that the gate electrode be formed apart from the remaining two surfaces so that the gate electrode is provided on each of the remaining two surfaces.

[0009]

According to the first aspect of the invention, the thickness of the semiconductor pillar serving as the channel is equal to the opening size of the recess formed in the opening of the first film. That is, the thickness of the semiconductor pillar is determined by the width of the opening formed in the first film by photolithography and reactive ion etching, and the thickness of the second film that covers the inner wall of this opening to form a recess. determined by As already mentioned, the limit of microfabrication by photolithography and reactive ion etching is 0.5 μm. therefore,
By increasing the thickness of the second film (limited to the range where the recesses (indentations) are formed), the thickness of the semiconductor pillar can be made thinner beyond the limits of the microfabrication. Therefore, a fully depleted vertical MOS semiconductor device can be manufactured without being restricted by the limitations of microfabrication.

According to the second aspect of the invention, the thickness of the semiconductor pillar serving as the channel is equal to the horizontal thickness of the recess formed in the opening of the first film. Therefore, by setting the thickness of the second film to 0.5 μm or less, the thickness of the semiconductor pillar can be reduced beyond the limits of microfabrication by photolithography and reactive ion etching. Therefore, similarly to the first invention, a fully depleted vertical MOS semiconductor device can be manufactured without being restricted by the limitations of microfabrication.

Further, the semiconductor pillar has a prismatic shape, and the opening inner wall surrounding the semiconductor pillar is a side wall 4 of the semiconductor pillar.
When the gate electrode is formed so that it is in contact with two of the surfaces that are opposite to each other and is spaced apart from the remaining two surfaces, and the gate electrode is provided on each of the remaining two surfaces, during operation after completion, Potentials can be applied independently to the gate electrodes on both sides of the semiconductor pillar. Therefore, the manufactured vertical MOS semiconductor device can be used in various operation modes.

0012

EXAMPLES The method for manufacturing a vertical MOS semiconductor device according to the present invention will be explained in detail below using examples.

FIGS. 1 to 3 show the manufacturing process of an embodiment of the first invention. In this example, the vertical M
An OS semiconductor device is manufactured.

First, as shown in FIG. 1(a), CVD (
A SiO2 film 2 is deposited as a first film on the surface of a p-type silicon substrate 1 to a predetermined thickness by chemical vapor deposition (chemical vapor deposition) or thermal oxidation.
will be established. Photolithography and reactive ion etching are performed to form a first opening A in the SiO2 film 2 that penetrates substantially perpendicularly to the surface of the substrate 1. The horizontal dimension of the opening A is 0.5 μm, which is the limit of microfabrication.

Next, as shown in the same figure (b), the above-mentioned Si
Arsenic ions are implanted through the opening A using the O2 film 2 as a mask. As a result, the inside of the substrate 1 (substrate 1
Depth R from the surface = 0.5 μm, width ΔR = 0.2 μm)
Then, a source region (first conductive region) 3 is formed.

Next, as shown in FIG. 4C, a SiO2 film 4 is deposited as a second film on the substrate 1 to a thickness of 50 nm by CVD. This SiO2 film 4 forms a recess 4a that covers the inner wall of the opening A. As will be described later, the thickness of the SiO2 film 4 is planned to be varied within a range that allows the formation of a recess (indentation) 4a.

Next, as shown in FIG. 1D, a tungsten film (hereinafter referred to as "W film") is deposited on the substrate 1 as a third film.
That's what it means. ) 5 to fill the inside of the recess 4a. After this, as shown in FIG. 2(e), etch back (W film 5
, etching the SiO2 film 4 at a constant rate),
While removing the portion existing in the flat portion of the W film 5,
A portion 5a existing within the recess 4a is left.

Next, as shown in FIG. 4(f), using the W film 5a left in the recess 4a as a mask, the SiO
2 films 2 and 4a are etched. While the SiO2 film 2 is completely removed, a portion 4b of the SiO2 film 4a under the mask 5a remains. Subsequently, the substrate 1 is etched to the depth of the source region 3. Thereby, a silicon pillar (semiconductor pillar) 1a, which is made of a part of the substrate 1 and is connected to the source region 3 and becomes a channel, is formed under the mask 5a. The thickness of the silicon pillar 1a is equal to the horizontal width of the mask 5a, and therefore equal to the horizontal opening size of the recess 4a.

Next, the W remaining on the silicon pillar 1a is
After removing the film 5a and the SiO2 film 4b, a SiO2 film 6 is deposited as a fourth film on the substrate 1, as shown in FIG. A second opening B surrounding the silicon pillar 1a is formed in the SiO2 film 6 by photolithography and reactive ion etching, and a gap is formed between the side wall of the silicon pillar 1a and the inner wall of the opening B. Form Δ.

Next, as shown in FIG. 3H, a gate insulating film 7 with a thickness of 10 nm is formed on the surface of the source region 3 in the opening B and the side wall (and top surface) of the silicon pillar 1a by thermal oxidation. form.

Next, as shown in FIG. 3(i), a W film 8 is deposited on the substrate 1 to a thickness of 0.1 μm by CVD to fill the gap Δ. As shown in FIG. 8(j), etching back is performed to form the gate electrode 8 within the gap Δ.
form a.

Finally, as shown in FIG. 4(j), arsenic ions are implanted into the surface of the substrate 1 using the SiO2 film 6 as a mask. Thereby, the drain region (second conductive region) 9 is formed on the upper part of the silicon pillar 1a, and the fabrication is completed (note that the source region 3 and the drain region 9 may be exchanged). .

According to this manufacturing method, the thickness of the silicon pillar 1a serving as the channel is finished to be equal to the horizontal opening dimension of the recess 4a shown in FIG. 1(c). That is, the thickness of the silicon pillar 1a is determined by the width of the first opening A formed by photolithography and reactive ion etching, and the width of the recess 4a that covers the inner wall of this opening A.
It is determined by the thickness of the SiO2 film 4 forming the . As already mentioned, the limit of microfabrication by photolithography and reactive ion etching is 0.
It is 5 μm. Therefore, by increasing the thickness of the SiO2 film 4 (limited to the range where the recess 4a is formed), it is possible to reduce the thickness of the silicon pillar 1a beyond the limits of microfabrication. . Therefore, a fully depleted vertical MOS semiconductor device can be manufactured without being restricted by the limitations of microfabrication.

As shown in FIG. 4, the inner wall of the second opening B may be processed to be spaced apart from the four side walls of the silicon column 1a, or as shown in FIG. The inner wall of the second opening B may be processed so that it is in contact with two of the four side walls of the silicon column 1a that are opposite to each other, but is spaced apart from the remaining two sides. In the example shown in FIG. 4, the gate electrode 8a is provided around the entire circumference of the silicon column 1a,
In the example shown in FIG.
It is provided only on the surface (the surface spaced apart from the inner wall of the opening B). In the latter case, during operation after completion, a potential can be applied independently to the gate electrodes 8a, 8a on both sides of the silicon pillar 1a. Therefore, the manufactured vertical MOS semiconductor device can be used in various operation modes.

FIGS. 6 to 9 show the manufacturing process of an embodiment of the second invention. In this example, the vertical M
An OS semiconductor device is manufactured.

First, as shown in FIG. 6A, a SiO2 film 12 is provided as a first film to a predetermined thickness on the surface of a p-type silicon substrate 11 by CVD or thermal oxidation. Photolithography and reactive ion etching are performed to form a first opening C in the SiO2 film 12 that penetrates substantially perpendicularly to the surface of the substrate 11. The horizontal dimension of the opening C is 0.5μ, which is the limit of microfabrication.
Let it be m.

Next, as shown in the same figure (b), the above-mentioned Si
Arsenic ions are implanted through the opening C using the O2 film 12 as a mask. As a result, a source region (first conductive region) 13 is formed on the surface of the substrate 11.

Next, as shown in FIG. 3C, a Si3N4 film 14 is deposited as a second film on the substrate 11 to a thickness of 50 μm by CVD. This Si3N4 film 1
4 forms a recess 14a that covers the inner wall of the opening C. As will be described later, the thickness of the Si3N4 film 14 is planned to be varied within a range that allows formation of the recesses (dents) 14a.

Next, as shown in FIG. 2D, a SiO2 film 15 is deposited as a third film on the substrate 11.
The inside of the recess 14a is filled. After that, as shown in FIG. 7(e), etchback (etching the SiO2 film 15 and Si3N4 film 14 at a uniform rate) is performed to remove the SiO2 film 15 and the Si3N4 film 14.
2 film 15, the portion of the Si3N4 film 14 existing in the flat portion is removed, while the recess 14a of the Si3N4 film 14 and the portion 15a of the SiO2 film 15 inside the recess 14a are left.

Next, as shown in FIG.
A portion of the 3N4 film 14 that constitutes the side wall of the recess 14a is selectively etched with respect to the SiO2 films 12 and 15a. The inner wall of the opening C of the SiO2 film 12 and the remaining S are etched and removed up to the surface of the substrate 11.
A pair of gaps Δ' are formed between the iO2 film 15a and the source region 13 is exposed.

Here, as shown in FIG. 3(g), heat treatment is performed to widen the source region 13 by about 0.1 μm both in the horizontal direction and in the depth direction (in the figure, the boundary before heat treatment is indicated by a broken line). 13').

Next, as shown in FIG. 8(h), a p-type silicon pillar 16 connected to the surface of the substrate 11 and serving as a channel is formed in the gap Δ' with a height of 0.3 μm by selective epitaxial growth. form it.

Next, as shown in FIG. 3(i), photolithography and chemical etching are performed to remove each of the films 12, 14b, 15a existing on the source region 13.
is selectively removed to form a second opening D surrounding the silicon pillar 16. That is, the horizontal dimension of the opening C is widened by 50 nm. As a result, the above gap Δ'
Increase the horizontal width of

Next, as shown in FIG. 5(j), the surface of the source region 13 within the opening D and the silicon pillar 1 are
A gate insulating film 17 is formed on the side walls (and top surface) of the gate electrode 6.

Next, as shown in FIG. 9(k), a W film 18 with a thickness of 0.1 μm is deposited on the substrate by CVD to fill the gap Δ'. As shown in FIG. 4(l), etchback is performed to form a gate electrode 18a within the gap Δ'.

Finally, as shown in FIG. 4(l), ions are implanted into the surface of the substrate 11 using the SiO2 film 12 left around the opening D as a mask. Thereby, a drain region (second conductive region) 19 is formed on the top of the silicon pillar 16 to complete the fabrication (note that the source region 13 and drain region 19 may be interchanged).

According to this manufacturing method, the thickness of the silicon pillar 16 serving as the channel is the same as that of the recess 14a shown in FIG. 6(c).
Finished with a thickness equal to the horizontal wall thickness. Therefore, the thickness of the Si3N4 film 14 constituting the recess 14a is set to 0.5
By setting the thickness to less than μm (possibly up to about 50 nm), the thickness of the silicon pillar 16 can be made thinner beyond the limits of microfabrication by photolithography and reactive ion etching. Therefore, similarly to the manufacturing method described above, a fully depleted vertical MOS semiconductor device can be manufactured without being restricted by the limitations of microfabrication.

[0038] Similarly to the previous example, the silicon pillar 1
6 and 16 have a prismatic shape, and the inner wall of the opening D surrounding the silicon pillars 16 and 16 is
It may be processed so that it is in contact with two of the four sides of the side walls that are opposite to each other, but is spaced apart from the remaining two sides. When the gate electrodes 18a are provided on each of the remaining two surfaces (however, the gate electrode 18a in the center
8a is provided commonly to the two channels. ), during operation after completion, a potential can be applied independently to the gate electrodes 18a, 18a on both sides of each of the silicon pillars 16, 16. Therefore, the manufactured vertical MOS semiconductor device can be used in various operation modes.

Note that FIGS. 10 and 11 show vertical MOS semiconductor devices manufactured by applying the two manufacturing methods described above to an SOI (silicon-on-insulator) substrate. In FIGS. 10 and 11, 31,
41 is a silicon substrate, and 36 and 46 are insulating layers. When an SOI substrate is used in this way, parasitic capacitance can be reduced, and high-speed operation is therefore possible.

[0040]

As is clear from the above, according to the method for manufacturing a vertical MOS semiconductor device according to the first aspect of the invention, the thickness of the semiconductor pillar serving as a channel is determined by the thickness of the semiconductor pillar formed within the opening of the first film. The finished size is equal to the opening size of the recess. In other words, the thickness of the semiconductor pillar is determined by the width of the opening formed in the first film by photolithography and reactive ion etching (the limit level of microfabrication) and the formation of the recess covering the inner wall of this opening. determined by the thickness of the second film. Therefore, by increasing the thickness of the second film within the range in which the recess is formed, the thickness of the semiconductor pillar can be made thinner beyond the limit of the fine processing. Therefore, a fully depleted vertical MOS semiconductor device can be manufactured without being restricted by the limitations of microfabrication.

According to the method for manufacturing a vertical MOS semiconductor device according to the second aspect of the invention, the thickness of the silicon pillar serving as the channel is equal to the thickness in the horizontal direction of the recess formed in the opening of the first film. Finished with equal thickness. Therefore, the thickness of the second film constituting the recessed portion is set to be 0.5 μm or less (50 μm or less).
The thickness of the silicon pillar can be reduced beyond the limits of microfabrication by photolithography and reactive ion etching. Therefore, similarly to the first invention, a fully depleted vertical MOS semiconductor device can be manufactured without being restricted by the limitations of microfabrication.

Further, the semiconductor pillar has a prismatic shape, and the inner wall of the opening surrounding the semiconductor pillar is a side wall 4 of the semiconductor pillar.
When the gate electrode is formed so that it is in contact with two of the surfaces that are opposite to each other and is spaced apart from the remaining two surfaces, and the gate electrode is provided on each of the remaining two surfaces, during operation after completion, Potentials can be applied independently to the gate electrodes on both sides of the semiconductor pillar. Therefore, the manufactured vertical MOS semiconductor device can be used in various operation modes.

[Brief explanation of drawings]

FIG. 1 is a process diagram illustrating a method for manufacturing a vertical MOS semiconductor device according to an embodiment of the first invention.

FIG. 2 is a process diagram illustrating a method for manufacturing a vertical MOS semiconductor device according to an embodiment of the first invention.

FIG. 3 is a process diagram illustrating a method for manufacturing a vertical MOS semiconductor device according to an embodiment of the first invention.

FIG. 4 is a perspective view showing a modification of the vertical MOS semiconductor device.

FIG. 5 is a perspective view showing a modification of the vertical MOS semiconductor device.

FIG. 6 is a process diagram illustrating a method for manufacturing a vertical MOS semiconductor device according to an embodiment of the second invention.

FIG. 7 is a process diagram illustrating a method for manufacturing a vertical MOS semiconductor device according to an embodiment of the second invention.

FIG. 8 is a process diagram illustrating a method for manufacturing a vertical MOS semiconductor device according to an embodiment of the second invention.

FIG. 9 is a process diagram illustrating a method for manufacturing a vertical MOS semiconductor device according to an embodiment of the second invention.

FIG. 10 is a diagram illustrating a vertical MOS semiconductor device manufactured by applying the first invention to an SOI substrate.

FIG. 11 is a diagram illustrating a vertical MOS semiconductor device manufactured by applying the first invention to an SOI substrate.

FIG. 12 is a process diagram illustrating a conventional method for manufacturing a vertical MOS semiconductor device.

FIG. 13 is a process diagram illustrating a conventional method for manufacturing a vertical MOS semiconductor device.

[Explanation of symbols]

1,11 Silicon substrate
1a, 16 Silicon pillar 2, 4, 6, 12, 15 SiO2 film
3, 13 Source region 4a, 14a recess
5, 5a, 8, 18 W film 7, 17 Gate insulating film
8a, 18a Gate electrode 9, 19 Drain region
A, C first opening

Claims (3)

[Claims] 1. A method for manufacturing a vertical MOS semiconductor device in which a channel is provided in a direction perpendicular to the surface of a semiconductor substrate, wherein a first film is provided with a predetermined thickness on the surface of the substrate, and photolithography and reactive・Performing ion etching to form a first opening that penetrates the first film substantially perpendicularly to the substrate surface; and using the first film as a mask, ions are etched through the first opening. forming a first conductive region to serve as a source or drain in the substrate at a predetermined depth from the surface of the substrate by implantation; depositing a second film on the substrate; forming a recess covering the inner wall of the opening with a second film, and embedding a third film made of a material that can be selectively etched with respect to the substrate and the first and second films in the recess; step, using the third film embedded in the recess as a mask, the first and second films existing around this mask are etched and removed, and then the substrate is etched with the third film embedded in the recess.
etching to the depth of the first conductive region to form a semiconductor pillar, which is made of a part of the substrate and is connected to the first conductive region and becomes a channel, under the mask; After removing the third and second films left on the substrate, a fourth film having an insulating property is deposited on the substrate, and photolithography and reactive ion etching are performed to form the fourth film. forming a second opening surrounding the semiconductor pillar in the film, forming a gap between a side wall of the semiconductor pillar and an inner wall of the opening; forming a gate insulating film on the side wall of the semiconductor pillar; forming a gate electrode in the gap between the semiconductor pillar side wall and the inner wall of the opening; and applying ions to the substrate surface using the fourth film as a mask. A method for manufacturing a vertical MOS semiconductor device, comprising the step of performing implantation to form a second conductive region to serve as a drain or a source above the semiconductor pillar. 2. A method for manufacturing a vertical MOS semiconductor device in which a channel is provided in a direction perpendicular to the surface of a semiconductor substrate, wherein a first film is provided with a predetermined thickness on the surface of the substrate, and photolithography and reactive・Performing ion etching to form a first opening that penetrates the first film substantially perpendicularly to the substrate surface; and using the first film as a mask, ions are etched through the first opening. A first implant is performed to form a source or drain on the surface of the substrate.
forming the first conductive region on the substrate; and forming the first conductive region on the substrate.
depositing a second film made of a material that can be selectively etched with respect to the film, and forming a recess covering the inner wall of the opening with the second film; depositing the second film on the substrate; After depositing a third film made of a material that can be selectively etched with respect to the film to fill the recess, etching back is performed to remove the third film that exists in the flat part of the third and second films. a step of removing a portion of the second film while leaving a portion of the recess of the second film and a portion of the third film within the recess;
The portion of the film that constitutes the side wall of the recess is the first and third film.
selectively etching and removing the film up to the substrate surface to form a pair of gaps between the inner wall of the opening of the first film and the remaining third film; 1
forming semiconductor pillars in the gap made of the same material as the substrate and connected to the surface of the substrate to form a channel; and performing photolithography and etching to expose the first conductive region. selectively removing each of the films existing on the region to form a second opening surrounding the semiconductor pillar to provide a gap between a side wall of the semiconductor pillar and an inner wall of the opening; forming a gate insulating film on the surface of the first conductive region in the opening and the side wall of the semiconductor pillar; forming a gate electrode in the gap between the semiconductor pillar side wall and the inner wall of the opening;
A step of implanting ions into the surface of the substrate using the first film left around the opening as a mask to form a second conductive region serving as a drain or a source on the top of the semiconductor pillar. A method for manufacturing a vertical MOS semiconductor device, characterized by: 3. The semiconductor column has a prismatic shape, and the inner wall of the opening surrounding the semiconductor column is in contact with two of the four side walls of the semiconductor column that are opposite to each other, while being spaced apart from the remaining two sides. 3. The method of manufacturing a vertical MOS semiconductor device according to claim 1, wherein the gate electrode is formed on each of the remaining two surfaces.