KR20080011488A - Method of manufacturing semiconductor device having multiple channels mos transistor - Google Patents

Abstract

A method for fabricating a semiconductor device including a multiple channel MOS transistor is provided to simplify an ion implantation process of a source/drain layer by forming a planarized source/drain layer on the upper surface of a semiconductor device without a facet. A preliminary active pattern(40) is formed on a semiconductor substrate(10) wherein a plurality of gate formation layers and a plurality of single crystal silicon layers are repeatedly stacked in the preliminary active pattern. A hard mask is formed on the preliminary active pattern. By using the hard mask, the preliminary active pattern is etched to the surface of the substrate to form an active channel pattern. A source/drain layer having a flat upper surface is formed in a portion removed in forming the active channel pattern. The plurality of gate formation layers are selectively etched to form a plurality of tunnels. A gate(50) fills the plurality of tunnels, surrounding the active channel pattern and protruding to the upper portion of the active channel pattern. The gate formation layer can be made of germanium or silicon germanium having etch selectivity with respect to the single crystal silicon layer.

Description

TECHNICAL FIELD A manufacturing method of a semiconductor device including a multi-channel MOS transistor.

1A is a perspective view illustrating an active pattern and an active channel pattern of a MOS transistor having multiple channels according to an embodiment of the present invention.

1B is a perspective view illustrating a gate electrode of a MOS transistor having multiple channels according to an embodiment of the present invention.

2 is a cross-sectional view of a MOS transistor having multiple channels according to an embodiment of the present invention.

3A to 3O are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4A through 4C are perspective views of respective stages of semiconductor device fabrication.

<Description of Symbols for Major Parts of Drawings>

10 semiconductor substrate 12 channel isolation region

14 gate forming layer 16 single crystal silicon layer

18: field area 20: gate hard mask

25: selective epitaxial single crystal film 25 ': planar selective epitaxial single crystal film

26 source / drain layer 30 silicon nitride film

34 oxide film spacer 36 active channel pattern

38: tunnel 40: active pattern

42: gate insulating film 44: first conductive film pattern

50: gate 52: second conductive film pattern

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a MOS transistor semiconductor device having multiple channels.

As the semiconductor device is highly integrated, the size of the device formation region, that is, the active region, is reduced, and the channel length of the MOS transistor formed in the active region is reduced. As the channel length of the MOS transistor decreases, the influence of the source and the drain on the electric field or potential in the channel region becomes remarkable. In addition, as the active region shrinks, the width of the channel decreases, resulting in a reverse narrow width effect in which a threshold voltage is reduced.

Accordingly, various methods for maximizing device performance while reducing the size of devices formed on a substrate have been researched and developed. Typical examples include a fin structure, a vertically depleted lean-channel TrAnsistor (DELTA) structure, a vertical transistor structure such as a gate all around (GAA) structure, and a multi-bridge channel transistor. transistor) structure.

For example, US Pat. No. 6,413,802 discloses a finned MOS transistor having a structure in which a plurality of parallel thin channel fins are provided between a source / drain region and a gate electrode extends over the top and sidewalls of the channel. have. According to the fin MOS transistor, gate electrodes are formed on both sides of the channel fin, and gate control is performed from both sides, thereby reducing the short-channel effect. However, in the fin-type MOS transistor, since a plurality of channel fins are formed in parallel along the width direction of the gate, an area occupied by the channel region and the source / drain region increases, and as the number of channels increases, source / drain junction capacitance is increased. There is a problem that increases.

Examples of the MOS transistor having the DELTA structure are described in US Patent No. 4,996,574 and the like. In the DELTA structure, the active layer forming the channel is formed to protrude vertically with a predetermined width. In addition, the gate electrode is formed to surround the vertically protruding channel region. Thus, the height of the protruding portion constitutes the width of the channel, and the width of the protruding portion forms the thickness of the channel layer. In the channel formed as described above, since both sides of the protruding portion can be used, the effect of doubling the width of the channel can be obtained, thereby preventing the narrow channel effect. In addition, when the width of the protruding portion is reduced, the depletion layers of the channels formed on both sides may overlap each other, thereby increasing channel conductivity.

However, when the MOS transistor of the DELTA structure is implemented on a bulk silicon substrate, the substrate should be processed while the substrate is processed so that the portion which will form a channel on the substrate is protruded and the protrusion is covered with an anti-oxidation film. At this time, if the oxidation is excessively performed, the portion connecting the protrusion forming the channel and the substrate main body is oxidized by oxygen diffused laterally from a portion not protected by the antioxidant film, thereby separating the channel and the substrate main body. As the channel is isolated by excessive oxidation, the thickness of the channel at the connection portion is narrowed, and the single crystal layer is stressed and damaged in the oxidation process.

On the other hand, when the DELTA structured MOS transistor is formed on a silicon-on-insulator (SOI) type substrate, the SOI layer is etched to have a narrow width to form a channel region, thereby causing problems due to excessive oxidation when using a bulk substrate. Disappears. However, when the SOI substrate is used, the width of the channel is limited by the thickness of the SOI layer. However, a fully depletion type SOI substrate has a limitation of use because the thickness of the SOI layer is only several hundreds of microseconds. .

On the other hand, in the MOS transistor of the GAA structure, an active pattern is typically formed of an SOI layer, and the gate electrode is formed so as to surround the channel region of the active pattern whose surface is covered with the gate insulating film. Therefore, effects similar to those mentioned in the DELTA structure can be obtained.

However, in order to implement the GAA structure, the buried oxide film under the active pattern is etched using an undercut phenomenon of isotropic etching to form the gate electrode to surround the active pattern in the channel region. In this case, since the SOI layer is used as the channel region and the source / drain region, the lower portion of the source / drain region as well as the lower portion of the channel region is removed during the isotropic etching process. Therefore, when the conductive film for the gate electrode is deposited, the parasitic capacitance is increased because the gate electrode is formed not only in the channel region but also under the source / drain region.

In addition, the lower portion of the channel region is horizontally etched in the isotropic etching process, so that the horizontal length (or width) of the tunnel to be filled with the gate electrode in a subsequent process is increased. Therefore, it is impossible to manufacture a MOS transistor having a gate length smaller than the width of the channel, and there is a limit in reducing the gate length.

As an alternative to this limitation, MOS transistors having a multi-bridge channel structure have been developed. In this case, the multi-bridge channel type MOS transistor forms an active channel pattern including a plurality of channels and tunnels passing through the channels, and includes a gate electrode formed to surround the plurality of channels while filling the tunnels. A source / drain region is formed to be connected to the plurality of channels. Therefore, even if the number of channels increases, it is possible to maintain a uniform source / drain junction capacitance, thereby improving the integration and speed of the device.

However, the fabricated multi-bridge channel type MOS transistor has a center-shaped source / drain, so that it is difficult to have a constant doping profile for ion implantation into the source / drain region, and the channel layer forming the multi-bridge is on top. As the length becomes shorter, the channel forming distance to the source / drain becomes longer toward the bottom, which affects the operation characteristics of the transistor. In addition, the source / drain regions are not flat and have a curved shape, which burdens subsequent deposition and photography processes.

An object of the present invention for solving the above problems is to provide a method of manufacturing a semiconductor device having a multi-channel having a planarized source / drain region.

A method of manufacturing a multi-channel semiconductor device of the present invention for achieving the above object of the present invention forms a preliminary active pattern in which a plurality of gate formation layers and a single crystal silicon layer are repeatedly stacked on each other on a semiconductor substrate. A hard mask is formed on the preliminary active pattern. The preliminary active pattern is etched to the surface portion of the substrate by using the hard mask to form an active channel pattern. A source / drain layer having a flat top surface is formed on a portion removed in the etching step of forming the active channel pattern. The plurality of gate forming layers are selectively etched to form a plurality of tunnels. A gate is formed on the active channel pattern while filling the plurality of tunnels to surround the active channel pattern. As a result, a semiconductor device including a MOS transistor having multiple channels is formed.

Preferably, the source / drain layer forms a selective epitaxial single crystal film while simultaneously supplying a silicon source gas and an etching gas to the side surface of the active channel pattern and the upper surface of the semiconductor substrate, and prevents the supply of the silicon source gas. It is formed by repeatedly performing an etching process for planarizing the top surface of the selective epitaxial single crystal film using an etching gas.

Accordingly, the present invention can fabricate a MOS transistor including a multi-channel having a source / drain layer planarized without a facet portion on the top surface, so that the transistor operating characteristics of the semiconductor device are kept constant, and subsequent deposition or photography processes are performed. Can be easily performed.

Hereinafter, a method of manufacturing a semiconductor device including multiple channels according to a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments, and those skilled in the art may implement the present invention in various other forms without departing from the technical spirit of the present invention. In the accompanying drawings, the dimensions of the substrate or structures are enlarged than actual for clarity of the invention.

1A is a perspective view illustrating an active pattern and an active channel pattern of a MOS transistor having multiple channels according to an embodiment of the present invention, and FIG. 1B is a gate electrode of the MOS transistor having multiple channels according to an embodiment of the present invention. It is a perspective view showing. 2 is a cross-sectional view of a MOS transistor having multiple channels according to an embodiment of the present invention.

Referring to FIG. 1A, an active pattern 40 is provided on a semiconductor substrate (not shown). The active pattern 40 includes an active channel pattern 36 in which a plurality of channels are formed in a vertical direction during transistor operation. Side surfaces of the active channel pattern 36 have a vertical shape.

In addition, the active pattern 40 may have a source / drain layer 26 having a flat surface parallel to the surface of the field region while the etched region between the active channel pattern 36 and the field regions (not shown) is buried. ).

The active channel pattern 36 is provided with a plurality of tunnels 38 for distinguishing each channel region. The active channel pattern 36 is doped with N or P type impurities, depending on the type of the transistor. For example, in the case of forming an N-type transistor, P-type impurities are lightly doped.

In the present exemplary embodiment, the active channel pattern 36 includes two tunnels 38 in which two lower gates are to be formed in order to form channels in a direction perpendicular to the substrate. However, the tunnel 38 may have one or three or more.

The source / drain layer 26 is doped with a low or high concentration of impurities of a type opposite to that of the doped impurities in the channel region. For example, in the case of forming an N-type transistor, the source / drain layer 26 is doped with N-type impurities.

Referring to FIGS. 1B and 2, the source / drain layers 26 may be embedded in the plurality of tunnels 38 so that a plurality of channels formed during transistor operation are formed in a horizontal direction across the source / drain region. The gate 50 is formed in between. In addition, the gate 50 is formed to protrude from an upper surface of the central portion of the active pattern 40.

Specifically, the gate 50 includes a gate insulating layer 42 provided on the inner surface of the tunnel 38 and the protruding upper surface of the active pattern 40. The gate insulating film 42 may be formed of a thermal oxide film or an ONO film. In addition, a first conductive layer pattern 44 formed of titanium nitride and a second conductive layer pattern 52 formed of tungsten to lower the gate resistance are included on the gate insulating layer 42.

A gate protruding from the gate 50 on the active pattern 40 is called an upper gate 50a, and a gate formed in the tunnel 38 inside the active pattern 40 is a lower gate 50b. It is called. Oxide film spacers 34 made of silicon oxide are provided on both side surfaces of the upper gate 50a.

The semiconductor substrate 10 may be used as silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), or silicon germanium-on-insulator (SGOI). In particular, the semiconductor substrate 10 is made of bulk silicon, which is advantageous in terms of cost reduction and process progress.

When the semiconductor substrate 10 is used as bulk silicon, the channel isolation region 12 is provided on the substrate under the tunnel 38 positioned at the bottom of the active pattern 40. The channel isolation region 12 is doped with a high or low concentration of impurities opposite to that of the source / drain regions of the transistor.

The active channel pattern 36 and the source / drain 26 are both formed of a single crystal semiconductor film, preferably a silicon film.

In the MOS transistor of the present invention, the source / drain has a constant doping profile in a direction perpendicular to the direction in which the channel is formed during transistor operation. Therefore, even if the number of channels increases, it is possible to maintain a uniform source / drain junction capacitance. Therefore, it is possible to improve the speed of the device by increasing the current while minimizing the junction capacitance.

In addition, the source / drain layer formed to be buried between the field regions can be formed to be planarized so that the source / drain can be doped with a constant doping profile and the same length of the single crystal silicon layers forming the multi-bridge can be formed. Can maintain a uniform source / drain junction capacitance. The process profile of the deposition and photography process which is then performed on the source / drain layer can be improved.

3A to 3O are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention, and FIGS. 4A to 4C are perspective views according to each step.

Referring to FIG. 3A, a semiconductor substrate 10 is prepared. The semiconductor substrate 10 is made of silicon (Si), silicon germanium (SiGe), silicon-on-insulator (SOI), or silicon germanium-on-insulator (SGOI).

The channel isolation region 12 is formed by implanting impurities of high or low concentration into the surface of the substrate 10. The impurities having a high concentration are doped with a high or low concentration of impurities opposite to those of the source and drain regions of the transistor to be formed. Therefore, the operation of the base transistor can be prevented and the short channel effect can be prevented.

The plurality of gate forming layers 14 and the plurality of single crystal silicon layers 16 are repeatedly stacked on the substrate 10. First, the first gate forming layer 14a is formed on the substrate 10, and the first single crystal silicon layer 16a is formed on the first gate forming layer 14a. Subsequently, a second gate forming layer 14b and a second single crystal silicon layer 16b are formed on the first single crystal silicon layer 16a. In addition, a gate forming layer is formed in the uppermost layer.

The single crystal silicon layer 16 and the gate forming layer 14 are formed of single crystal semiconductor materials having an etch selectivity with respect to each other. Preferably, the single crystal silicon layer 16 is formed of a single crystal silicon film having a thickness of about 300 GPa, and the gate forming layer 14 is formed of a single crystal germanium film or a single crystal silicon-germanium film having a thickness of about 300 GPa. The single crystal silicon layer and the gate forming layer can be formed by an epitaxial growth method.

In addition, the thickness and the number of repetitions of the single crystal silicon layer 16 and the gate forming layer 14 may be freely adjusted according to the purpose of the transistor to be made. In this case, the channel doping may be performed in advance by forming the single crystal silicon layer 16 as a doped single crystal silicon film.

Referring to FIG. 3B, the single crystal silicon layer 16 and the gate forming layer 14 are etched and subsequently etched to the lower end of the channel isolation region 12 of the substrate 10 to form a device isolation trench. Next, an oxide film is deposited by a chemical vapor deposition (CVD) method so as to fill the trench, and the oxide film is exposed by an etch back or chemical mechanical polishing (CMP) process until the top surface of the single crystal silicon layer 16b is exposed. The planarization separates the active region and the field region 18. By the above process, a preliminary active pattern in which the single crystal silicon layer 16 and the gate forming layer 14 are stacked is formed. The active region is formed in an island pattern.

Referring to FIG. 3C, an etch stop layer and a dummy gate layer are sequentially stacked on the single crystal silicon layer 16.

The etch stop layer is formed by depositing an insulating material, preferably silicon nitride, which can be selectively removed with respect to the dummy gate layer, to a thickness of about 100 to 200 microns. The etch stop layer prevents the underlying single crystal silicon layer 16b from being etched when the dummy gate layer is etched in a subsequent process. The dummy gate layer is used to define a gate region, and is formed by depositing silicon oxide to a thickness of 1000 to 3000 GPa.

Subsequently, the dummy gate layer and the etch stop layer are sequentially dry-etched by a photolithography process to form a gate hard mask 20 including the etch stop layer pattern 20a and the dummy gate pattern 20b. The dry etching is performed such that the etch stop layer and the dummy gate layer are etched with a predetermined slope. Accordingly, the side surface of the gate hard mask 20 including the etch stop layer pattern and the dummy gate pattern 20b may be inclined. Specifically, the cross section of the gate hard mask 20 is formed so that the upper side has a trapezoidal shape smaller than the lower side.

Referring to FIG. 3D, the preliminary active pattern is etched using the gate hard mask 20 as an etch mask. The etching process is performed to be exposed below the channel isolation region 12 of the semiconductor substrate. As a result, the preliminary active channel pattern 22 is formed.

Referring to FIG. 3E, the plurality of single crystal silicon layer patterns 16a 'and 16b' and the gate forming layer patterns 14a 'and 14b' exposed to the side surface of the preliminary active channel pattern 22 are partially isotropically etched. As a result, an active channel pattern 24 having a line width smaller than that of the preliminary active channel pattern 22 is formed. Since the channel length is determined by the etching process, the etching process is also called a channel trimming process.

In order for the side profile of the active channel pattern 24 to be formed vertically, the sidewall profile of the active channel pattern 24 must be performed under a condition in which the etch selectivity between the single crystal silicon layers 14a ″ and 14b ″ and the gate forming layers 16a ″ and 16b ″ is little. Specifically, the etching process may be performed by chemical dry etching using radicals of the etching gas. By performing the etching process, the active channel pattern 24 having a line width smaller than the pattern size that can be formed by the photolithography process can be formed.

Referring to FIG. 3F, a selective epitaxial single crystal layer 25 is formed while simultaneously supplying a silicon source gas and an etching gas to the side surface of the active channel pattern 24 and the upper surface of the semiconductor substrate 10.

In this case, the line width of the active channel pattern 24 is smaller than the lower line width of the gate hard mask 20. That is, since the mask is masked by the gate hard mask 20 on the active channel pattern 24, the active epitaxial single crystal layer 25 grows on the side of the active channel pattern 24. The growth of the film in the direction parallel to the side surface of the channel pattern 24 is suppressed, and most of the growth occurs in the direction perpendicular to the side surface of the active channel pattern 24. However, the active channel pattern 24 is further grown on the side of the active channel pattern 24, and the portion facing the field region 18 forms a facet region in which growth is delayed due to difficulty in supplying a silicon source or the like.

As described above, the selective epitaxial single crystal layer 25 having a center shape has difficulty in implanting ions to form a source / drain thereafter, and the channel length of the active channel pattern 24 may be changed to vary. have. Therefore, the selective epitaxial single crystal film 25 should be grown evenly while suppressing the growth of the active channel pattern 24 to the side surface.

Referring to FIG. 3G, a planar selective epitaxial single crystal film 25 ′ without a facet portion is formed by blocking the supply of the silicon source gas and performing an etching process on the selective epitaxial single crystal film 25 using the etching gas. To form. As an example, the etching process may include a dry etching process. The selective epitaxial single crystal layer 25 grows in a horizontal direction at the point where it meets the sidewall of the active channel pattern 24, and the growth is suppressed at the facet point where the field region 18 is interviewed. The dry etching process is performed until the top surface is planarized. As a result, the line width of the active channel pattern 24 remains the same at the top and the bottom.

Referring to FIG. 3H, the active channel pattern 24 is etched between the active channel pattern 24 and the field region 18 by repeatedly forming the planar selective epitaxial single crystal layer 25 ′. Form a source / drain layer 26 having a flat top surface at the site removed at. That is, after the selective epitaxial growth process is continuously performed on the planar selective epitaxial single crystal film 25 ′, the process of dry etching to planarize the upper surface is repeated to the upper surface of the field region 18. As a result, a source / drain layer 26 having a constant width and a flat top surface is formed at the top and the bottom.

 Subsequently, the planarized source / drain layer 26 is doped with ionic impurities to form a source / drain having a uniform impurity concentration on the entire surface.

Referring to FIG. 3I, a silicon nitride layer 30 is formed to completely fill the gate hard mask 20 on the source / drain layer 26 and the field region 18. Subsequently, the silicon nitride layer 30 is chemically mechanically polished to expose the upper surface of the gate hard mask 20, that is, the dummy gate pattern.

Referring to FIG. 3J, the dummy gate pattern 20b is selectively removed, and then the etch stop layer pattern 20a is etched to form a gate trench 32 defining a region in which an upper gate is to be formed. Since the etch stop layer pattern 20a having the high etching selectivity with the dummy gate pattern 20b is formed, the recess of the lower single crystal silicon layer 16b ″ may be minimized during the etching process.

The cross section of the hard mask pattern 20 including the etch stop layer pattern 20a and the dummy gate pattern 20b has a trapezoid having a larger size of a lower side than an upper side. Therefore, the gate trench 32 has a shape where the upper portion of the trench is narrower than the lower portion of the trench.

Referring to FIG. 3K, a silicon oxide layer is formed on an inner surface of the gate trench 32 and an upper surface of the silicon nitride layer 30. Subsequently, the silicon oxide film is anisotropically etched to form internal oxide spacers 34 on the sidewalls of the gate trench.

Since the internal oxide spacer 34 reduces the opening width of the gate trench 32, the upper gate length of the transistor is reduced according to the thickness of the internal oxide spacer 34. In addition, since the lower portion of the inner oxide spacer 34 has a thicker shape than the upper portion thereof, the inner sidewall of the upper gate trench is close to the vertical by the inner oxide spacer 34.

Therefore, an upper gate having a gate length similar to the lower gate length may be formed by the internal oxide spacer 34 through a subsequent process, and the upper gate side may be formed to be close to the vertical.

When the impurity doping process is not performed on the single crystal silicon layers 16a ″ and 16b ″ in the previous process, the gate trench 32 is formed by performing an ion implantation process after forming the internal oxide spacer 34. Impurities are doped into the single crystal silicon layers 16a "and 16b" formed below. 4A is a perspective view after performing the above-described processes. Field regions 18 are exposed on the front and rear surfaces of the active channel pattern.

3L, 4B, and 4C, a field region exposed on the bottom surface of the gate trench 32 is selectively etched to expose the front and rear surfaces of the active channel pattern 24. (FIG. 4B)

Subsequently, the plurality of gate forming layer patterns 14a "and 14b" are selectively removed by an isotropic etching process using an etchant having an etching selectivity with respect to silicon and silicon germanium, thereby forming a plurality of gates in the active channel pattern 24. Two tunnels 38 are formed. (FIG. 4C)

By the above process, the active channel pattern 24 including the plurality of tunnels 38 in the vertical direction on the substrate 10 and the source / drain layer 26 on both sides of the tunnel 38 are provided. An active pattern 40 having a structure is formed. The active pattern 40 is buried between neighboring field regions 18 to have a flat top surface with the field region 18.

Referring to FIG. 3M, a thermal oxidation process is performed to form a gate insulating layer 42 on the inner surfaces of the plurality of tunnels 38 and the gate trench 32.

Here, before forming the gate insulating layer 42, a high temperature heat treatment may be performed in a hydrogen (H ₂ ) or argon (Ar) atmosphere to improve the surface roughness of the exposed films. In addition, the gate insulating layer 42 may be formed of a silicon oxide film or silicon oxynitride.

Referring to FIG. 3N, a first conductive layer pattern 44 is formed to surround the plurality of tunnels 38 while filling the plurality of tunnels 38, etched field regions, and gate trenches 32. In this case, the first conductive layer pattern 44 is formed to partially fill the gate trench 32 while sufficiently filling the plurality of tunnels 38. A second conductive layer pattern 52 made of tungsten is formed on the first conductive layer pattern 44 of the gate trench 32. By the above process, the gate 50 including the gate insulating film 42, the first conductive film pattern 44, and the second conductive film pattern 52 is formed.

Specifically, titanium nitride is chemically vapor deposited to sufficiently fill the plurality of tunnels 38, the etched field region 18, and the gate trench 32 to form a first conductive layer. The first conductive layer may fill the tunnel 38 and the lower portion of the gate trench 32 by performing an entire surface etching process on the deposited first conductive layer to expose the upper portion of the gate trench 32. The film pattern 44 is obtained.

The gate 50 is completed by forming a second conductive film to sufficiently fill the upper portion of the exposed gate trench 32, and chemically mechanical polishing to obtain a second conductive film pattern 44.

When the process is performed, the first conductive layer pattern 44 and the second conductive layer penetrating the active channel pattern 24 and protruding from the active channel pattern 24 while filling the plurality of tunnels 38 are formed. The film pattern 52 is formed.

A gate formed on the active pattern 40 is called an upper gate 50a, and a gate penetrating through the active pattern 40 is called a lower gate 50b. In this case, the second conductive layer pattern 52 made of tungsten formed on the upper gate 50a reduces the resistance of the upper gate 50a.

Referring to FIG. 3O, all of the exposed silicon nitride layer 30 is removed.

By the above process, an active pattern 40 is provided on the substrate 10, and lower gates 50b automatically aligned in the vertical direction are provided in the active pattern 40, and an upper surface of the active pattern 40 is provided. The upper gate 50a is provided. An oxide spacer 34 is formed on a side of the upper gate 50a.

After removing the silicon nitride layer 30, a highly doped impurity doping process may be further performed under the surface of the source / drain layer 26.

According to the method, as the dry etching process is performed, the selective epitaxial single crystal layer may be excessively grown or not grown in a predetermined region, thereby minimizing bending at the facet region. Therefore, the shape of the source and drain layers can be prevented from being poor. In addition, since the side profile of the active pattern is close to the vertical, the line width of the active channel pattern is constant, and a titanium nitride film having a uniform thickness can be formed. Therefore, the resistance of the source drain can be minimized.

According to the method of manufacturing the semiconductor device having the multi-channel according to the preferred embodiment of the present invention as described above, it is possible to form a planarized source / drain layer without a facet portion on the upper surface. Therefore, the ion implantation process of the source / drain layer can be simplified and the process margin can be improved.

In addition, the MOS transistor including multiple channels having the planarized source / drain layer has a constant channel line width formed between the source and the drain so that the resistance between the source and the drain becomes constant, thereby reducing the current difference between each channel. have. Therefore, the transistor operating characteristics of the semiconductor device including the MOS transistor are kept constant, and subsequent deposition, photography, and polishing processes can be easily performed.

While the foregoing has been described with reference to preferred embodiments of the present invention, those skilled in the art will be able to variously modify and change the present invention without departing from the spirit and scope of the invention as set forth in the claims below. It will be appreciated.

Claims (13)

Forming a preliminary active pattern in which a plurality of gate forming layers and a single crystal silicon layer are repeatedly stacked on each other on a semiconductor substrate; Forming a hard mask on the preliminary active pattern; Etching the preliminary active pattern to a surface portion of the substrate using the hard mask to form an active channel pattern; Forming a source / drain layer having a flat top surface on a portion removed in the etching step of forming the active channel pattern; Selectively etching the plurality of gate forming layers to form a plurality of tunnels; And And filling the plurality of tunnels, surrounding the active channel pattern, and forming a gate protruding above the active channel pattern. The method of claim 1, wherein the gate forming layer is formed of germanium or silicon-germanium having an etching selectivity with respect to the single crystal silicon layer. The method of claim 1, wherein the source / drain layer, Forming a selective epitaxial single crystal film while simultaneously supplying a silicon source gas and an etching gas to a side surface of the active channel pattern and an upper surface of a semiconductor substrate; And And performing an etching process to stop the supply of the silicon source gas and to planarize the top surface of the selective epitaxial single crystal film using the etching gas. The semiconductor of claim 1, further comprising forming a channel isolation region on the surface of the semiconductor substrate under the gate forming layer at the lowermost level by doping impurities of a type opposite to the source and the drain at a high concentration. Method of manufacturing the device. The method of claim 1, wherein the preliminary active pattern, Repeatedly laminating a gate forming layer and a single crystal silicon layer on the substrate; Forming a device isolation trench defining a field region by etching the stacked gate forming layer, the single crystal silicon layer, and the field portion of the substrate to a predetermined depth; And And forming a field oxide film in the device isolation trench. The method of claim 1, wherein the hard mask has a lower width than the upper width of the pattern. The method of claim 6, wherein the hard mask, Stacking an etch stop layer and a dummy gate layer on the preliminary active pattern; And And diagonally etching the dummy gate layer and the etch stop layer so that the side surface of the hard mask pattern has an inclination with respect to an upper surface thereof. The method of claim 1, prior to forming a plurality of tunnels through which the plurality of gate forming layers are selectively etched through. Forming a silicon nitride film to fill the active channel pattern, the source / drain layer, and the hard mask; Planarizing the silicon nitride film to expose the hard mask surface; Selectively removing the hard mask; Forming a spacer on a side portion of the trench formed by removing the hard mask from a material having an etching selectivity with respect to the silicon nitride film; And Selectively removing the field region exposed on the bottom surface of the trench from which the hard mask has been removed, and exposing the plurality of gate forming layers to the outside. The method of claim 8, wherein the forming of the gate comprises: Forming a first conductive layer pattern filling a lower portion of the trench while sufficiently filling the tunnels; And And forming the second conductive film pattern filling the upper portion of the trench to complete the gate. 10. The method of claim 9, further comprising removing the silicon nitride film after completing the gate. The method of claim 1, further comprising trimming the etched active channel pattern to have a smaller width than the width of the lower portion of the hard mask. The method of claim 11, wherein the trimming process is performed by isotropic etching under a condition in which an etch selectivity is substantially the same between the plurality of single crystal silicon layers and the plurality of gate formation layers. The method of claim 11, wherein the trimming process is performed by a chemical dry etch process.

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