KR20070048465A - Method of manufacturing schottky barrier semiconductor device having multi-channel - Google Patents

Abstract

A method of forming a Schottky barrier semiconductor device having multiple channels is disclosed. An isolation layer is formed on a semiconductor substrate in which a sacrificial layer and a channel layer are alternately stacked. A sacrificial gate layer is formed and a stacked channel pattern is formed to expose the sacrificial gate pattern and the semiconductor substrate. The source / drain is formed of a metal silicide or metal of a certain thickness so as to surround the exposed semiconductor substrate and the side surface of the stacked channel pattern. A gate mask layer is formed to completely fill the sacrificial gate pattern, the sacrificial gate pattern is removed, and a recess is formed in the device isolation layer using the gate mask layer as a mask to expose side surfaces of the stacked channel pattern. After removing the sacrificial layer through the exposed side surface of the stacked channel pattern, the gate electrode is formed by filling the portions where the sacrificial gate pattern is removed, the recesses and the sacrificial layer of the device isolation layer with conductive layers.

Multi-Channel, Schottky Barrier, Channel Layer, Source / Drain

Description

Schottky Barrier Semiconductor Device Having Multi-Channel

1 is a cross-sectional view for explaining the structure of a conventional multi-channel MOS transistor.

2A through 2K are cross-sectional views illustrating a process of fabricating a Schottky barrier MOS transistor having multiple channels according to an embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a process of metal siliciding a silicon film for source / drain after a gate electrode is formed during the manufacture of a Schottky barrier MOS transistor having a multi-channel according to another embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 112 sacrificial layer

114: channel layer 110: laminated channel pattern

120: device isolation film 132, 132a: etching prevention film

134, 134a: sacrificial gate film 136: hard mask film

140: etching region 152: silicon film

152 metal silicide film 145 hard mask layer

160: gate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method of manufacturing a CMOS transistor having multiple channels.

As the semiconductor device is highly integrated, the size of the active region is reduced, thereby reducing the channel length of the MOS transistor formed in the active region. If the channel length of the transistor is reduced, a short channel effect occurs.

One of the transistors for improving device performance while reducing the size of transistors is a MOS transistor having a gate all around (GAA) structure. The multichannel MOS transistor of the GAA type has a multichannel in which a plurality of horizontal channel layers are stacked in a direction perpendicular to the substrate surface and a gate electrode surrounds the channel layer. The MOS transistor is formed by alternately repeatedly stacking two different epitaxial layers having an etching selectivity on a substrate, and removing one of the two epitaxial layers to form a plurality of horizontal channel regions. A gate electrode is formed in the removed portion. Therefore, the multi-channel MOS transistor can reduce the area occupied by the channel region and the source / drain region, thereby improving the integration degree, and preventing the increase of parasitic capacitance, thereby improving the operation speed.

1 is a cross-sectional view for explaining the structure of a conventional multi-channel MOS transistor. Referring to FIG. 1, a gate electrode 60 and a channel layer 14 are formed in multiple layers between the source / drain 50 on the semiconductor substrate 10. The gate electrode 60 is also formed in the device isolation layer 20, so that the channel layer 14 formed in multiple layers has a structure in which the top, bottom, front, and back are surrounded by the gate electrode 60. Between the gate electrode 60 on the source / drain 50, a silicon nitride film 45 used as a mask film is formed.

However, a MOS transistor having multiple channels as shown in FIG. 1 has a limitation in forming a source / drain having the same electrical characteristics by ion implantation regardless of the depth of the channel layer. That is, the concentration of the impurity of the source / drain on the lower channel is formed lower than the concentration of the impurity of the source / drain on the upper channel, so that the resistance is changed and accordingly, the magnitude of the saturation current is smaller. In order to increase the impurity concentration of the source / drain in the lower channel, increasing the impurity diffusion in the depth direction simultaneously impurity diffuses in the channel direction, making it difficult to control the short channel effect.

An object of the present invention is to form a source / drain that has uniform electrical characteristics regardless of the depth of a channel layer in a semiconductor device having multiple channels.

In order to achieve the above technical problem, in the method of manufacturing a Schottky barrier semiconductor device according to an embodiment of the present invention, the sacrificial layer and the channel layer are alternately formed on the semiconductor substrate at least one or more times. An isolation layer defining an active region is formed on the semiconductor substrate in which the sacrificial layer and the channel layer are alternately formed. A sacrificial gate pattern is formed on the semiconductor substrate on which the device isolation layer is formed. The sacrificial gate pattern is used as a mask, and the sacrificial layer, the channel layer, and the semiconductor substrate are etched to form a stacked channel pattern in which a pair of opposing first side surfaces are exposed, and a portion of the semiconductor substrate is exposed. A silicon film serving as a source / drain is formed to surround the exposed semiconductor substrate and the exposed first side surface of the stacked channel pattern with a predetermined thickness. The entire silicon film is metal silicided. A first insulating layer is formed on the semiconductor substrate on which the silicon film is formed to completely fill the sacrificial gate pattern. The sacrificial gate pattern is removed, and the device isolation layer is etched using the first insulating layer as a mask to expose a pair of opposing second side surfaces of the stacked channel pattern to form a gate recess. The sacrificial layer of the stacked channel pattern is selectively removed to form a gate tunnel. The gate recess and the gate tunnel are filled with a conductive layer to form a gate electrode.

In order to achieve the above technical problem, the method for manufacturing a Schottky barrier semiconductor device according to another embodiment of the present invention alternately forms a sacrificial layer and a channel layer on the semiconductor substrate at least one or more times. An isolation layer defining an active region is formed on the semiconductor substrate in which the sacrificial layer and the channel layer are alternately formed. A sacrificial gate pattern is formed on the semiconductor substrate on which the device isolation layer is formed. Using the sacrificial gate pattern as a mask, the sacrificial layer, the channel layer, and the semiconductor substrate are etched to form a stacked channel pattern in which a pair of opposing first side surfaces are exposed, and a portion of the semiconductor substrate is exposed. A silicon film serving as a source / drain is formed to surround the exposed semiconductor substrate and the exposed first side surface of the stacked channel pattern with a predetermined thickness. A first insulating layer is formed on the semiconductor substrate on which the silicon film is formed to completely fill the sacrificial gate pattern. The sacrificial gate pattern is removed, and the device isolation layer is etched using the first insulating layer as a mask to expose a pair of opposing second side surfaces of the stacked channel pattern to form a gate recess. The sacrificial layer of the stacked channel pattern is selectively removed to form a gate tunnel. The gate recess and the gate tunnel are filled with a conductive layer to form a gate electrode. The first insulating layer is removed from the semiconductor substrate on which the gate electrode is formed to expose the silicon layer. The entire exposed silicon film is metal silicided.

In the present invention, the channel layer and the sacrificial layer is preferably formed of a material having an etch selectivity with respect to each other, the channel layer epitaxially grow single crystal silicon, the sacrificial layer is monocrystalline germanium or single crystal silicon germanium Can be grown epitaxially.

The sacrificial gate pattern may be formed of a silicon oxide layer, and the gate electrode may be formed of silicon or titanium nitride, tungsten or tantalum nitride.

According to the present invention, a transistor having uniform electrical characteristics can be formed regardless of the depth of the channel layer.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art.

2A through 2K are cross-sectional views illustrating a process of fabricating a Schottky barrier MOS transistor having multiple channels according to an embodiment of the present invention.

Referring to FIG. 2A, at least a sacrificial layer 112 for providing a space in which a gate electrode is to be formed in a semiconductor substrate 100 made of a silicon single crystal and at least a channel layer 114 for forming a channel of a transistor are alternately provided. It is formed two times or more. In this embodiment, the sacrificial layer 112 and the channel layer 114 are alternately formed twice so that the channel layer 114 becomes two layers.

The sacrificial layer 112 and the channel layer 114 are preferably a single crystal semiconductor film having an etching selectivity under predetermined etching conditions. For example, the channel layer 114 may be formed of single crystal silicon, and the sacrificial layer 112 may be formed of single crystal silicon germanium. The sacrificial layer 112 and the channel layer 114 can be grown epitaxially.

Referring to FIG. 2B, a device isolation layer 120 is formed next to separate the transistor. In this embodiment, the device isolation layer 120 is formed by shallow trench isolation (STI) using silicon oxide as an insulating material.

Referring to FIG. 2C, an etch stop layer 132, a sacrificial gate layer 134, and a hard mask layer 136 are formed on the semiconductor substrate 100 on which the device isolation layer 120 is formed. The sacrificial gate layer 134 may be formed of a silicon oxide layer, and the etch stop layer 132 and the hard mask layer 136 may be formed of a silicon nitride layer having an etching selectivity with a silicon oxide layer of the sacrificial gate layer 134. It is preferable.

Referring to FIG. 2D, the hard mask layer 136 is patterned by photolithography to form a hard mask pattern (not shown), and the sacrificial gate layer 134 is etched using the hard mask pattern as a mask to form a sacrificial gate pattern ( 134a). In this case, the etch stop layer 132 prevents the device isolation layer 120 from being etched when the sacrificial gate pattern 134a is formed.

Referring to FIG. 2E, a layer formed by removing the exposed etch stop layer 132 and etching a portion of the sacrificial layer 112a, the channel layer 114a and the semiconductor substrate 100 using the sacrificial gate pattern 134a as a mask. The channel pattern 110 and the etching space 140 are prepared.

Referring to FIG. 2F, a material to be a source / drain is formed on the semiconductor substrate 100 exposed in the etching space 140 and on the side surface of the stacked channel pattern 110. For example, the single crystal silicon film 150 may be selectively epitaxially grown to form metal silicide. In this case, the single crystal silicon layer 150 is not formed to fill the entire etching space 140, but is formed to have a predetermined thickness on the semiconductor substrate 100 and on the side surface of the stacked channel pattern 110. This is because when the single crystal silicon film 150 is formed in the entire etching space 140, the entire single crystal silicon film 150 may be hardly metal silicided.

Referring to FIG. 2G, the entire single crystal silicon film 150 is metal silicided to form a source / drain 152 of metal silicide. For example, cobalt is deposited on the resultant shown in FIG. 2F and heat-treated to selectively cobalt silicide the single crystal silicon film 150, and then the remaining cobalt is removed to form a source / drain 152 of cobalt silicide. have. When the single crystal silicon film 150 is grown and the metal silicide is formed in the entire etching space 140, only a part of the single crystal silicon film 150 is metal silicided, and thus an ion implantation process is required to lower the resistance. However, when the entire source / drain 152 formed to a predetermined thickness is formed of metal silicide as in the present invention, a Schottky barrier is formed between the metal silicide constituting the source / drain region 152 and the channel layer 114a. Schottky barrier transistors can be constructed. Therefore, there is no need to proceed with the ion implantation process separately. If the ion implantation process is omitted, the short channel effect due to diffusion of impurities in the source / drain can be prevented, which is advantageous for scale reduction of the device.

Meanwhile, when the source / drain material is formed of a metal such as tungsten or aluminum, the entire etching space 140 may be filled with a metal material. In this case, it is because a process for metal silicideization is not necessary.

Referring to FIG. 2H, the gate mask layer 145 is formed in the etching space 140 in which the source / drain 152 is formed. Since the sacrificial gate pattern 134a is to be selectively removed after the gate mask layer 145 is formed, a material having an etching selectivity with the sacrificial gate pattern 134a should be used. In the exemplary embodiment of the present invention, a silicon nitride film is preferably used. . The gate mask layer 145 may be formed by depositing a silicon nitride layer such that the etching space 140 is completely filled, and then chemically mechanical polishing the exposed surface of the sacrificial gate pattern 134a.

Referring to FIG. 2I, after the silicon oxide layer of the sacrificial gate pattern 134a is selectively removed, the etch stop layer 132a is removed. The device isolation layer 120 is further etched using the gate mask layer 145 as a mask to provide a gate recess 150 in which a gate pattern is to be formed. Since the gate recess 150 is lowered into the device isolation layer 120, the stacked channel pattern 110 on the side contacting the device isolation layer 120 is exposed by the gate recess 150.

Referring to FIG. 2J, the sacrificial layer 112a in the stacked channel pattern 110 is removed through an isotropic etching process. The channel layer 114a remains in the shape of a plate above and below the space 112b from which the sacrificial layer 112a is removed.

Referring to FIG. 2K, a gate insulating layer (not shown) is formed on an exposed surface of the channel layer 114a and a gate electrode 160 is formed in the space 112b from which the gate recess 150 and the sacrificial layer are removed. . The gate insulating layer (not shown) may be formed by thermal oxidation of the channel layer 114a or through a deposition process, and a high dielectric constant material such as ZrO ₂ or HfO ₂ may be used as the gate insulating layer. The gate electrode is deposited by depositing a conductive film, such as a doped polysilicon film, so that the gate recess 150 and the space 112b from which the sacrificial layer is removed are completely filled, and then planarize the gate mask film 145 through the CMP process. Can be formed.

According to another embodiment of the present invention, when the source / drain is formed of the metal silicide, after the epitaxial growth of the single crystal silicon, the silicon may be immediately silicided without forming the gate silicide. In this case, the process up to the formation of the gate electrode is as described with reference to FIGS. 2A to 2K, except that the process does not go through the metal silicide process of the silicon film for the source / drain described in FIG. 2G. 3A to 3D are cross-sectional views illustrating a process of metal silicideizing a silicon film for a source / drain after forming a gate electrode. 3A is a cross-sectional view of a state in which the gate electrode 160 is formed. 3B is a state in which the gate mask layer 145 is removed to silicide the silicon layer 150 for the source / drain, and FIG. 3C is a state in which the source / drain 152 is formed by metallizing the silicon layer. . 3D is a step of forming an insulating film 147 after silicidating the silicon film.

As mentioned above, the present invention has been described in detail through specific embodiments, but the present invention is not limited thereto, and modifications or improvements thereof may be made by those skilled in the art within the technical spirit of the present invention.

According to the present invention, the ion implantation process for source / drain formation can be omitted by forming the entire source / drain region of metal silicide or metal in a semiconductor device having multiple channels. Therefore, since the ion implantation is not uniformly performed to the source / drain of the lower channel among the multiple channels, the problem of reducing the saturation current in the lower channel can be solved. On the other hand, the short channel effect due to the diffusion of the ionic impurities can be prevented and the high temperature process for activating the ionic impurities is omitted, thereby enabling a low temperature process for forming the metal gate.

Claims (9)

Alternately forming at least one sacrificial layer and a channel layer on the semiconductor substrate; Forming an isolation layer defining an active region on the semiconductor substrate in which the sacrificial layer and the channel layer are alternately formed; Forming a sacrificial gate pattern on the semiconductor substrate on which the device isolation layer is formed; Etching the sacrificial layer, the channel layer and the semiconductor substrate using the sacrificial gate pattern as a mask to form a stacked channel pattern exposing a pair of opposing first side surfaces and exposing a portion of the semiconductor substrate; Forming a source / drain silicon film on the exposed semiconductor substrate and covering the exposed first side surface of the stacked channel pattern to a predetermined thickness; Metal silicideing the entire silicon film; Forming a first insulating film on the semiconductor substrate on which the silicon film is formed so as to completely fill the sacrificial gate pattern; Removing the sacrificial gate pattern and etching the device isolation layer using the first insulating layer as a mask to expose a pair of opposing second side surfaces of the stacked channel pattern to form a gate recess; Selectively removing the sacrificial layer of the stacked channel pattern to form a gate tunnel; And Forming a gate electrode by filling the gate recess and the gate tunnel with a conductive layer to form a gate electrode. Alternately forming at least one sacrificial layer and a channel layer on the semiconductor substrate; Forming an isolation layer defining an active region on the semiconductor substrate in which the sacrificial layer and the channel layer are alternately formed; Forming a sacrificial gate pattern on the semiconductor substrate on which the device isolation layer is formed; Etching the sacrificial layer, the channel layer and the semiconductor substrate using the sacrificial gate pattern as a mask to form a stacked channel pattern exposing a pair of opposing first side surfaces and exposing a portion of the semiconductor substrate; Forming a source / drain silicon film on the exposed semiconductor substrate and covering the exposed first side surface of the stacked channel pattern to a predetermined thickness; Forming a first insulating film on the semiconductor substrate on which the silicon film is formed so as to completely fill the sacrificial gate pattern; Removing the sacrificial gate pattern and etching the device isolation layer using the first insulating layer as a mask to expose a pair of opposing second side surfaces of the stacked channel pattern to form a gate recess; Selectively removing the sacrificial layer of the stacked channel pattern to form a gate tunnel; And Filling the gate recess and the gate tunnel with a conductive layer to form a gate electrode; Exposing the silicon film by removing the first insulating film from the semiconductor substrate on which the gate electrode is formed; A method of manufacturing a Schottky barrier semiconductor device having multiple channels, the method comprising silicidating the entire exposed silicon film. The method of claim 1, wherein the channel layer and the sacrificial layer are formed of a material having an etch selectivity with respect to each other. 3. The Schottky barrier according to claim 1 or 2, wherein the channel layer epitaxially grows single crystal silicon and the sacrificial layer epitaxially grows single crystal germanium or single crystal silicon germanium. Method of manufacturing a semiconductor device. The method according to claim 1 or 2, wherein the sacrificial gate pattern is formed of a silicon oxide film. 3. The method of claim 1, wherein the first insulating layer is formed of a material having an etch selectivity with a material of the sacrificial gate pattern. 4. The method of claim 1 or 2, wherein the gate electrode is formed of silicon. The method according to claim 1 or 2, wherein the gate electrode is formed of titanium nitride, tungsten or tantalum nitride. 3. The method of claim 2, further comprising forming a second insulating film on the semiconductor substrate on which the metal silicide is formed to completely fill the gaps between the gate electrodes.

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