JPH04361576A - High dielectric constant oxide semiconductor device - Google Patents

Abstract

PURPOSE:To realize a high dielectric constant oxide semiconductor device low in contact resistance by a method wherein a high carrier concentration region is provided onto the surface of a high dielectric constant oxide semiconductor region, and a material region lower than the oxide semiconductor in dielectric constant is formed on the high carrier concentration region. CONSTITUTION:A high carrier concentration region 2 of SrTiO3 doped with Nb is made to grow on an oxide semiconductor device 1 of SrTiO3 doped with Nb. Furthermore, a tunnel barrier layer 3 of aluminum oxide is deposited on the region 2, and an electrode 4 of Nb is provided onto the layer 3. As mentioned above, a high carrier concentration region of N<+>-type oxide semiconductor is arrange on an N-type oxide semiconductor region, a tunnel barrier layer of low dielectric constant is formed thereon, and a metal electrode is formed on the barrier layer, so that a tunnel current flows between the electrode and the oxide semiconductor region when a voltage is applied between them.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a high dielectric constant oxide semiconductor device using an oxide semiconductor having a high dielectric constant and having a low resistance contact.

[0002] In this specification, a high dielectric constant refers to a dielectric constant of at least 100 or more. Most high-permittivity semiconductors having a high dielectric constant and a semiconductor-like band structure are oxides. These high dielectric constant oxide semiconductors have the potential to create highly sensitive semiconductor elements that can operate at a low voltage of about several mV, and their future potential is attracting attention.

For example, in the case of a diode, it is possible to create a detection element for detecting electromagnetic waves weaker than that of a normal semiconductor diode. Further, in the case of a transistor, a transistor with extremely low power consumption can be manufactured. Such a transistor has high utility value as a component of a highly integrated circuit and a component of a high-performance computer.

In order to use these elements to attach lead wires to the outside or to integrate multiple elements and connect them to each other, it is necessary to create a low resistance between the oxide semiconductor and the conductive material that constitute the element. It is necessary to form a contact.

[0005]

[Prior Art] Low-resistance contacts to semiconductors include alloy contacts, which are made by forming a metal layer on the semiconductor surface and alloying it by heating, etc., and alloy contacts, which are made by forming a high carrier concentration layer on the semiconductor surface. A non-alloy contact is known in which a layer of a conductive material is formed on top of the contact to extremely narrow the width of the potential barrier created by the contact potential difference, allowing carriers to easily pass through by tunneling.

[0006] No alloy type low resistance contacts are known for oxide semiconductors. On the other hand, doping is also possible for high dielectric constant oxide semiconductors. Therefore, there is a possibility that a non-alloy type low resistance contact can be made to a high dielectric constant oxide semiconductor.

FIG. 2 shows a case where a non-alloy contact according to the conventional concept is formed for a high dielectric constant oxide semiconductor. FIG. 2(A) shows the configuration, and FIG. 2(B) shows the potential distribution.

In FIG. 2A, an oxide semiconductor region 11 formed of, for example, an oxide semiconductor having a high dielectric constant
A high carrier concentration region 12 having a high carrier concentration is formed on the surface of the substrate, and an electrode 14 made of a conductive material is formed thereon. The dielectric constant ε1 of the oxide semiconductor is at least 100 or more, and has a value of 1000 or more, for example. The high carrier concentration region 12 is, for example, 1019
It is an n-type region having a carrier concentration of cm-3 or more. The electrode 14 is a metal electrode made of, for example, Nb.

A Schottky barrier is formed at the interface between a metal or other conductive material and a semiconductor. In the case of a normal semiconductor having a dielectric constant of about 10, if the carrier concentration on the semiconductor surface is high, the thickness of the surface depletion layer associated with the Schottky barrier becomes extremely thin. Therefore, a current flows due to carrier tunneling through the thin depletion layer, resulting in a low resistance contact.

0010

[Problems to be Solved by the Invention] However, although such a low-resistance contact formation method is effective for normal semiconductors whose dielectric constant is not very high, it is not suitable for high-permittivity oxide semiconductors that have a high dielectric constant. It is not effective against That is, it is extremely difficult to obtain a low resistance contact even if the structure shown in FIG. 2(A) is created. The inventor analyzed the reason as follows.

FIG. 2(B) schematically shows the potential distribution when a voltage is applied to the configuration of FIG. 2(A). The case where the high carrier concentration region 12 is of n type will be illustrated. Electrode 1
4, when a positive voltage is applied to the oxide semiconductor region 11, a depletion layer spreads from the surface of the high carrier concentration region 12, and the potential at the bottom of the conduction band curves as shown in the figure. However, if the high carrier concentration region 12 and the oxide semiconductor region 11 have a high dielectric constant, this band bending will be small and a wide depletion layer will be formed. As the dielectric constant of the semiconductor increases, the thickness of the depletion layer increases in proportion to the 1/2 power of the dielectric constant. If the high dielectric constant oxide semiconductor has a dielectric constant that is, for example, hundreds of times higher than that of a normal semiconductor, the thickness of the depletion layer will be at least several tens of times thicker. The resistance due to carrier tunneling through the depletion layer increases exponentially with the thickness of the depletion layer.

Therefore, even if the semiconductor surface is made into a high carrier concentration region, the thickness of the depletion layer will be far greater than the thickness that allows tunneling. For this reason, in the case of a high dielectric constant oxide semiconductor, even if a high carrier concentration region is formed on the surface, the thickness of the formed surface depletion layer becomes thick and the tunneling resistance becomes significantly large. The height of the Schottky barrier is generally 1 eV or more, and there are very few carriers with enough energy to cross the barrier. Therefore, the contact resistance becomes extremely high at low applied voltages. For this reason, it has been extremely difficult to obtain a low resistance contact with a configuration similar to the conventional one.

For example, when a diode structure is created using a high dielectric constant oxide semiconductor, although the diode itself operates at a low voltage, a low resistance contact cannot be obtained and the low voltage characteristics of the element cannot be utilized.

An object of the present invention is to provide a high dielectric constant oxide semiconductor device having a low resistance contact.

[0015]

[Means for Solving the Problems] FIG. 1 is a diagram illustrating the principle of the present invention.

In FIG. 1A, a high carrier concentration region 2 having a high carrier concentration is formed in the surface portion of an oxide semiconductor region 1 formed of an oxide semiconductor having a high dielectric constant.
is formed. A tunnel barrier layer is formed on the high carrier concentration region 2, which is made of a low dielectric constant material that has a significantly lower dielectric constant than an oxide semiconductor, and forms a thin tunnel barrier through which carriers can pass, and has a conductive layer on its surface. An electrode 4 made of a chemical substance is arranged. When the dielectric constant of the oxide semiconductor region 1 is ε1, and the dielectric constant of the tunnel barrier layer 3 is ε2, there is a relationship of ε2<<ε1.

[0017]

[Operation] The electrical coupling between the oxide semiconductor region 1 and the electrode 4 can be expressed by the equivalent circuit shown in FIG. 1(B). That is, it can be represented by a series combination of capacitances C1 and C2. The capacitance C1 is a depletion layer capacitance caused by a depletion layer formed on the surfaces of the oxide semiconductor region 1 and the high carrier concentration region 2. Capacitance C2 is a capacitance formed by tunnel barrier layer 3. When the width of the depletion layer is d1 and the thickness of the tunnel barrier layer 3 is d2, the capacitance C
1 is proportional to ε1/d1, and the capacitance C2 is proportional to ε2/d2. When voltage V is applied between oxide semiconductor region 1 and electrode 4, the voltage applied to tunnel barrier layer 3 is
V/{1+(ε2d1/ε1d2)}. this is,
This is because when a voltage is applied to a series connection of capacitors, the voltage applied to each capacitor is divided in inverse proportion to the capacitance. Therefore, if ε1>>ε2, the value of ε2d1/ε1d2 becomes extremely small, and most of the applied voltage is applied to the tunnel barrier layer. Therefore, the potential distribution when a voltage is applied to the configuration shown in FIG. 1(A) is as shown in FIG. 1(C). If the surface portion 2 of the oxide semiconductor region 1 has a high carrier concentration, the semiconductor surface will be in a degenerate metallic state, so that almost all of the applied voltage will be applied to the tunnel barrier layer 3, and the tunnel barrier layer 3 will have a very narrow width. form a narrow potential barrier. Therefore, carriers can move between the electrode 4, the oxide semiconductor region 1, and the high carrier concentration region 2. If the barrier formed by the tunnel barrier layer 3 is sufficiently thin, a large tunnel current can easily flow. In this way, a low resistance contact is obtained.

[0018]

[Embodiments] Hereinafter, embodiments of the present invention will be explained.

FIGS. 3A, 3B, and 3C show high dielectric constant oxide semiconductor devices according to three embodiments of the present invention.

In FIG. 3(A), Nb is 0.005
On the oxide semiconductor region 1 formed of SrTiO3 doped with wt%, Sr doped with 0.5 wt% of Nb is formed.
A high carrier concentration region 2 made of rTiO3 is grown to a thickness of about 300 nm by high frequency sputtering. On the high carrier concentration region 2, a tunnel barrier layer 3 made of aluminum oxide AlOx is deposited to a thickness of about 2 nm by high frequency sputtering. On this tunnel barrier layer 3, an electrode 4 made of Nb is formed.

[0021] SrTiO3 has a temperature of about 250,4.
It has a high dielectric constant of about 20,000 at 2K. The dielectric constant of AlOx is about 12 to 15. 0.005w of Nb
t% doped SrTiO3 is about 1017 cm-3
It has a carrier concentration of about In addition, 0.5 wt% Nb
Doped SrTiO3 is 1019-1020 cm
-Has a carrier concentration of 3rd place. Therefore, Fig. 3 (A
) has an n-type oxide semiconductor region 1 and an n-type oxide semiconductor region 1.
High carrier concentration region 2 formed of + type oxide semiconductor
is arranged, a low dielectric constant tunnel barrier layer 3 is formed thereon, and a metal electrode 4 is formed thereon. In such a configuration, when a voltage is applied between the electrode 4 and the oxide semiconductor region 1, as described above, most of the applied voltage is applied to the tunnel barrier layer 3, and the voltage is applied between the electrode 4 and the oxide semiconductor regions 1 and 2. A tunnel current flows through.

In the structure of FIG. 3A, Nb is used as the electrode, but other metals may be used. for example,
When Al is used, an oxide film formed when performing ultrasonic bonding may be used as the tunnel barrier layer.

In the structure of FIG. 3A, donor impurity Nb is doped to form a high carrier concentration region, but the high carrier concentration region can also be formed by other methods.

In FIG. 3B, a high carrier concentration region 2 is formed by subjecting the surface of the SrTiO3 substrate 1 to plasma treatment with argon. The conditions for plasma treatment are, for example, a high frequency power density of 0.1 W/
cm2, Ar gas pressure is 10 mTorr, and plasma processing time is 5 minutes. When the surface of the oxide semiconductor region is treated with Ar plasma, oxygen vacancies are introduced. This oxygen vacancy acts as a donor, and a high carrier concentration region is formed. This method has the advantage that the process can be performed at a lower temperature and in a shorter time than the method of growing a high carrier concentration region by high frequency sputtering. Other points are similar to the embodiment shown in FIG. 3(A).

In the embodiments shown in FIGS. 3(A) and 3(B),
As the tunnel barrier layer 3, aluminum oxide AlO
x was used. The tunnel barrier layer can be formed from various other low dielectric constant materials.

In FIG. 3C, the tunnel barrier layer 3 is made of magnesium titanate MgTiO3 with a thickness of about 2 nm.
It is formed of. MgTiO3 is SrTiO3
It has the same perovskite structure. MgTiO3 films can be grown epitaxially on SrTiO3 substrates. Therefore, even if a thin tunnel barrier layer is formed, the tunnel barrier layer has no pinholes and has good characteristics. In addition, MgTiO3
has a dielectric constant of about 12 to 18. Therefore, a low resistance contact with good characteristics can be obtained.

FIGS. 4A to 4D show four other embodiments of the present invention. In FIG. 4A, the tunnel barrier layer 3 is formed of a Si thin film with a thickness of about 6 nm formed by high frequency sputtering. Si is
It has an electron affinity greater than that of SrTiO3. Therefore, at the Si/SrTiO3 interface, Si does not act as a barrier against the movement of carriers (electrons). Therefore, the probability that electrons pass through the Si barrier becomes sufficiently high, and a low resistance contact can be easily obtained. Since the barrier height between the Nb electrode and Si is also low, the thickness of the tunnel barrier layer 3 may be relatively thick in this embodiment.

In the above embodiments, SrTiO3 was used as the high dielectric constant oxide semiconductor. SrTiO3
is a promising material having a high dielectric constant of about 20,000 at a low temperature of about 4.2 K, but various other materials can also be used as the high dielectric constant oxide semiconductor. for example,
titanate, stannate, zirconate, niobate,
Tantalates, mixed crystals thereof, and the like can be used.

In FIG. 4B, the oxide semiconductor region 1 and the high carrier concentration region 2 are KTa1-x Nbx
It is formed by O3 (x=0.05). Furthermore, in order to provide carrier concentration, a part of K is replaced with Ca. That is, the oxide semiconductor region 1 has K1
-y Cay Ta1-x Nbx O3 (y=1×
10-5, x=0.05), and the high carrier concentration region 2 is formed by K1-y Cay Ta1-x Nbx O3
(y=0.01, x=0.05). Other points are similar to the embodiment shown in FIG. 3(A).

When a mixed crystal is used as an oxide semiconductor, various physical properties can be controlled by controlling the composition of the mixed crystal.

The oxide semiconductor used in FIG. 4(B) was 77
It has a dielectric constant of about 20,000 at K. Therefore, the low resistance contact of the embodiment of FIG. 4B can operate well at liquid nitrogen temperatures.

In the above embodiments, the electrodes are as follows:
A metal such as Nb was used. When a superconductor is used as an electrode, electrode resistance can be reduced to almost zero. In particular, when a high-temperature superconductor is used, it is possible to obtain an electrode that becomes superconducting even at relatively high temperatures.

In FIG. 4C, the electrode 4 is made of YBa2Cu3O7-x, which is a high temperature superconductor. In order to form the YBa2 Cu3 O7-x electrode 4, the tunnel barrier layer 3 disposed thereunder is made of yttrium aluminate YAlO3 with a thickness of about 2 nm.
formed by

In addition to aluminates, gallates such as lanthanum gallate LaGaO3 can also be used as the tunnel barrier layer.

Note that the tunnel barrier layer 3 may be made of other materials, such as group IV, group III-V compound semiconductors,
It can also be formed using an I-VI compound semiconductor or the like.

In FIG. 4D, the tunnel barrier layer 3 is formed of an InSb layer with a thickness of about 6 nm. By using such a semiconductor for the tunnel barrier, the height of the tunnel barrier can be reduced. Further, by using various mixed crystal semiconductors, the physical properties of the tunnel barrier layer can be controlled in various ways.

In the embodiments shown in FIGS. 3 and 4, a low resistance contact to the oxide semiconductor can be obtained. For example, in the configuration of Figure 3(A), 2×10-6Ω
A contact resistance of cm2 could be obtained. Also,
In the configuration of FIG. 4(A), a contact resistance of 5×10 −7 Ωcm 2 could be obtained.

By using such a low resistance contact, various oxide semiconductor devices can be formed.

FIG. 5 shows an example of a high dielectric constant oxide semiconductor device using a high dielectric constant oxide semiconductor.

FIG. 5A shows a diode operating at low voltage. A high carrier concentration region 2 is selectively formed on the surface of an oxide semiconductor region 1 made of a high dielectric constant oxide semiconductor, and a tunnel barrier layer 3 and an electrode 4 are laminated on the high carrier concentration region 2. There is. This configuration is shown in Figures 3 and 4.
The structure may be constructed using any of the embodiments shown in . A carrier injection control tunnel barrier layer 5 thicker than the tunnel barrier layer 3 is formed on the side of the high carrier concentration region 2, and a carrier injection electrode 6 is laminated thereon. The carrier injection controlled tunnel barrier layer 5 can be formed of a thicker layer of the same material as the tunnel barrier layer 3. Further, the carrier injection electrode 6 can be formed of the same material as the electrode 4. Further, the carrier injection control tunnel barrier layer 5 can be formed of other materials as long as they form a tunnel barrier with a lower tunneling probability than the tunnel barrier layer 3. In addition, the carrier injection electrode 6
may be formed of other conductive materials.

When a voltage is applied between the carrier injection electrode 6 and the electrode 4, a low resistance contact is formed between the electrode 4 and the oxide semiconductor region 1, and a low resistance contact is formed between the carrier injection electrode 6 and the oxide semiconductor region 1. , a contact with varying tunneling probability is formed by the applied electrode. Therefore, a diode that operates at low voltage can be obtained.

FIG. 5B shows a transistor structure using a high dielectric constant oxide semiconductor. The oxide semiconductor region 1, high carrier concentration region 2, tunnel barrier layer 3, and electrode 4 are as follows:
This is similar to the embodiment of FIG. 5(A), and constitutes a low resistance contact. On the oxide semiconductor region 1, a laminated layer of an emitter barrier layer 7 and an emitter electrode 8 is further formed on the side of the high carrier concentration region 2, and a base electrode 9 is formed on the other main surface. Emitter barrier layer 7, emitter electrode 8
has the same structure as the carrier injection control tunnel barrier layer 5 and carrier injection electrode 6 shown in FIG. 5(A). Base electrode 9 is an electrode that forms a Schottky contact with oxide semiconductor region 1 . In such a configuration, the oxide semiconductor region 1 having a high dielectric constant is controlled by the potential of the base electrode 9.
The potential of is controlled. Therefore, depending on the voltage applied between the emitter electrode 8 and the base electrode 9, the emitter electrode 8
The current injected into the oxide semiconductor region 1 is controlled. In this way a transistor structure is obtained that operates at low voltages.

[0043] The present invention has been explained above in accordance with the examples.
The present invention is not limited to these. for example,
It will be obvious to those skilled in the art that various changes, improvements, combinations, etc. are possible.

[0044]

[Effects of the Invention] As explained above, according to the present invention,
A low resistance contact can be easily obtained with a high dielectric constant oxide semiconductor.

For this reason, various high dielectric constant oxide semiconductor devices are provided that take advantage of the characteristics of high dielectric constant oxide semiconductors.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 1(A) shows the configuration, FIG. 1(B) shows an equivalent circuit, and FIG. 1(C) shows the potential distribution.

FIG. 2 shows a conventional technique. FIG. 2(A) shows the configuration,
FIG. 2(B) shows the potential distribution.

FIG. 3 shows an embodiment of the invention. Figures 3(A),(B),
(C) shows a structure in which a low resistance contact is formed on a high dielectric constant oxide semiconductor.

FIG. 4 shows an embodiment of the invention. Figures 4(A),(B),
(C) and (D) each show a structure in which a low resistance contact is formed in a high dielectric constant oxide semiconductor.

FIG. 5 shows an embodiment of the invention. FIG. 5(A) shows the structure of a diode, and FIG. 5(B) shows the structure of a transistor.

[Explanation of symbols]

1 Oxide semiconductor region 2 High carrier concentration region 3 Tunnel barrier layer 4 Electrode 5 Carrier injection control tunnel barrier layer 6 Carrier injection electrode 7 Emitter barrier layer 8 Emitter electrode 9 Base electrode 11 Oxide semiconductor region 12 High carrier concentration region 14 Electrode

Claims (6)

[Claims] 1. An oxide semiconductor region (1) formed of an oxide semiconductor having a high dielectric constant, and a high carrier concentration region (2) formed in a surface portion of the oxide semiconductor region and having a higher carrier concentration. ), and a tunnel barrier layer disposed in contact with the high carrier concentration region, formed of a low dielectric constant material having a significantly lower dielectric constant than the oxide semiconductor, and forming a thin tunnel barrier through which carriers can pass. (3) and an electrode (4) disposed on the tunnel barrier layer and made of a conductive material, the electrode having a high dielectric constant and forming a low resistance contact with the oxide semiconductor region. Oxide semiconductor device. 2. The high dielectric constant oxide semiconductor device according to claim 1, wherein the high carrier concentration region is formed in a region having a composition that deviates from the stoichiometric composition of the oxide semiconductor. 3. The high dielectric constant oxide semiconductor device according to claim 1, wherein both the oxide semiconductor and the low dielectric constant material have a perovskite crystal structure. 4. The high dielectric constant oxide semiconductor device according to claim 1, wherein the low dielectric constant material has a larger electron affinity than the oxide semiconductor. 5. Further, a carrier injection control tunnel barrier layer formed on the oxide semiconductor region and forming a controllable tunnel barrier with respect to carriers, and a conductive layer disposed on the carrier injection control tunnel barrier layer. Claim 1 further comprising a carrier injection electrode made of a chemical substance.
5. The high dielectric constant oxide semiconductor device according to any one of . 6. The high dielectric constant oxide semiconductor device according to claim 5, further comprising a control electrode disposed on the oxide semiconductor region and made of a conductive material.