JPH0888414A - Dielectric-base transistor - Google Patents

Abstract

PURPOSE: To enhance the controllability of a voltage gain and a superconducting current and to improve the productivity by simplifying the manufacturing steps by enhancing the controllability of a control electrode. CONSTITUTION: In a dielectric-base transistor comprising a base layer 2 formed of dielectric and an emitter electrode 4 and a collector electrode 5, which are provided on the base layer 2 in close proximity through a low dielectric layer 3 whose dielectric constant is lower than that of the base layer, a base electrode 6 for controlling the potential of the base layer 2 is provided on the surface of the base layer 2 on the same side as the emitter electrode 4 and the collector electrode 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dielectric base transistor, and more particularly to an electrode structure of a dielectric transistor using a thin film oxide base.

[0002]

2. Description of the Related Art Currently, in the field of electronics technology, active elements using semiconductors such as semiconductor transistors are used, and bipolar transistors or MISFETs occupy most of the active elements.
As a semiconductor material, a group IV semiconductor such as germanium or a group III-V compound semiconductor such as GaAs is used, centering on silicon.

On the other hand, a transistor using an oxide semiconductor has been proposed. Many of such oxide semiconductors have an energy gap of 3 eV or more and are transparent to visible light. It has characteristics that ordinary semiconductors do not have, such as high dielectric constant or ferroelectricity.

Some oxides, such as high-temperature superconductors, exhibit superconductivity at a temperature around 77K, which is higher than that of ordinary superconductors. By using it, it becomes possible to fabricate a non-volatile memory using ferroelectricity, a display device utilizing transparency to visible light, or a functional device such as a superconducting switch utilizing superconductivity.

The principle, structure, and characteristics of a dielectric base transistor using such an oxide are shown in FIGS. 6 and 7.
Will be explained. FIG. 6A shows a conceptual structure of the dielectric base transistor, FIG. 6B shows a band diagram without bias, and FIG. 6C shows a band diagram with bias. is there. Further, FIG. 7A shows a specific structure of a conventional dielectric base transistor, FIG. 7B shows characteristics of a general dielectric base transistor, and FIG. It shows the characteristics when the collector interval is set to about 50 nm.

Referring to FIG. 6, the dielectric base transistor is composed of a pair of current applying electrodes composed of an emitter electrode 4 and a collector electrode 5, and a base layer 2 composed of an oxide semiconductor provided between the current applying electrodes, The electric potential of the base layer 2 is controlled by the base electrode 6, which is a control electrode, to form a channel in the base layer 2 to control the flowing current.

In practice, as shown in the figure, a low dielectric layer 3 having a dielectric constant lower than that of the base layer 2 is interposed between the current applying electrodes 4 and 5 and the oxide semiconductor base layer 2. As a result, the capacitance between the current application electrodes 4, 5 and the base electrode 6 is reduced and the characteristics are improved. Further, in operation, as shown in FIGS. 6B and 6C, the electrons injected from the emitter electrode 4 travel in the base layer 2 by diffusion or drift and reach the collector electrode 5.

See FIG. 7A. FIG. 7A shows a concrete structure of a dielectric base transistor actually proposed, in which an oxide semiconductor made of SrTiO ₃ having a high dielectric constant is used as a base layer. In addition to being used as 2, the emitter electrode 4 and the collector electrode 5 are provided on the base layer 2 with a low dielectric layer 3 having a low dielectric constant such as ZnO and separated by a predetermined distance. The base electrode 6 which is a control electrode is provided on the back surface of the base layer 2 and controls the current between the emitter and the collector by the voltage applied to the base electrode 6, and 7 is a protective film such as SiO _2. Is.

7B and 7C. FIG. 7B shows the characteristics of the dielectric base transistor shown in FIG. 7A, and the current gain is as large as that of the FET. Although it is a value, the voltage gain is about 3. In addition, in FIG. 7C, the electrodes 4 to 6 are made of a superconductor such as Nb, and an n-type doped region doped with 10 ¹⁹ cm ⁻³ is formed in a portion of the SrTiO ₃ layer 2 in contact with the low dielectric layer 3. The distance between the emitter electrode 4 and the collector electrode 5 is 5
The characteristics are exhibited when the thickness is set to about 0 nm, and it can be confirmed that a superconducting current flows.

This superconducting current flows by the so-called proximity effect. That is, in the emitter electrode 4 and the collector electrode 5 made of a superconductor, the electrons form a Cooper pair and are in a superconducting state, and the electrons forming the pair are a base made of SrTiO ₃ which is a normal conductor. Layer 2
However, the Cooper pair breaks down with time and its density decreases, but the thickness of the base layer 2 becomes 50%.
In the case of about nm, most Cooper pairs reach the collector made of a superconductor and are observed as a superconducting current.

[0011]

However, the conventional dielectric base transistor has a problem that the voltage gain is about 3 which is small as a transistor, and
When controlling the superconducting current as shown in FIG. 7C, there is a problem that the change in characteristics with respect to the control voltage is small because the electron density in the n-type doped region is too large.

That is, in the dielectric base transistor, when a voltage change is applied to the base electrode 6, the base layer 2
The electric potential of the channel region formed near the base electrode changes, but when the doping amount of the channel region is large, the carrier density changes rather than the electric potential change, and as a result, the channel resistance changes. .

When the current flowing through the transistor is determined by the current injected from the emitter electrode 4 into the base layer 2, the current is determined by the potential of the base layer 2, so that a small control voltage is applied to the base layer 2. If the potential changes greatly, the change in the transistor current also increases. Further, when the current is determined by the resistance in the base layer 2, that is, the carrier density and the mobility, if the change of the carrier density is large with a small control voltage, the change of the current of the transistor also becomes large. The controllability of the control electrode is evaluated according to the degree of change of

In the case of FIG. 7 described above, since the carrier density of the doped n-type doped region forming the channel region, that is, the electron density is large, the current is determined by the electron density. In the case of a device, the electron density in the n-type doped region is too large, so that the change in electron density with respect to the change in control voltage is small and the controllability of the control electrode is low.

Furthermore, in the conceptual structure shown in FIG. 6, the base layer 2 provided between the emitter electrode 4 and the collector electrode 5 in order to increase the arrival rate of carriers to the collector.
In order to reduce the thickness of the film, a high-level thin film forming technique is required, which causes a problem in productivity.

Therefore, according to the present invention, in the dielectric base transistor, the controllability of the control electrode is enhanced, the controllability of the voltage gain and the superconducting current is enhanced, and the manufacturing process is simplified to improve the productivity. To aim.

[0017]

FIG. 1 is a diagram showing a cross section of an element for explaining the principle structure of the present invention. The means for solving the problem of the present invention will be described with reference to FIG. According to the present invention, a base layer 2 made of a dielectric material, and an emitter electrode 4 and a collector electrode 5 provided on the base layer 2 in close proximity to each other via a low dielectric layer 3 having a lower dielectric constant than the base layer 2. In the dielectric base transistor consisting of, a base electrode 6 for controlling the potential of the base layer 2 is provided on the surface of the base layer 2 on the same side as the emitter electrode 4 and the collector electrode 5.

Further, the present invention is characterized in that the base electrode 6 is provided so as to surround the emitter electrode 4 and the collector electrode 5, and the present invention is electrically connected to the base electrode 6 on the back surface of the base layer 2. A back electrode for connection is provided.

Further, the present invention is characterized in that a barrier layer for preventing carrier movement is provided between the base electrode 6 and the base layer 2, and further, a ferroelectric layer is provided between the base electrode 6 and the base layer 2. It is also characterized in that a body layer is provided.

[0020]

The operation of the present invention will be described with reference to FIG. Figure 2
(A) shows that the portion of the base layer 2 in contact with the low dielectric layer 3 has 10
FIG. 2B is a cross-sectional view of an element for explaining a model of controllability of a control electrode of a conventional dielectric base transistor provided with an n-type doped region 11 doped with an n-type impurity of about ¹⁹ cm ⁻³ . [FIG. 3] is an element cross section for describing the controllability of the control electrode of the present invention as a model.

In this case, the controllability of the control electrode is determined by the capacitance between the base electrode 6 which is the control electrode and the n-type doped region 11. That is, the electrostatic capacity in this case is an amount representing how much the carrier amount of the n-type doped region changes due to the change of the control voltage. Therefore, the unit area of the n-type doped region is relative to the control electrode. The larger the electrostatic capacity has, the greater the controllability.

In FIG. 2, the capacitance C of this model is obtained by using the approximation that the width of the control electrode 6 is infinite. In the conventional case of FIG. 2 (a), the following (1) It becomes like a formula.

[Equation 1]

In the case of the present invention shown in FIG. 2B, the capacitance C is given by the above equation (1), but the value of k is
k = d / (d + 2w). However, w is a gap between the n-type doped region 11 and the control electrode (base electrode) 6.

In this case, for example, the base layer 2 is composed of a SrTiO ₃ layer having a thickness h of 400 μm, the width d of the n-type doped region 11 is 20 μm, and the gap w between the n-type doped region 11 and the control electrode 6 is set. Assuming that the relative dielectric constant of the SrTiO ₃ layer is 2 μm and 2000 (4.2 K), the capacitance of 0.65 μF / cm ² per unit area in the conventional example becomes 2.1 μF / cm ² in the present invention. , A significant improvement is obtained.

In the above model calculation, a two-dimensional model in which the cross-sectional structure of the device shown in the figure continues infinitely perpendicularly to the paper surface was used, but the control electrode was provided so as to surround the emitter electrode and the collector electrode. The same effect can be obtained in the case of

Therefore, since the control electrode (base electrode) and the emitter electrode and the collector electrode are provided on the same side of the base layer, the controllability of the control electrode is improved and the gain parameters such as voltage gain and transconductance are improved. Then
Further, since the surface of the thin film base layer is used as the channel region, it is possible to use a relatively thick thin film that does not reduce the gain, so that no advanced thin film forming technology is required and all electrodes are on the same side. Since it is provided in the above, the manufacturing process is simplified.

Since the base electrode 6 is provided so as to surround the emitter electrode 4 and the collector electrode 5, the controllability of the control electrode is further enhanced, and the back electrode electrically connected to the base electrode 6 is a base layer. Since the channel region is shielded from the outside by being provided on the back surface of 2, the operation becomes more stable.

Further, by providing a barrier layer between the base electrode 6 and the base layer 2 to prevent the movement of carriers,
It is possible to realize a normally-off type transistor,
Furthermore, by providing a ferroelectric layer between the base electrode 6 and the base layer 2, a transistor having a memory function can be realized.

[0029]

FIG. 3 is a diagram showing a first embodiment of the dielectric base transistor of the present invention. 3A and 3B, first, an n-type SrTiO ₃ thin film doped with 0.1% by weight of Nb is deposited to a thickness of 500 nm on an insulating substrate 1 such as sapphire, and then ZnO having a lower dielectric constant than SrTiO ₃ is deposited. 10
Then, the base layer 2 and the low-dielectric layer 3 are formed by patterning.

Then, the emitter electrode 4 and the collector electrode 5 having a thickness of 200 nm and the base electrode 6 having a thickness of 200 nm are formed from Nb which is a superconductor, and the emitter extraction electrode 8 is formed through the protective film 7 such as SiO _2. And a collector extraction electrode 9 are provided. Note that FIG. 3B shows a state seen from the upper surface when the protective film 7 and the extraction electrodes 8 and 9 in FIG. 3A are removed in order to clarify the plane pattern of the electrodes.

In this case, normally-on operation is performed by the contact potential difference between Nb which constitutes the control electrode and SrTiO ₃ which constitutes the base layer. Since it is improved by about 3.2 times as compared with, the voltage gain is also about 10, and the characteristics are significantly improved. Further, in this example, the current-voltage characteristics when an n-type doped region doped with an n-type impurity of about 2 × 10 ¹⁹ cm ⁻³ is provided in contact with the low dielectric layer is shown in FIG.

See FIG. 3C. The characteristics of the superconducting current of the present invention shown in FIG.
Comparing with the superconducting current characteristic of the conventional example shown in (c),
It can be seen that I _C is changed about 3 times by the same change of the control voltage (V _BE ), and therefore, the controllability of the superconducting current is also improved about 3 times.

FIG. 4A is a diagram for explaining a second embodiment of the dielectric base transistor of the present invention. In order to clarify the planar pattern of the electrodes, a protective film and The figure shows a state seen from the upper surface when the extraction electrode is removed, and the configuration other than the electrode arrangement is the same as that of the first embodiment.

In the second embodiment, the base electrode 6 is provided so as to completely surround the emitter electrode 4 and the collector electrode 5 in the plane pattern, and the control electrode is formed by such an electrode arrangement. Controllability of 50
Improve about%.

See FIG. 4B. FIG. 4B shows a third dielectric base transistor of the present invention.
FIG. 6 is a cross-sectional view of an element for explaining the example of FIG.
The configuration other than the electrode arrangement is the same as that of the first embodiment. In the third embodiment, a back electrode electrically connected to a base electrode made of Pt having a thickness of 50 nm, that is, a back base electrode 12, is provided on the surface of the base layer 2 facing the insulating substrate 1. In addition, since the channel region is shielded from external influences by such an electrode structure, more stable operation characteristics can be obtained.

See FIG. 5A. FIG. 5A shows a fourth dielectric base transistor of the present invention.
FIG. 6 is a cross-sectional view of an element for explaining the example of FIG.
A non-doped SrTiO ₃ layer is used as the base layer 2, and the thickness between the control electrode 6 and the base layer 2 is 5 nm.
The barrier layer 13 made of the insulating CeO ₂ thin film is inserted, and the other structure is the same as that of the first embodiment.

As described above, when the non-doped SrTiO ₃ is used, normally-off characteristics can be obtained unlike the first to third embodiments, but as described above, the control electrode 6 and the base are used. By providing the barrier layer 13 between the layer 2 and the layer 2, it is possible to prevent electrons flowing in the channel region on the surface of the base layer 2 from flowing into the control electrode when an on-voltage is applied. Obtainable. The detailed mechanism is unknown,
The barrier action is considered to be due to the difference in band gap between CeO ₂ and SrTiO ₃ .

See FIG. 5B. FIG. 5B shows a fifth example of the dielectric base transistor of the present invention.
FIG. 6 is a cross-sectional view of an element for explaining the example of FIG.
PZ with a thickness of 200 nm between the control electrode 6 and the base layer 2
Ferroelectric layer 1 made of T (PbZr _0.52 Ti _0.48 O ₃ ).
4 is inserted, and other configurations are similar to those of the first embodiment.

In the case of the fifth embodiment, the potential or carrier density of the channel region differs depending on the direction of the spontaneous polarization of the ferroelectric layer even when the same control voltage is applied, so that the transistor is a transistor. The characteristics will be different. Since the direction of this polarization can be inverted by the voltage applied to the control voltage, the transistor characteristics will differ depending on the voltage applied to the control voltage in the past, and it can be used as a memory.

Further, in this case, since the control electrode 6 is provided on the surface of the base layer 2, the ferroelectric layer 14 is also provided on the surface. Therefore, a ferroelectric material such as PZT that is weak against high temperature is used. It also allows the use of thin films.

In each of the above embodiments, the low dielectric layer 3 has a continuous structure between the emitter electrode 4 and the collector electrode 5, but as shown in the conventional example of FIG. It may be provided separately between the electrode 4 and the collector electrode 5, and the base layer 2 may be S.
Although rTiO ₃ is used, other perovskite oxide similar to SrTiO ₃ may be used.
Further, in each of the above embodiments, the rectangular pattern is described, but the present invention is not limited to the rectangular pattern.

[0042]

According to the present invention, since the control electrode and the emitter electrode and the collector electrode are provided on the same surface, the controllability of the control electrode is improved, so that the voltage gain is improved and the superconductivity is increased. The controllability of the current is also improved, and further,
Since the manufacturing process is simplified, productivity is also improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a principle configuration of the present invention.

FIG. 2 is a diagram illustrating the operation of the present invention.

FIG. 3 is a diagram illustrating a first embodiment of the present invention.

FIG. 4 is a diagram illustrating second and third embodiments of the present invention.

FIG. 5 is a diagram illustrating fourth and fifth embodiments of the present invention.

FIG. 6 is a diagram illustrating a conceptual configuration of a dielectric base transistor.

FIG. 7 is a diagram illustrating a conventional dielectric base transistor.

[Explanation of symbols]

 1 Insulating Substrate 2 Base Layer 3 Low Dielectric Layer 4 Emitter Electrode 5 Collector Electrode 6 Base Electrode (Control Electrode) 7 Protective Film 8 Emitter Extraction Electrode 9 Collector Extraction Electrode 10 Base Extraction Electrode 11 n-type Doped Region 12 Backside Base Electrode 13 Barrier Layer 14 Ferroelectric layer

Claims (10)

[Claims] 1. A dielectric base comprising a base layer made of a dielectric material, and an emitter electrode and a collector electrode provided on the base layer in close proximity to each other with a low dielectric layer having a lower dielectric constant than the base layer interposed therebetween. In the transistor, a base electrode for controlling the electric potential of the base layer is provided on the surface of the base layer on the same side as the emitter electrode and the collector electrode, and a dielectric base transistor. 2. The dielectric base transistor according to claim 1, wherein the base layer is composed of a thin film dielectric provided on an insulating substrate. 3. The dielectric base transistor according to claim 1, wherein the emitter electrode and the collector electrode are made of a superconductor. 4. The dielectric base transistor according to claim 1, wherein the base electrode is provided so as to surround the emitter electrode and the collector electrode. 5. The dielectric base transistor according to claim 1, further comprising a back electrode provided on the back surface of the base layer and electrically connected to the base electrode. 6. A ferroelectric layer is provided between the base electrode and the base layer.
The dielectric base transistor according to any one of 1. 7. The dielectric base transistor according to claim 1, wherein the base layer is composed of SrTiO ₃ doped with an n-type impurity. 8. The dielectric base transistor according to claim 7, wherein a region of the base layer in contact with the low dielectric layer is further doped with an n-type impurity to provide a high impurity concentration region. 9. The dielectric base transistor according to claim 1, further comprising a barrier layer for carriers between the base electrode and the base layer. 10. The base layer is made of non-doped SrT.
The dielectric base transistor according to claim 9, wherein the dielectric base transistor is composed of iO ₃ .