JPH04361536A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04361536A JPH04361536A JP3137463A JP13746391A JPH04361536A JP H04361536 A JPH04361536 A JP H04361536A JP 3137463 A JP3137463 A JP 3137463A JP 13746391 A JP13746391 A JP 13746391A JP H04361536 A JPH04361536 A JP H04361536A
- Authority
- JP
- Japan
- Prior art keywords
- solder material
- solder
- semiconductor element
- die pad
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 229910000679 solder Inorganic materials 0.000 claims abstract description 51
- 239000000463 material Substances 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims description 15
- 238000002844 melting Methods 0.000 abstract description 3
- 230000008018 melting Effects 0.000 abstract description 3
- 238000005476 soldering Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L2224/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Die Bonding (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体素子を支持体に
取付けるダイボンディングに関し、特にはんだ接着法に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to die bonding for attaching semiconductor elements to a support, and more particularly to a solder bonding method.
【０００２】0002
【従来の技術】図３は従来の半導体装置の製造方法を示
す斜視図、図４は従来のはんだ材とはんだ材を巻いてい
るリールの斜視図である。これらの図において、１は半
導体素子を取付ける支持体としてのダイパット、４はダ
イパット１上に載置され半導体素子をダイパット１に接
着するリボン状のはんだ材で、リール３に巻かれている
。このような構成において、従来半導体素子をダイパッ
ト１上に取付けるには、まずリボン状のはんだ材４をリ
ール３から引出して、所定寸法に切断し、このはんだ材
４をダイパット１上に載置し、ダイパット１をはんだ材
４の融点以上にまで加熱し、はんだ材４を溶融状態とし
た後、半導体素子を押えつけ、はんだ材４を半導体素子
、ダイパット１間に拡げる、その後、冷却することによ
り、はんだ材４を凝固させ、半導体素子をダイパット１
上に取付けている。この後、半導体装置を完成させるに
は、半導体素子の電極取出し口と内部リードの先端部と
を熱圧着方式、あるいは超音波方式等のワイヤボンディ
ング方法で金属細線により接続し、モールド工程、リー
ドカット工程、リードベンド工程電気特性検査工程を経
て行われる。2. Description of the Related Art FIG. 3 is a perspective view showing a conventional method for manufacturing a semiconductor device, and FIG. 4 is a perspective view of a conventional solder material and a reel on which the solder material is wound. In these figures, 1 is a die pad as a support for attaching a semiconductor element, and 4 is a ribbon-shaped solder material placed on the die pad 1 to bond the semiconductor element to the die pad 1, which is wound around a reel 3. In such a configuration, conventionally, in order to attach a semiconductor element onto the die pad 1, a ribbon-shaped solder material 4 is first pulled out from the reel 3, cut into a predetermined size, and this solder material 4 is placed on the die pad 1. , by heating the die pad 1 to a temperature higher than the melting point of the solder material 4 to bring the solder material 4 into a molten state, pressing the semiconductor element, spreading the solder material 4 between the semiconductor element and the die pad 1, and then cooling it. , solidify the solder material 4, and place the semiconductor element on the die pad 1.
It is installed on top. After this, to complete the semiconductor device, the electrode outlet of the semiconductor element and the tip of the internal lead are connected with a thin metal wire using a wire bonding method such as a thermocompression method or an ultrasonic method, followed by a molding process and lead cutting. The process is carried out through a lead bending process and an electrical characteristic inspection process.
【０００３】0003
【発明が解決しようとする課題】従来の半導体装置の製
造方法は以上のような方法で行われているので、リール
から供給されるリボン状のはんだ材を溶融状態とした後
、半導体素子を押えつけることで、はんだ材を半導体素
子、ダイパット間に均一にかつ充分に濡れ拡がらせる必
要があり、このため半導体素子に応力がかかり半導体素
子に損傷を与える危険性がある。また、半導体素子の大
型化にともない、はんだ材をリボン状で供給する方法で
は、ダイパット上の中央部のみにしかはんだを供給でき
ず、半導体素子外周部付近まではんだが濡れ拡がらない
状態が生じたり、逆にリボン面積を大きくするとはんだ
がダイパット上からはみ出し、溶融状態中に酸化し、濡
れ拡がらない状態となるなど、半導体装置としての品質
を低下させるという問題がある。本発明は上記した従来
の問題点に鑑みなされたものであり、その目的とすると
ころは、半導体素子、支持体間のはんだ材を均一かつ充
分に濡れ拡げることができるはんだ材を用いて半導体装
置の品質向上を図った製造方法を提供することにある。[Problems to be Solved by the Invention] Conventional methods for manufacturing semiconductor devices are carried out as described above, so after melting the ribbon-shaped solder material supplied from the reel, the semiconductor element is held down. By applying the solder material, it is necessary to uniformly and sufficiently wet and spread the solder material between the semiconductor element and the die pad, which may cause stress to be applied to the semiconductor element and cause damage to the semiconductor element. In addition, as semiconductor devices become larger, the method of supplying solder material in the form of a ribbon can only supply solder to the center of the die pad, resulting in a situation where the solder does not wet and spread to the vicinity of the outer periphery of the semiconductor device. On the other hand, if the ribbon area is increased, the solder protrudes from the die pad, oxidizes during the molten state, and becomes unable to wet and spread, which deteriorates the quality of the semiconductor device. The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide a semiconductor device using a solder material that can uniformly and sufficiently spread the solder material between the semiconductor element and the support. The purpose of this invention is to provide a manufacturing method that improves the quality of products.
【０００４】0004
【課題を解決するための手段】この目的を達成するため
に、本発明は、加熱した後、溶融状態としたはんだ材で
半導体素子を支持体に取付ける半導体装置の製造方法で
あって、前記はんだ材は円形の断面を有する極細の線状
を呈しており、このはんだ材を単数本あるいは複数本に
切断して用いたものである。[Means for Solving the Problems] In order to achieve this object, the present invention provides a method for manufacturing a semiconductor device in which a semiconductor element is attached to a support using a solder material that is heated and molten. The solder material is in the form of an extremely thin wire with a circular cross section, and this solder material is cut into a single piece or a plurality of pieces.
【０００５】[0005]
【作用】本発明に係る半導体装置の製造方法では、半導
体素子を取付ける際に用いるはんだ材を断面が円形で極
細の線状にするとともに、このはんだ材を単数本あるい
は複数本に切断して用いたので、半導体素子、支持体間
のはんだの濡れ拡がりが均一でかつ充分となる。[Operation] In the method for manufacturing a semiconductor device according to the present invention, the solder material used when attaching the semiconductor element is made into an extremely thin wire shape with a circular cross section, and the solder material is cut into single or multiple pieces. Therefore, the solder spreads uniformly and sufficiently between the semiconductor element and the support.
【０００６】[0006]
【実施例】以下、本発明の一実施例を図にもとづいて説
明する。図１は本発明の製造方法示す斜視図、図２は本
発明のはんだ材とはんだ材を巻いているリールの斜視図
である。これらの図において、本発明の特徴とするとこ
ろは、はんだ材２の形状にある。すなわち、本発明のは
んだ材２は、断面が円形で極細の線状を呈しており、リ
ール３に巻かれている。ダイパット１はＦｅ−Ｎｉ系合
金が用いられ、０．１５ｍｍ程度の厚さに形成されてい
る。このような構成において、リール３からはんだ材２
を引出し、所定寸法に切断し、単数本あるいは複数本を
ダイパット１上の任意の位置にコンピュータ制御された
装置で載置する。この際必要に応じてはんだ材２に超音
波あるいは圧力等を加える。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing the manufacturing method of the present invention, and FIG. 2 is a perspective view of the solder material of the present invention and a reel wound with the solder material. In these figures, the feature of the present invention lies in the shape of the solder material 2. That is, the solder material 2 of the present invention has a circular cross section and an extremely thin linear shape, and is wound around the reel 3. The die pad 1 is made of Fe--Ni alloy and is formed to have a thickness of about 0.15 mm. In such a configuration, the solder material 2 is transferred from the reel 3.
is pulled out, cut to a predetermined size, and one or more pieces are placed at an arbitrary position on the die pad 1 using a computer-controlled device. At this time, ultrasonic waves or pressure are applied to the solder material 2 as necessary.
【０００７】次にダイパット１を加熱し、はんだ材２を
溶融状態とした後、半導体素子を押えつけ取付ける。こ
のときはんだ材２はその形状を断面が円形で極細の線状
とすることによりはんだ材２表面の酸化膜が少なくなり
、このために、半導体素子、ダイパット１間に均一でか
つ充分に濡れ拡がる。その後従来技術と同一の方法で半
導体装置を完成させる。なお、上記実施例では、１種類
の半導体素子の取付け方法を説明したが、複数種類の半
導体素子を取付ける場合には、はんだ材２をダイパット
１上に載置する位置を制御変更することにより、従来の
リボン状のはんだ材と比較してはんだ材の交換等の段取
り替えに要する時間を短縮できる。また、ダイパット１
の材質についてはＣｕ合金を使用しても同等の作用効果
を奏する。Next, the die pad 1 is heated to melt the solder material 2, and then the semiconductor element is pressed and mounted. At this time, the solder material 2 has a circular cross section and an ultra-fine linear shape, so that the oxide film on the surface of the solder material 2 is reduced, so that it spreads uniformly and sufficiently between the semiconductor element and the die pad 1. . Thereafter, a semiconductor device is completed using the same method as in the prior art. In the above embodiment, a method for attaching one type of semiconductor element was explained, but when attaching multiple types of semiconductor elements, by controlling and changing the position where the solder material 2 is placed on the die pad 1, Compared to conventional ribbon-shaped solder materials, the time required for setup changes such as replacing solder materials can be reduced. Also, die pad 1
Regarding the material, the same effect can be obtained even if a Cu alloy is used.
【０００８】[0008]
【発明の効果】以上説明したように、本発明によれば、
半導体素子を支持体に取付けるはんだ材を断面が円形で
かつ極細の線状とし、このはんだ材を切断して単数本あ
るいは複数本用いたので、はんだ材が半導体素子、ダイ
パット間に均一でかつ充分に濡れ拡がり、半導体素子に
損傷を与えることなく支持体に取付けることができ、こ
のため半導体装置として品質および信頼性の向上を図れ
る効果がある。[Effects of the Invention] As explained above, according to the present invention,
The solder material used to attach the semiconductor element to the support body has a circular cross section and an ultra-fine wire shape, and this solder material is cut and used in single or multiple pieces, so that the solder material is uniform and sufficient between the semiconductor element and the die pad. It spreads and can be attached to a support without damaging the semiconductor element, which has the effect of improving the quality and reliability of the semiconductor device.
【図１】本発明の製造方法を示す斜視図である。FIG. 1 is a perspective view showing the manufacturing method of the present invention.
【図２】本発明のはんだ材の収納状態を示す斜視図であ
る。FIG. 2 is a perspective view showing a stored state of the solder material of the present invention.
【図３】従来の製造方法を示す斜視図である。FIG. 3 is a perspective view showing a conventional manufacturing method.
【図４】従来のはんだ材の収納状態示す斜視図でる。FIG. 4 is a perspective view showing a state in which conventional solder material is stored.
１ ダイパット ２ はんだ材 ３ リール 1 Die pad 2 Solder material 3 Reel
Claims (1)
で半導体素子を支持体に取付ける半導体装置の製造方法
であって、前記はんだ材は円形の断面を有する極細の線
状を呈しており、このはんだ材を単数本あるいは複数本
に切断して用いたことを特徴とする半導体の製造方法。1. A method for manufacturing a semiconductor device in which a semiconductor element is attached to a support using a solder material that is heated and then brought into a molten state, the solder material being in the form of an extremely thin line having a circular cross section, A method for manufacturing a semiconductor, characterized in that the solder material is cut into a single piece or a plurality of pieces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3137463A JPH04361536A (en) | 1991-06-10 | 1991-06-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3137463A JPH04361536A (en) | 1991-06-10 | 1991-06-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04361536A true JPH04361536A (en) | 1992-12-15 |
Family
ID=15199197
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3137463A Pending JPH04361536A (en) | 1991-06-10 | 1991-06-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04361536A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH104102A (en) * | 1996-06-14 | 1998-01-06 | Nec Corp | Manufacture of semiconductor device |
| WO2020160915A1 (en) * | 2019-02-08 | 2020-08-13 | Jenoptik Optical Systems Gmbh | Method for soldering one or more components |
-
1991
- 1991-06-10 JP JP3137463A patent/JPH04361536A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH104102A (en) * | 1996-06-14 | 1998-01-06 | Nec Corp | Manufacture of semiconductor device |
| WO2020160915A1 (en) * | 2019-02-08 | 2020-08-13 | Jenoptik Optical Systems Gmbh | Method for soldering one or more components |
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