JPH04360559A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH04360559A
JPH04360559A JP3162208A JP16220891A JPH04360559A JP H04360559 A JPH04360559 A JP H04360559A JP 3162208 A JP3162208 A JP 3162208A JP 16220891 A JP16220891 A JP 16220891A JP H04360559 A JPH04360559 A JP H04360559A
Authority
JP
Japan
Prior art keywords
chip
package
improved
oil
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3162208A
Other languages
Japanese (ja)
Inventor
Hisashi Yamanobuta
恒 山信田
Hiroki Chikama
広樹 千釜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP3162208A priority Critical patent/JPH04360559A/en
Publication of JPH04360559A publication Critical patent/JPH04360559A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To radiate the heat generated in an IC chip without adding any special heat radiating device, such as heat sink, etc., by dipping the IC chip in insulating oil enclosed in an LSI package. CONSTITUTION:An IC chip 6 is mounted in a package 4. The package 4 is filled with insulating oil 1 so as to dip the chip 6 in the oil 1 and the package is airtightly sealed with a cap 3 so that no air can get in the package 4. Therefore, the heat radiating effect of the IC chip is remarkably improved and, at the same time, the mechanical strength of the chip 6 can be improved, because the oil 1 can absorb vibrations and shocks. Moreover, the reliability of the IC chip can be improved, because electrical insulation between wires from each other can be improved and occurrence of short circuit due to dust can be prevented.

Description

【発明の詳細な説明】[Detailed description of the invention]

【０００１】0001

【技術分野】本発明は半導体集積回路装置に関し、特に
ＬＳＩパッケージの封入方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a method of enclosing an LSI package.

【０００２】0002

【従来技術】従来のＬＳＩは図４に示す如く、パッケー
ジ４内にＩＣチップ６が搭載されており、パッケージ内
部には不活性ガス等の気体７がキャップ３により封入さ
れている。尚、２はワイヤボンディング線を示し、５は
端子を示している。2. Description of the Related Art As shown in FIG. 4, a conventional LSI has an IC chip 6 mounted in a package 4, and a gas 7 such as an inert gas is sealed inside the package with a cap 3. Note that 2 indicates a wire bonding line, and 5 indicates a terminal.

【０００３】この様な従来のＬＳＩパッケージにおける
ＩＣチップの封入方法では、ＩＣチップ６の周囲が不活
性ガス７によりに覆われているために、ＩＣチップ６か
らの放熱を十分吸収することができない。よって、ＬＳ
Ｉの性能の低下を招来するという欠点がある。[0003] In such a conventional method of encapsulating an IC chip in an LSI package, the IC chip 6 is surrounded by the inert gas 7, so that heat dissipated from the IC chip 6 cannot be absorbed sufficiently. . Therefore, L.S.
This method has the disadvantage of causing a decrease in the performance of I.

【０００４】また、特に消費電力の多いＬＳＩの場合に
は、ヒートシンクを別に装着することが必要となるとい
う欠点もある。[0004] In addition, especially in the case of an LSI that consumes a large amount of power, there is also a drawback that a heat sink needs to be separately installed.

【０００５】[0005]

【発明の目的】そこで、本発明はかかる従来のものの欠
点を解決すべくなされたものであって、その目的とする
ところは、ＩＣチップの放熱をヒートシンク等の特別の
放熱装置を付加することなく可能とした半導体集積回路
装置を提供することにある。[Object of the Invention] Therefore, the present invention has been made to solve the drawbacks of such conventional devices, and its purpose is to dissipate heat from an IC chip without adding a special heat dissipation device such as a heat sink. The object of the present invention is to provide a semiconductor integrated circuit device that makes it possible.

【０００６】[0006]

【発明の構成】本発明による半導体集積回路装置は、パ
ッケージと、前記パッケージ内に搭載されたＩＣチップ
と、前記ＩＣチップを浸漬するように前記パッケージ内
に密閉封入された絶縁性油とを含むことを特徴とする。A semiconductor integrated circuit device according to the present invention includes a package, an IC chip mounted in the package, and an insulating oil hermetically sealed in the package so as to immerse the IC chip. It is characterized by

【０００７】[0007]

【実施例】以下に図面を参照しつつ本発明の実施例を説
明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

【０００８】図１は本発明の実施例の断面図であり、図
４と同等部分は同一符号により示している。本発明では
、図４の従来の不活性ガス７の代りに絶縁性の油１によ
りＩＣチップ６を浸漬するようパッケージ４内に、この
絶縁性油１を満たす。そして、キャップ３によりパッケ
ージ内に空気が入らないように密閉封入した構造である
。FIG. 1 is a sectional view of an embodiment of the present invention, and parts equivalent to those in FIG. 4 are designated by the same reference numerals. In the present invention, the package 4 is filled with insulating oil 1 instead of the conventional inert gas 7 shown in FIG. 4 so that the IC chip 6 is immersed in the insulating oil 1. The structure is such that the cap 3 seals the package to prevent air from entering.

【０００９】図２に示すようにＩＣチップ６の取付け位
置を図１の例とは逆にしても良く、また、図３に示すよ
うに、キャップ封入位置を図１の例よりも高くして絶縁
油１を多く封入するような構造としても良い。As shown in FIG. 2, the mounting position of the IC chip 6 may be reversed from the example shown in FIG. 1, and as shown in FIG. A structure may be adopted in which a large amount of insulating oil 1 is sealed.

【００１０】0010

【発明の効果】以上のべた如く、本発明によれば、ＬＳ
Ｉパッケージ内に絶縁性油を封入してこれによりＩＣチ
ップを浸漬するようにしたので、ＩＣチップの放熱効果
が著しく向上し、また震動や衝撃をこの油により吸収す
ることができ、機械的強度が良好となるという効果があ
る。更に、ワイヤ同士の絶縁性が良好となり、ゴミによ
るショートを防止することが可能となり、信頼性が向上
する。[Effects of the Invention] As described above, according to the present invention, the LS
Since insulating oil is sealed inside the I package and the IC chip is immersed in this oil, the heat dissipation effect of the IC chip is significantly improved, and vibrations and shocks can be absorbed by this oil, improving mechanical strength. This has the effect of making it better. Furthermore, the insulation between the wires is improved, making it possible to prevent short circuits due to dust, and improving reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

【図１】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.

【図２】本発明の他の実施例を示す断面図である。FIG. 2 is a sectional view showing another embodiment of the present invention.

【図３】本発明の別の実施例を示す断面図である。FIG. 3 is a sectional view showing another embodiment of the invention.

【図４】従来の半導体集積回路装置の断面図である。FIG. 4 is a cross-sectional view of a conventional semiconductor integrated circuit device.

【符号の説明】[Explanation of symbols]

１　　絶縁性油 ４　　パッケージ ６　　ＩＣチップ 1 Insulating oil 4 Package 6 IC chip

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】　　パッケージと、前記パッケージ内に搭
載されたＩＣチップと、前記ＩＣチップを浸漬するよう
に前記パッケージ内に密閉封入された絶縁性油とを含む
ことを特徴とする半導体集積回路装置。1. A semiconductor integrated circuit device comprising a package, an IC chip mounted within the package, and insulating oil hermetically sealed within the package so as to immerse the IC chip. .
JP3162208A 1991-06-06 1991-06-06 Semiconductor integrated circuit device Pending JPH04360559A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3162208A JPH04360559A (en) 1991-06-06 1991-06-06 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3162208A JPH04360559A (en) 1991-06-06 1991-06-06 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH04360559A true JPH04360559A (en) 1992-12-14

Family

ID=15750026

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3162208A Pending JPH04360559A (en) 1991-06-06 1991-06-06 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH04360559A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310635A (en) * 1993-04-22 1994-11-04 Nec Corp Semiconductor device
EP0933650A2 (en) * 1998-01-28 1999-08-04 Canon Kabushiki Kaisha Two-dimensional image pickup apparatus
US6825472B2 (en) 2000-06-27 2004-11-30 Canon Kabushiki Kaisha Radiation imaging system
JP2012241657A (en) * 2011-05-23 2012-12-10 Denso Corp Fuel filter diagnostic system and filter cartridge

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310635A (en) * 1993-04-22 1994-11-04 Nec Corp Semiconductor device
EP0933650A2 (en) * 1998-01-28 1999-08-04 Canon Kabushiki Kaisha Two-dimensional image pickup apparatus
EP0933650A3 (en) * 1998-01-28 2000-08-02 Canon Kabushiki Kaisha Two-dimensional image pickup apparatus
US6897449B1 (en) 1998-01-28 2005-05-24 Canon Kabushiki Kaisha Two-dimensional image pickup apparatus
US6967333B2 (en) 1998-01-28 2005-11-22 Canon Kabushiki Kaisha Two dimensional image pick-up apparatus
US6825472B2 (en) 2000-06-27 2004-11-30 Canon Kabushiki Kaisha Radiation imaging system
JP2012241657A (en) * 2011-05-23 2012-12-10 Denso Corp Fuel filter diagnostic system and filter cartridge
US8655542B2 (en) 2011-05-23 2014-02-18 Denso Corporation Fuel filter diagnostic system and filter cartridge

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