JPH04359470A - Soi-cmosfet device - Google Patents

Abstract

PURPOSE:To achieve an improved operation at a low power supply voltage by setting a ratio of the thickness of a gate oxide film to the thickness of a buried oxide film in a specific range and a back gate voltage of an SOI- CMOSFET where a channel region is constituted by a genuine semiconductor to be set to approximately 1/2 of the power supply voltage. CONSTITUTION:A ratio of a thickness tfox of a gate oxide film to a thickness tfox of a buried oxide film is set to 0.1-1 range and also an SOI-CMOSFET where a channel region consists of a genuine semiconductor is constituted. Then, a backgate voltage Vgh which is half the voltage of a power supply voltage Vdd for operation is supplied to a back gate terminal of this SOI- CMOSFET. In this case, a voltage-driving circuit which consists of a series connection circuit of two resistors with a same resistance R is used, thus enabling an improved operation to be performed at a low power supply voltage.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to SOI-CMOSFET
Regarding equipment.

0002

2. Description of the Related Art An ideal SOI-CMOSFET device structure is shown in FIG. In FIG. 2, portions 1 to 10 and 11 are N-channel S
It is a part of OI-MOSFET, and is also designated by the drawing code 10.
, 11, 12 to 20 are P-channel SOI-MO
The SFET portion includes front gate terminals 1 and 12, back gate terminals 11, front gate electrodes 2 and 13, gate oxide films 3 and 14, drain terminals 4 and 15, 5, 16 is each drain electrode, 6 and 17 are each intrinsic semiconductor layer, 7 and 18 are each source electrodes, 8 and 19 are each source terminals, 9 and 20 are each buried oxide films, and 10 is a back gate. Now, the threshold voltage of the n-channel SOI-MOSFET in the SOI-CMOSFET having the device structure shown in FIG. 2 is expressed by the following equation (1) (the threshold voltage of the p-channel SOI-MOSFET is Although it is expressed by a different formula from formula (1) which has the same contents as the formula, in this specification, SOI-CM
Only the threshold voltage of an n-channel SOI-MOSFET in the OSFET is taken up as a representative and used for the explanation).

[0003] Vth≒0.3-(tfox/tbox)(Vgb
-Vfbb)+Vfbf...(1) However, Vt
h...threshold voltage of n-channel SOI-MOSFET, tfox...thickness of gate oxide film, tbox...thickness of buried oxide film, Vgb...back gate voltage, Vfbb...flat band potential of back gate, Vfb
f... flat band potential of the front gate, 0.3... source and channel potential barrier, and the buried oxide film thickness tbox is usually much larger than the gate oxide film thickness tfox, so The above equation (1) is expressed as the following equation (2), ignoring the second term. Vth≒0.3+Vfbf...(2) From equation (2) above, the threshold voltage of the n-channel SOI-MOSFET is approximately 0.
．． 8 volts (the threshold voltage of the p-channel SOI-MOSFET is also about 0.8 volts), but if the threshold voltage is about 0.8 volts as mentioned above, the operating power supply voltage is 5 volts. It can be operated conveniently in some cases.

0004

[Problems to be Solved by the Invention] As the degree of integration of integrated circuits increases, the voltage value of the operating power supply will increase from the current standard value of 5 volts to 3 to 3.3 volts or 1 volt in the future. It is expected that the voltage will be lowered to .5 volts, but in that case, it would be inconvenient for the circuit operation if the SOI-MOSFET threshold voltage was about 0.8 volts, so the voltage value of the operating power supply will be lowered. with SOI-MO
It is also necessary to lower the threshold voltage of the SFET, and a solution has been sought.

[0005]

[Means for Solving the Problems] The present invention provides an SOI-I in which the ratio of the thickness of the gate oxide film to the thickness of the buried oxide film is in the range of 0.1 to 1, and the channel region is made of an intrinsic semiconductor. SOI-CM using CMOSFET and setting the back gate voltage to approximately 1/2 of the power supply voltage
Provides OSFET devices.

[0005]

[Function] SO in which the ratio of the thickness tfox of the gate oxide film to the thickness tbox of the buried oxide film is set in the range of 0.1 to 1, and the channel region is made of an intrinsic semiconductor.
By setting the back gate voltage of the I-CMOSFET to approximately 1/2 of the power supply voltage, good operation can be achieved even with a low power supply voltage.

[0006]

[Example] Hereinafter, with reference to the accompanying drawings, SOI-
The specific contents of the CMOSFET device will be explained in detail. FIG. 1 is a block diagram showing a schematic configuration of an SOI-CMOSFET device according to the present invention. SOI of the present invention shown in FIG.
In the CMOSFET device, the same drawing numbers as those used in FIG. 2 are used for the component parts corresponding to the SOI-CMOSFET having the device structure shown in FIG. is the S of N channels.
The part of the OI-MOSFET is shown, and the drawing number 10
, 11, 12 to 20 are P-channel SOI-MO
It shows the SFET part. Also in Figure 1, 1, 12
are each front gate terminal, 11 is the back gate terminal, 2
, 13 are each front gate electrode, 3 and 14 are each gate oxide film, 4 and 15 are each drain terminal, 5 and 16 are each drain electrode, 6 and 17 are each intrinsic semiconductor layer, 7 and 18 are each source electrode, Reference numerals 8 and 19 indicate each source terminal, 9 and 20 indicate each buried oxide film, and 10 indicates a back gate. In FIG. 1, a voltage 1/2 of the operating power supply voltage Vdd is supplied as the back gate voltage Vgb to the back gate terminal 11 of the SOI-CMOSFET device of the present invention. In the illustrated embodiment, in order to supply 1/2 of the operating power supply voltage Vdd as the back gate voltage Vgb, the power supply voltage Vdd is formed by a series connection circuit of two resistors having the same resistance value R. Although a voltage dividing circuit is used, the above-described back gate voltage Vgb supply circuit is not limited to the illustrated configuration example.

[0007] The SOI-CMOSFET device of the present invention includes:
The ratio of the thickness of the gate oxide film to the thickness of the buried oxide film is 0.
．． Using an SOI-CMOSFET whose channel region is made of an intrinsic semiconductor,
The back gate voltage Vgb is set to approximately 1/2 of the operating power supply voltage Vdd, and a specific example will be described below. Now, for example, when the operating power supply voltage Vdd is 3 volts, the SOI-CMOS shown in FIG.
When it is desired to set the threshold voltage in the FET to 0.5 volts, a voltage of 1, which corresponds to 1/2 of the operating power supply voltage Vdd = 3 volts, is applied to the back gate terminal 11 of the SOI-CMOSFET device of the present invention. Provides a voltage of .5 volts. In this way, the operating power supply voltage V
The reason for supplying the back gate voltage Vgb with a voltage value of 1/2 of dd is to set similar threshold voltages for the N-channel SOI-MOSFET in the SOI-CMOSFET and the P-channel SOI-MOSFET in the SOI-CMOSFET. It is.

Now, the back gate voltage Vgb supplied to the back gate terminal 11 of the SOI-CMOSFET device
The fluctuation amount ΔVth of the threshold voltage that changes due to
-Vfbb)≒-(tfox/tbox)Vgb...
(3), but when the operating power supply voltage Vdd is 3 volts as described above, the SOI in FIG.
- When attempting to set the threshold voltage in the CMOSFET to 0.5 volts, the threshold voltage of 0.5 volts is a threshold voltage lower by 0.3 volts than the previously mentioned threshold voltage of 0.8 volts, so Gate oxide thickness tf required to lower the threshold voltage by 0.3 volts
The ratio between ox and the thickness tbox of the buried oxide film is (3)
From the formula, tfox/tbox=0.3/(Vdd/
2) It is calculated as ≒0.3/1.5=1/5. So, now the thickness of the gate oxide film tfox is set to 200.
In Angstrom, the thickness of the buried oxide film tb
ox is 0.1 micron, but if the thickness tfox of the gate oxide film and the thickness tbox of the buried oxide film are determined in this way, the threshold voltage of the N-channel SOI-MOSFET in the SOI-CMOSFET and the SOI- CMO
The threshold voltages of the P-channel SOI-MOSFET in the SFET are both 0.5 volts. S of the present invention
Ratio of gate oxide thickness to buried oxide thickness tfo when an OI-CMOSFET device is operated with an operating power supply voltage of 3 volts to 1.5 volts.
x/tbox will be set in the range of 0.1 to 1. Note that the thickness tfox of the gate oxide film and the thickness t of the buried oxide film in the conventional SOI-CMOSFET device
The ratio tfox/tbox with box shows a value smaller than 0.1.

[0009]

As is clear from the above detailed explanation, the SOI-CMOSFET device of the present invention has a gate oxide film thickness tfox and a buried oxide film thickness tbo.
SOI-CMOS in which the ratio to x is in the range of 0.1 to 1 and the channel region is made of an intrinsic semiconductor
By setting the back gate voltage of the FET to approximately 1/2 of the power supply voltage, it is possible to perform good operation even at a low power supply voltage while maintaining the ideal SOI-CMOSFET device structure.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an SOI-CMOSFET device of the present invention.

FIG. 2 is a diagram showing the device structure of an ideal SOI-CMOSFET.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1, 12... Front gate terminal, 2, 13... Front gate electrode, 3, 14... Gate oxide film, 4, 15... Drain terminal, 5, 16... Drain electrode, 6, 17... Intrinsic semiconductor layer, 7, 18... Source electrode, 8, 19... source terminal,
9, 20...Buried oxide film, 10...Back gate, 11...
back gate terminal,

Claims (1)

[Claims] 1. An SOI-CMO in which the ratio of the thickness of the gate oxide film to the thickness of the buried oxide film is in the range of 0.1 to 1, and the channel region is made of an intrinsic semiconductor.
Using SFET, the back gate voltage is approximately 1 of the power supply voltage.
/2 SOI-CMOSFET device.