JPH0870247A - Level shift circuit - Google Patents

Abstract

PURPOSE: To shift a level from a low voltage system to a high voltage system without increasing a chip area by forming a thickness of a gate oxide film of a high breakdown voltage MOS transistor (TR) receiving an input signal to be thinner than that of an oxide film of high breakdown voltage MOS TRs in cross connection. CONSTITUTION: In the level shift circuit converting a level of a low, voltage system into a level of a high voltage system, the thickness of a gate oxide film of high breakdown voltage MOS TRs M3, M4 receiving an input signal is formed to be thinner than that of a gate oxide film of the high breakdown voltage MOS TRs M1,M2 in cross connection. Thus, a chip area is reduced. Moreover, the gate oxide film of the MOB TRs M3, M4 is formed by the same process as the gate oxide film of the MOS TRs M5, M6 with a usual breakdown voltage, then the thickness of the gate oxide film of the MOS TRs M3, M4 is made thinner without addition of the special process and the manufacture process is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift circuit, and more particularly to a level shift circuit incorporated in an LCD driver IC.

[0002]

2. Description of the Related Art An LCD driver IC receives a low voltage system (for example, 5V system) signal from a CPU or the like, performs predetermined signal processing by a shift register or the like, and outputs the output by a level shift circuit to a high voltage system. The LCD panel is driven by converting it into a signal (for example, 40 system).
Therefore, the level shift circuit has a role of converting a low-voltage system signal into a high-voltage system signal, and one level shift circuit is required for each bit of the LCD driver IC. In recent years, with the increasing capacity of LCD panels,
The number of bits of the LCD driver also tends to increase significantly. For example, if the number of bits is 160 bits, it is necessary to incorporate 160 level shift circuits.

FIG. 1 is a diagram showing the structure of a level shift circuit. In the figure, MOS transistors M1, M2,
M3 and M4 are high breakdown voltage transistors, and the MOS transistors M5 and M6 are normal breakdown voltage transistors. Further, Vdd1 is a low-voltage power supply voltage (for example, Vdd1 = 3
V) and Vdd is the power supply voltage of the high voltage system (for example, Vdd = 40V).

The DC operation of this circuit is as follows. Now, when the input signal φ is at L level, M3 is off, M4 is on, M1 is on, and M2 is off, so that the node a becomes Vdd (40V) and the node b becomes Vss (0V). When the input signal φ is at H level, M3 is turned on and M4 is turned on.
Turns off, M1 turns off, and M2 turns on, so node a
Is Vss (0V) and node b is Vdd (40V). Therefore, this circuit uses Vdd1 / Vss (3V / 0V system) as V
The operation of converting to dd / Vss (40V / 0V system) is performed.

Next, the operation of this circuit in the transient state will be considered. Now, it is assumed that the transistor sizes of M1, M2, M3 and M4 are the same. Further, the on-resistance of each transistor is r1, r2, r3, r4. When the input signal φ changes from L to H, M3 changes from the off state to the on state. At this time, the voltage Va of the node a is expressed by the following equation. Va = r3 · Vdd / (r1 + r3) (1) Also, Vgs of M3 = Vdd1 = 3V, Vgs of M1 = Vdd =
Since it is 40V, the following equation holds.

R3 >> r1 (2) Therefore, Va≈Vdd (3) That is, even if the input changes from L to H, Va remains fixed at Vdd. Become. In this case, M2 does not change from OFF to ON, and this circuit does not operate. Therefore, from the above, the following conditions are necessary to perform the level shift operation.

Vdd-Va> Vth (M2) (4) Here, Vth (M2) is the absolute value of the threshold voltage of M2. Then, by substituting the Va of the equation (1) into the equation (4), Vdd / (1 + r3 / r1)> Vth (M2) (5) When the input signal φ changes from H to L, M4 is turned off. The state changes from ON to ON. Also in this case, the following conditions are required to perform the level shift operation in the same manner as above.

Vdd / (1 + r4 / r2)> Vth (M1) (6) Therefore, in order to perform the level shift operation, r3 / r
It can be seen that it is necessary to make the values of 1 and r4 / r2 as small as possible. Conventionally, as a means for this, MOS
The ON resistances r3 and r4 have been reduced by increasing the gate width (W) of the transistors M3 and M4 and setting the threshold voltage thereof to be small.

[0009]

However, since a large number of level shift circuits must be built in the LCD driver IC, increasing the transistor size of M3 and M4 increases the chip area of the IC. there were. On the other hand, setting the threshold voltages of M3 and M4 to be selectively low in the ion implantation process has a drawback that an additional manufacturing process is required.

[0010]

According to the present invention, in order to solve the above problems, the gate oxide film thickness (tox2) of the MOS transistors M3 and M4 is set to the MOS transistors M1 and M2.
The gate oxide film thickness (tox1) was made thinner (tox2 <tox1).
Further, the gate oxide films of the MOS transistors M3 and M4 were formed in the same step as the gate oxide films of the MOS transistors M5 and M6.

[0011]

Function: Generally, the drain current Id of the MOS transistor
Is given by the following equation. Id = μ · W · Vds · ε · (Vgs−Vth) / L · tox ··· (7) Therefore, the on-resistance r (Vds / Id) ∝ tox ··· (8) where Vds is Source-drain voltage, Vgs is gate-source voltage, ε is dielectric constant, L is channel length, and tox is gate oxide film thickness. That is, the on-resistance can be reduced by reducing the gate oxide film thickness. Therefore, by making the gate oxide film thickness (tox2) of the MOS transistors M3 and M4 thinner than the gate oxide film thickness (tox1) of the MOS transistors M1 and M2 (tox2 <tox1),
The conditions of the above formulas (5) and (6) can be satisfied.

In addition, even if the gate oxide film thickness (tox2) of M3 and M4 is reduced in this way, a high voltage (40 V) is not applied to the gate electrode of the circuit structure, so that there is no possibility of causing a breakdown voltage failure. Absent. Therefore, according to the above means, there is an advantage that the chip area can be reduced as compared with the conventional case.
Furthermore, by forming the gate oxide films of the MOS transistors M3 and M4 in the same step as the gate oxide films of the MOS transistors M5 and M6, the gate oxide film thickness (tox2) of M3 and M4 can be obtained without adding a special step. Since it can be thinned, it is also effective in reducing the number of manufacturing steps.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A level shift circuit according to an embodiment of the present invention will be described below with reference to the drawings. As shown in FIG. 1, the level shift circuit of this embodiment has P-channel type MOS transistors M1 and M2 whose gates and drains are cross-connected to each other, and a high power source Vdd (supplied to the sources of the MOS transistors M1 and M2). 40V), and the N-channel MOS transistor M connected between the drains of the MOS transistors M1 and M2 and the ground power supply Vss (0V).
3 and M4, and a signal φ and an inverted signal * φ input to the gates of the MOS transistors M3 and M4, respectively, and outputs a level-shifted signal from the connection point b of the MOS transistors M2 and M4. Then, the MOS transistors M1, M2, M3, and M4 are formed to have a high breakdown voltage, and an inverter M that generates an inversion signal * φ is formed.
The OS transistors M5 and M6 are normally formed to withstand voltage, and the gate oxide film thickness (tox2) of the MOS transistors M3 and M4 is made thinner than the gate oxide film thickness (tox1) of the MOS transistors M1 and M2 (tox2 <tox1). Is characterized by.

As described above, in order for this circuit to normally perform the level shift operation, it is necessary to satisfy the conditions of the expressions (5) and (6). By the way, since the on-resistance of the MOS transistor is proportional to the gate oxide film thickness tox as shown in the equation (8), the gate oxide film thickness (tox2) of the MOS transistors M3 and M4 is set to the gate of the MOS transistors M1 and M2. By making the thickness smaller than the oxide film thickness (tox1), it becomes possible to satisfy such a condition while suppressing an increase in the transistor size.

Next, the MOS transistors M1 and M
The device structures of 2, M3 and M4 will be described. As shown in FIG. 3, in the MOS transistors M1 and M2, the N well 2 is formed on the P-type Si substrate 1, and the film thickness tox1 (1000
A gate electrode 4 is formed on the gate oxide film 3 of Å), and a source layer 5 and a drain 6 layer are formed on both sides of the gate electrode 4. The drain layer 6 is composed of a low concentration P ⁻ layer 6A self-aligned with the gate electrode 4 and a high concentration P ⁺ layer 6B offset from the gate electrode. Since a high voltage (40 V) is applied to the gate electrode 4 and the drain 6 in the transistor, the gate oxide film 3 is formed relatively thick and the drain has an offset gate type high breakdown voltage structure.

On the other hand, the MOS transistors M3 and M4 are
As shown in FIG. 4, the film thickness tox2 (30
A gate electrode 8 is formed on the gate oxide film 7 of 0Å), and a source layer 9 and a drain layer 10 are formed on both sides of the gate electrode 8. The drain layer 10 is composed of a low concentration N ⁻ layer 10A self-aligned with the gate electrode 8 and a high concentration N ⁺ layer 10B offset from the gate electrode. Since a high voltage is not applied to the gate electrode 8 in the above transistor, the problem of gate breakdown voltage deterioration does not occur.

Further, the MOS transistors M5 and M6 are
As shown in FIG. 5, the structure is usually a breakdown voltage type structure. That is, the gate electrode 12 is formed on the P-type Si substrate 1 via the gate oxide film 11 having a film thickness tox2 (300Å), and the source layer 13 and the drain layer 14 are formed on both sides thereof.
Since the above transistors are normally breakdown voltage type, they do not have an offset drain structure.

Next, a method of manufacturing a MOS transistor which constitutes the level shift circuit of this embodiment will be described in comparison with a conventional example. First, the conventional manufacturing method is as shown in FIG.
By the first gate oxidation (1), the film thickness tox1 (1000
The gate oxide film of Å) is formed, and then the gate oxide film is etched, that is, the gate oxide film in the formation region of the normal breakdown voltage transistors M5 and M6 is selectively removed by etching. Next, the second gate oxidation (2) is performed, and the film thickness tox2 (300) is formed in the formation region of the normal breakdown voltage type transistors M5 and M6.
Å) Gate oxide film is formed. After that, in order to control the threshold voltage, the high voltage MOS transistor M3,
Channel ion implantation of M4 and normal withstand voltage MOS transistors M5 and M6 is performed respectively.

On the other hand, the manufacturing method according to the present invention is
It is shortened as shown in FIG. First, a gate oxide film having a film thickness tox1 (1000 Å) is formed by the first gate oxidation (1) in the same manner, but in the next gate oxide film etching, only the formation regions of the normal breakdown voltage transistors M5 and M6 are formed. Not only that, the oxide film in the formation region of the high breakdown voltage MOS transistors M3 and M4 is also removed at the same time. Next, the second gate oxidation (2) is performed to form a gate oxide film having a thickness of tox2 (300 Å). Then, channel ion implantation of the normal breakdown voltage transistors M5 and M6 and the high breakdown voltage MOS transistors M3 and M4 is performed. In this way, high withstand voltage MO
In order to reduce the gate oxide film thickness of the S transistors M3 and M4, the gate oxide film forming process of the normal breakdown voltage MOS transistors M5 and M6 is normally used, so that it can be manufactured without adding a special process. . Further, since the gate oxide film thickness is the same, the channel / ion implantation process for controlling the threshold voltage can be shared, and the manufacturing process can be shortened.

[0020]

As described above, according to the present invention,
The gate oxide film thickness (tox2) of the MOS transistors M3, M4 of the level shift circuit is set to the MOS transistors M1, M
It is made thinner than the gate oxide film thickness (tox1) of 2 (tox2 <to
x1). As a result, the level shift from the low voltage system to the high voltage system can be realized without increasing the chip area as in the conventional case.

Further, according to the present invention, the gate oxide films of the MOS transistors M3 and M4 are replaced by the MOS transistor M.
By forming the gate oxide film of M5 and M6 in the same process, the gate oxide film thickness (tox2) of M3 and M4 can be thinned without adding a special process, which also reduces the manufacturing process. effective.

[Brief description of drawings]

FIG. 1 is a circuit diagram illustrating a level shift circuit according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of the reshift circuit during a transient response.

FIG. 3 is a sectional view illustrating a structure of high breakdown voltage MOS transistors M1 and M2.

FIG. 4 is a cross-sectional view illustrating the structure of high breakdown voltage MOS transistors M3 and M4.

FIG. 5 is a sectional view illustrating a structure of normal breakdown voltage MOS transistors M5 and M6.

FIG. 6 is a process flow diagram illustrating a manufacturing process according to a conventional example.

FIG. 7 is a process flow diagram illustrating a manufacturing process according to an embodiment of the present invention.

[Explanation of symbols]

M1, M2, M3, M4 High voltage MOS transistor M5, M6 Normal voltage MOS transistor Vdd1 Low voltage power supply voltage Vdd High voltage power supply voltage φ Input signal r1 High voltage MOS transistor M1 ON resistance r3 High voltage MOS transistor M3 ON resistance 1 P-type substrate 2 N well 3 Gate oxide film 4 Gate electrode 5 Source layer 6 Drain layer 7 Gate oxide film 8 Gate electrode 9 Source layer 10 Drain layer 11 Gate oxide film 12 Gate electrode 13 Source layer 14 Drain layer

Continuation of front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/78

Claims (2)

[Claims] 1. One conductive channel type MOS transistors M1 and M2 whose gates and drains are cross-connected to each other,
The high power supply Vdd supplied to the sources of the MOS transistors M1 and M2, and the reverse conductive channel type M connected between the drains of the MOS transistors M1 and M2 and the ground power supply Vss.
OS transistors M3 and M4 and MOS transistor M
In the level shift circuit which outputs the signal level-shifted from the connection point of the MOS transistors M2 and M4, the level shift circuit having the signal φ and the inverted signal * φ respectively input to the gates of the MOS transistors M1 and M4.
A MOS transistor M which forms an inverter for generating an inversion signal * φ by forming 2, 2, M3 and M4 in a high withstand voltage type.
5 and M6 are formed in a normal breakdown voltage type, and the gate oxide film thickness (tox2) of the MOS transistors M3 and M4 is MO.
A level shift circuit characterized by being made thinner (tox2 <tox1) than the gate oxide film thickness (tox1) of the S transistors M1 and M2. 2. The level shift circuit according to claim 1, wherein the gate oxide films of the MOS transistors M3 and M4 are formed in the same step as the gate oxide films of the MOS transistors M5 and M6.