JPH04358429A - Path monitoring system - Google Patents

Path monitoring system

Info

Publication number
JPH04358429A
JPH04358429A JP3133152A JP13315291A JPH04358429A JP H04358429 A JPH04358429 A JP H04358429A JP 3133152 A JP3133152 A JP 3133152A JP 13315291 A JP13315291 A JP 13315291A JP H04358429 A JPH04358429 A JP H04358429A
Authority
JP
Japan
Prior art keywords
monitoring
path
bit
section
monitoring bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3133152A
Other languages
Japanese (ja)
Inventor
Yutaka Yoshida
豊 吉田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3133152A priority Critical patent/JPH04358429A/en
Publication of JPH04358429A publication Critical patent/JPH04358429A/en
Withdrawn legal-status Critical Current

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  • Debugging And Monitoring (AREA)
  • Computer And Data Communications (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Monitoring And Testing Of Transmission In General (AREA)

Abstract

PURPOSE:To specify a faulty section if a fault occurs in a section where the monitoring is not carried out between the devices or in other sections in a path monitoring system which monitors the communication state of a signal path set in a device or between the devices. CONSTITUTION:A monitoring bit inserting part 1 is provided to insert a correct monitoring bit to a main circuit 6 of an input part at the relevant time point together with a path monitoring part 2 which monitors the monitoring bit via the circuit 6, a path monitoring bit reinserting part 3 which reproduces a monitoring bit similar to that of the part 1, and a selector part 4 which detects the monitoring bit passed through the circuit 6 at a path detecting part 2, transmits the signal of the circuit 6 as it is if a fault is detected, and then selects the monitoring bit of the part 3 and sends it to the following circuit 6 if no fault is detected. Thus the part 4 decides to transmit the original monitoring bit to the following stage as it is or to transmit the monitoring bit inserted to the part 3.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は通信における装置内、ま
たは装置間の信号経路の状態を監視するパス監視方式に
関する。近年のデータ社会の発展に伴い、通信装置の重
要性がますます高まってきており、高信頼の装置並びに
伝送路が要求されている。このため、装置内又は装置間
の信号経路を監視し、経路中のある区間で障害が起こっ
た場合にその区間を予備の線路に切り替えるなりして信
頼性を高めている。このためパスの監視が非常に重要に
なってきている。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a path monitoring system for monitoring the state of a signal path within a communication device or between devices. With the development of the data society in recent years, the importance of communication devices is increasing, and highly reliable devices and transmission paths are required. For this reason, reliability is improved by monitoring the signal path within the device or between devices, and when a failure occurs in a certain section of the route, that section is switched to a backup line. For this reason, path monitoring has become extremely important.

【0002】0002

【従来の技術】従来のバス監視方式の接続構成図を図4
に示す。図4(a)は一つの区間毎にパス監視ビットの
挿入、検出を行う方式で、区間区間毎に独自にパス監視
を行うものである。図4(b)はその経路内への入力点
で監視ビットを付加する方式で、その監視ビットに従っ
て経路内の任意のポイントで監視を行うものである。
[Prior Art] Figure 4 shows a connection configuration diagram of a conventional bus monitoring system.
Shown below. FIG. 4A shows a method in which a path monitoring bit is inserted and detected for each section, and path monitoring is performed independently for each section. FIG. 4B shows a method in which a monitoring bit is added at an input point into the route, and monitoring is performed at an arbitrary point within the route according to the monitoring bit.

【0003】図において、21は監視ビット挿入部であ
り、その時点の正しい監視ビットの挿入を行うことが出
来るもの、22はパス検出部であり、監視ビット挿入部
21で挿入した監視ビットとの間でパスの監視を行って
いるもの、26は監視を行う主回路であり、装置内の回
路またはケーブルなどを指す。また、太線は信号の流れ
を示し、点線は監視区間の区切りを示している。
In the figure, 21 is a monitoring bit insertion unit that can insert the correct monitoring bit at that time, and 22 is a path detection unit that can insert the monitoring bit inserted by the monitoring bit insertion unit 21. 26 is a main circuit that performs monitoring, and refers to a circuit or cable within the device. Furthermore, thick lines indicate signal flows, and dotted lines indicate separations between monitoring sections.

【0004】点線で囲まれた部分A,B,C,Dはそれ
ぞれ主回路26を含み、例えば、Aの主回路はインタフ
ェース回路で64KHz と8Mhzの信号変換を行い
、B,Cの主回路はタイムスイッチ回路でタイミングの
ズレをチェックしたり、タイムスロットの変換を行った
りするバッファ回路から構成され、Dの主回路はインタ
フェース回路で8Mhzと64KHz の信号変換を行
い、入力端末と出力端末間のデータの入出力を行ってい
る。各主回路26はケーブル又は伝送路でA〜Dが接続
され、入力端末側からの伝送信号が主回路を経由してデ
ィジタル信号により出力端末側に伝送される。監視ビッ
ト挿入部21でディジタル信号のフレーム毎に監視ビッ
トが挿入され、主回路を経由した監視ビットをそれぞれ
のパス検出部22で検出し、主回路26並びに伝送路の
障害を監視している。
[0004] Portions A, B, C, and D surrounded by dotted lines each include a main circuit 26. For example, the main circuit of A is an interface circuit that converts signals between 64 KHz and 8 Mhz, and the main circuits of B and C are It consists of a buffer circuit that uses a time switch circuit to check timing discrepancies and converts time slots.The main circuit of D is an interface circuit that converts signals between 8Mhz and 64KHz, and connects input terminals and output terminals. Performing data input/output. Each main circuit 26 is connected to A to D by a cable or a transmission path, and a transmission signal from the input terminal side is transmitted as a digital signal to the output terminal side via the main circuit. A monitoring bit inserting section 21 inserts a monitoring bit into each frame of the digital signal, and each path detecting section 22 detects the monitoring bit passing through the main circuit, thereby monitoring failures in the main circuit 26 and the transmission path.

【0005】[0005]

【発明が解決しようとする課題】図4(a)の方式では
、ある区間から次の監視区間への区切れの部分a,b,
c,dの伝送路の部分が、僅かではあるが監視が全く行
われない状態になっている。また、図4(b)の方式で
は、入力点から出力点まで途切れることなく監視されて
いるが、任意のある区間Bで障害が発生すると異常が検
出されるが、その後の区間C,Dは正常、異常に関わら
ず異常と検出されてしまう。このため複数の区間で障害
が発生した場合、入力に近い方の障害区間が復旧しない
限り、他の障害区間の特定が不可能である。
[Problem to be Solved by the Invention] In the method shown in FIG. 4(a), the sections a, b,
The transmission path portions c and d are not monitored at all, although only slightly. In addition, in the method shown in Fig. 4(b), monitoring is performed without interruption from the input point to the output point, but if a failure occurs in an arbitrary section B, an abnormality is detected, but the subsequent sections C and D are Regardless of whether it is normal or abnormal, it will be detected as abnormal. Therefore, if a fault occurs in multiple sections, it is impossible to identify other faulty sections unless the faulty section closest to the input is restored.

【0006】本発明は、図4(a)の方式のように監視
が全く行われていない区間を作らず、且つ図4(b)の
方式のように複数の区間で障害が発生した場合に障害区
間の特定が不可能にならない、パス監視方式を提供する
ことを目的とする。
[0006] The present invention does not create sections where no monitoring is performed as in the method shown in FIG. The purpose of the present invention is to provide a path monitoring method that does not make it impossible to identify faulty sections.

【0007】[0007]

【課題を解決するための手段】本発明の原理構成図を図
1に示す。図において、1は監視ビット挿入部であり、
その時点の正しい監視ビットを入力部の主回路6に挿入
する。2はパス検出部で主回路6を経由した監視ビット
の監視を行っている。3は監視ビット挿入部1と同様な
監視ビットを再生するパス監視ビット再挿入部、4は主
回路6を経由した監視ビットをパス検出部2で検出し、
障害でなければ主回路6の信号をそのまま通し、障害で
あればパス監視ビット再挿入部3の監視ビットを選択し
て次の主回路6に送出するセレクタ部を示す。6は監視
を行う主回路であり、装置内の回路又はケーブルなどを
指す。また、太線は信号の流れを示し、点線は監視区間
の区切りを示している。
[Means for Solving the Problems] A diagram of the principle configuration of the present invention is shown in FIG. In the figure, 1 is a monitoring bit insertion section,
The correct monitoring bit at that time is inserted into the main circuit 6 of the input section. Reference numeral 2 denotes a path detection unit which monitors the monitoring bits passed through the main circuit 6. 3 is a path monitoring bit reinsertion unit that reproduces monitoring bits similar to the monitoring bit insertion unit 1; 4 is a path detection unit 2 that detects the monitoring bits that have passed through the main circuit 6;
A selector section is shown that passes the signal of the main circuit 6 as is if there is no failure, and selects the monitoring bit of the path monitoring bit reinsertion section 3 and sends it to the next main circuit 6 if there is a failure. 6 is a main circuit for monitoring, which refers to a circuit or cable within the device. Furthermore, thick lines indicate signal flows, and dotted lines indicate separations between monitoring sections.

【0008】本方式は基本的には従来の図4(a)の方
式と同じ監視方式を採用しているが、監視ビット挿入部
1を入力部の主回路6に接続し、各監視区間において、
パス検出部2とパス監視ビット再挿入部3とセレクタ部
4とを主回路6の後に接続し、検出点の直後に監視ビッ
ト挿入部1と同様のパス監視ビット再挿入部3を設け、
セレクタ部4により、元々の監視ビットをそのまま後方
に送出するか、パス監視ビット再挿入部3で挿入した監
視ビットを送出するかを選択するように構成する。
This method basically employs the same monitoring method as the conventional method shown in FIG. 4(a), but the monitoring bit insertion section 1 is connected to the main circuit 6 of the input section, and the ,
A path detection section 2, a path monitoring bit reinsertion section 3, and a selector section 4 are connected after the main circuit 6, and a path monitoring bit reinsertion section 3 similar to the monitoring bit insertion section 1 is provided immediately after the detection point.
The selector unit 4 is configured to select whether to send out the original monitoring bit as it is or to send out the monitoring bit inserted by the path monitoring bit reinsertion unit 3.

【0009】[0009]

【作用】本発明の監視ビットのタイムチャートを図2に
示す。図において、■は入力データで1フレーム8KH
z毎に監視ビット挿入位置に‘0’又は‘1’を挿入す
る。■は主回路6を経由したデータで監視ビット挿入位
置がシフトされている。■はパス検出部2に挿入される
監視ビットで、監視ビット挿入位置の‘0’又は‘1’
を監視する。 ■は主回路6を経由したデータの監視ビット■とパス検
出部2の監視ビット■のEXORを取り、同一であれば
‘0’を送出し、同一でなければ‘1’を送出する。同
一であれば■の様にセレクタ部4からは主回路からの監
視ビットがそのまま送出され、同一でなければ■の様に
セレクタ部4を制御してパス監視ビット再挿入部3から
の監視ビットが再挿入される。
[Operation] A time chart of the monitoring bit of the present invention is shown in FIG. In the figure, ■ is input data of 8KH per frame.
'0' or '1' is inserted into the monitoring bit insertion position for each z. 3 is data that has passed through the main circuit 6, and the monitoring bit insertion position has been shifted. ■ is a monitoring bit inserted into the path detection unit 2, and '0' or '1' at the monitoring bit insertion position
monitor. (2) performs an EXOR operation on the monitoring bit (2) of the data that has passed through the main circuit 6 and the monitoring bit (2) of the path detection unit 2, and if they are the same, it sends out '0', and if they are not the same, it sends out '1'. If they are the same, the monitor bit from the main circuit is sent as is from the selector unit 4 as shown in ■; if not, the monitor bit from the path monitor bit reinsertion unit 3 is sent out by controlling the selector unit 4 as shown in ■. is reinserted.

【0010】従って、ある区間で障害が発生してもセレ
クタ部4により、パス監視ビット再挿入部3からその時
点で正しい監視ビットの挿入を行うことが出来るので、
そのあとの区間の監視を行うことが可能となる。
Therefore, even if a failure occurs in a certain section, the selector section 4 allows the path monitoring bit reinsertion section 3 to insert the correct monitoring bit at that point.
It becomes possible to monitor the subsequent section.

【0011】[0011]

【実施例】本発明の実施例の接続構成図を図3に示す。 図はN枚のパッケージで構成されている装置において、
全ての入出力点にパス監視検出部、挿入部及びセレクタ
部を持たせ、セレクタ部は各ポイントごとに自由に選択
できるようにする。また、1枚目のパッケージの入力側
は、パス監視をしないようにマスク部を持つようにする
Embodiment FIG. 3 shows a connection configuration diagram of an embodiment of the present invention. The figure shows a device consisting of N packages.
All input/output points are provided with a path monitoring detection section, an insertion section, and a selector section, and the selector section can be freely selected for each point. Further, the input side of the first package is provided with a mask portion so as not to perform path monitoring.

【0012】図において、10は1枚目のパッケージ、
20は2枚目のパッケージ、30はN枚目のパッケージ
を示し、11は監視ビット挿入部、12は入力パス検出
部、13はパス監視ビット再挿入部、14は入力セレク
タ部、15はマスク部、16は主回路、17は出力セレ
クタ部、18は出力パス検出部を示す。
In the figure, 10 is the first package;
20 is the second package, 30 is the Nth package, 11 is a monitoring bit insertion section, 12 is an input path detection section, 13 is a path monitoring bit reinsertion section, 14 is an input selector section, and 15 is a mask. 16 is a main circuit, 17 is an output selector section, and 18 is an output path detection section.

【0013】1枚目のパッケージ10には、当然監視ビ
ットが入力されないので、マスク部15により入力パス
検出部12で検出しないよう設定して、入力セレクタ部
14もその時点での監視ビットを挿入するように選択す
る。その他の主回路16の出力側は前述したように監視
を行う。各パッケージの入力側と出力側で監視を行って
いるのでパッケージ内の障害か、パッケージ間の障害か
を切り分けすることが出来る。任意の点で障害が発生し
た場合、検出した直後のポイントで入力セレクタ部14
により、その時点での正しい監視ビットに切り替える。 これにより複数箇所の障害発生にも対応可能になる。
Naturally, the monitoring bit is not input to the first package 10, so the mask section 15 is set so that the input path detection section 12 does not detect it, and the input selector section 14 also inserts the monitoring bit at that point. choose to do so. The other output sides of the main circuit 16 are monitored as described above. Since the input and output sides of each package are monitored, it is possible to isolate whether the problem is within a package or between packages. If a failure occurs at any point, the input selector unit 14
to switch to the currently correct monitoring bit. This makes it possible to deal with failures occurring in multiple locations.

【0014】上記実施例では、一装置内に限った監視を
行っているが、同じ監視方式を持つ装置と組合わせるこ
とによって、マスク部15を解除しセレクタ部14も前
方のものを選択するようにすることにより、一装置を超
えて全く同じ精度て装置間のパス監視を行うことが容易
に出来る。
In the above embodiment, monitoring is performed only within one device, but when combined with a device having the same monitoring method, the mask portion 15 is released and the selector portion 14 also selects the one in front. By doing so, it is possible to easily monitor paths between devices with exactly the same accuracy for more than one device.

【0015】[0015]

【発明の効果】以上説明したように、本発明によればあ
る区間で障害が発生してもその時点での正しい監視ビッ
トの挿入を行うことが出来るので、そのあとの区間の監
視を行うことが可能となるため、複数箇所の障害が生じ
ても障害箇所の特定が可能となる効果を奏し、また、実
施例に示したようにすることによって装置内に留まらず
、装置間のパス監視が容易且つ性格に可能となる効果を
奏し、かかる通信装置の信頼性向上に寄与するところが
大きい。
[Effects of the Invention] As explained above, according to the present invention, even if a failure occurs in a certain section, it is possible to insert the correct monitoring bit at that point, so that the subsequent sections can be monitored. This has the effect of making it possible to identify the fault location even if a fault occurs at multiple locations.In addition, by doing as shown in the example, path monitoring between devices can be performed not only within the device. This has the effect of being easily and easily possible, and greatly contributes to improving the reliability of such communication devices.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】  本発明の原理構成図[Figure 1] Principle configuration diagram of the present invention

【図2】  本発明のタイムチャート[Figure 2] Time chart of the present invention

【図3】  実施例の接続構成図[Figure 3] Connection configuration diagram of the embodiment

【図4】  従来例の接続構成図[Figure 4] Connection configuration diagram of conventional example

【符号の説明】[Explanation of symbols]

1,11,21  監視ビット挿入部 2,12,18,22  パス検出部 3,13  パス監視ビット再挿入部 4,14,17  セレクタ部 6,16,26  主回路 10,20,30  パッケージ 15  マスク部 1, 11, 21 Monitor bit insertion part 2, 12, 18, 22 Path detection section 3,13 Path monitoring bit reinsertion unit 4, 14, 17 Selector section 6, 16, 26 Main circuit 10, 20, 30 package 15 Mask part

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】  通信における装置内、または装置間の
信号経路の状態を監視するパス監視方式において、その
時点の正しい監視ビットを入力部の主回路(6)に挿入
する監視ビット挿入部(1)と、主回路(6)を経由し
た監視ビットの監視を行うパス監視部(2)と、該監視
ビット挿入部(1)と同様な監視ビットを再生するパス
監視ビット再挿入部(3)と、主回路(6)を経由した
監視ビットをパス検出部(2)で検出し、障害でなけれ
ば主回路(6)の信号をそのまま通し、障害であればパ
ス監視ビット再挿入部(3)の監視ビットを選択して次
の主回路(6)に送出するセレクタ部(4)を有し、該
セレクタ部(4)により、元々の監視ビットをそのまま
後方に送出するか、パス監視ビット再挿入部(3)で挿
入した監視ビットを送出するかを選択することを特徴と
するパス監視方式。
1. In a path monitoring method for monitoring the state of a signal path within a device or between devices in communication, a monitoring bit insertion unit (1) inserts the correct monitoring bit at that time into a main circuit (6) of an input unit. ), a path monitoring section (2) that monitors the monitoring bits passed through the main circuit (6), and a path monitoring bit reinsertion section (3) that reproduces the same monitoring bits as the monitoring bit insertion section (1). The path detection unit (2) detects the monitoring bit that has passed through the main circuit (6), and if there is no failure, the signal from the main circuit (6) is passed through as is, and if there is a failure, the path monitoring bit reinsertion unit (3) detects the monitoring bit that has passed through the main circuit (6). ) and sends it to the next main circuit (6).The selector part (4) selects whether to send the original monitoring bit backwards as it is or to send it to the next main circuit (6). A path monitoring method characterized by selecting whether to transmit the monitoring bit inserted by the reinsertion unit (3).
【請求項2】  上記構成において、入力側に監視ビッ
ト挿入部とパス検出部とセレクタ部とを有し、該パス検
出部にマスク部を設け、装置内に留まらず、装置間のパ
ス監視を行うことを特徴とする請求項1記載のパス監視
方式。
2. In the above configuration, the input side includes a monitoring bit insertion section, a path detection section, and a selector section, and the path detection section is provided with a mask section, so that path monitoring between devices without remaining within the device is performed. 2. The path monitoring method according to claim 1, wherein:
JP3133152A 1991-06-05 1991-06-05 Path monitoring system Withdrawn JPH04358429A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3133152A JPH04358429A (en) 1991-06-05 1991-06-05 Path monitoring system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3133152A JPH04358429A (en) 1991-06-05 1991-06-05 Path monitoring system

Publications (1)

Publication Number Publication Date
JPH04358429A true JPH04358429A (en) 1992-12-11

Family

ID=15097927

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3133152A Withdrawn JPH04358429A (en) 1991-06-05 1991-06-05 Path monitoring system

Country Status (1)

Country Link
JP (1) JPH04358429A (en)

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Effective date: 19980903