JPH0435777B2 - - Google Patents

Info

Publication number
JPH0435777B2
JPH0435777B2 JP57138535A JP13853582A JPH0435777B2 JP H0435777 B2 JPH0435777 B2 JP H0435777B2 JP 57138535 A JP57138535 A JP 57138535A JP 13853582 A JP13853582 A JP 13853582A JP H0435777 B2 JPH0435777 B2 JP H0435777B2
Authority
JP
Japan
Prior art keywords
line
absolute value
operand
circuit
operands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57138535A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5930143A (ja
Inventor
Akira Yamaoka
Koji Nakamura
Masahiro Hashimoto
Kenichi Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57138535A priority Critical patent/JPS5930143A/ja
Publication of JPS5930143A publication Critical patent/JPS5930143A/ja
Publication of JPH0435777B2 publication Critical patent/JPH0435777B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
JP57138535A 1982-08-11 1982-08-11 演算処理方式 Granted JPS5930143A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57138535A JPS5930143A (ja) 1982-08-11 1982-08-11 演算処理方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57138535A JPS5930143A (ja) 1982-08-11 1982-08-11 演算処理方式

Publications (2)

Publication Number Publication Date
JPS5930143A JPS5930143A (ja) 1984-02-17
JPH0435777B2 true JPH0435777B2 (en, 2012) 1992-06-12

Family

ID=15224420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57138535A Granted JPS5930143A (ja) 1982-08-11 1982-08-11 演算処理方式

Country Status (1)

Country Link
JP (1) JPS5930143A (en, 2012)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61103243A (ja) * 1984-10-25 1986-05-21 Nec Corp 減算装置
JPS61177542A (ja) * 1985-02-01 1986-08-09 Nec Corp 符号補数・符号絶対値併用加減算装置
JPH0371329A (ja) * 1989-08-11 1991-03-27 Fujitsu Ltd 算術論理演算処理装置の演算制御回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5852747A (ja) * 1981-09-25 1983-03-29 Nec Corp 加減算回路

Also Published As

Publication number Publication date
JPS5930143A (ja) 1984-02-17

Similar Documents

Publication Publication Date Title
US5469377A (en) Floating point computing device for simplifying procedures accompanying addition or subtraction by detecting whether all of the bits of the digits of the mantissa are 0 or 1
US5136536A (en) Floating-point ALU with parallel paths
US4617641A (en) Operation unit for floating point data having a variable length exponent part
US4110831A (en) Method and means for tracking digit significance in arithmetic operations executed on decimal computers
US4692891A (en) Coded decimal non-restoring divider
JPH0435777B2 (en, 2012)
JPH0545980B2 (en, 2012)
US3489888A (en) Floating point look-ahead binary multiplication system utilizing two's complement notation for representing negative numbers
JPH1091395A (ja) プロセッサ
US4951238A (en) Processor for executing arithmetic operations on input data and constant data with a small error
JPH07118654B2 (ja) 算術演算装置
US4810995A (en) Arithmetic and logic operating unit
JP2807170B2 (ja) 演算装置
JP4159565B2 (ja) ベクトル積和演算回路
EP0442220B1 (en) Decoder
US5724275A (en) Fast multi-operand bit pattern detection method and circuit
JP2856792B2 (ja) 浮動小数点数演算装置
JP2752698B2 (ja) 浮動小数点加減算回路
JP3205020B2 (ja) 演算装置
JP3522387B2 (ja) パイプライン演算装置
JPS62259140A (ja) アドレス生成回路
JP2555967B2 (ja) 浮動小数点加減算器
JPH04151729A (ja) 浮動小数点累算器
JPH04191925A (ja) 演算処理装置
JPH03150631A (ja) １０進除算回路