JPH04355950A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To protect a small signal amplitude circuit against malfunction by a method wherein small signal wirings are collectively arranged taking advantage of the upper wiring layer of a semiconductor integrated circuit. CONSTITUTION:Small signal wirings 11 are arranged on a second large signal wiring 12b through the intermediary of an insulating film film 14d. The small signal wirings 11 are made to serve as an inter-macro wiring. A first large signal wiring 12a, the second large signal wiring 12b, and the small signal wirings are formed on a first wiring layer, a second layer, and an uppermost third wirings layer taking advantage of three wiring layers. By this setup, in a semiconductor integrated circuit provided with a large number of inter- macro wirings at an EDL signal level, not only a capacitance coupling between adjacent wirings is not required to be taken into consideration but also a shielding electrode is not required to be additionally provided, so that a semiconductor integrated circuit of this design can be made simple in design, easily designed, and enhanced in degree of integration.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention applies to CMOS (Complete
Mentary Metal Oxide Semi
conductor) circuit, and ECL (Emitte
The present invention relates to a semiconductor integrated circuit that operates using a plurality of signals having mutually different signal amplitudes, such as a semiconductor integrated circuit that includes both circuits of a (Coupled Logic) circuit.

0002

2. Description of the Related Art An example of a semiconductor integrated circuit in which a small signal wiring with a small signal amplitude is integrated on the same semiconductor integrated circuit as a large signal wiring with a large signal amplitude is a sense amplifier of a memory integrated circuit. In such a semiconductor integrated circuit in which small signal wiring and large signal wiring coexist, noise may occur on the small signal wiring side when a signal changes on the large signal wiring side due to capacitive coupling between the two wirings, resulting in malfunction. As a countermeasure to this problem, widening the distance between the small signal wiring and the adjacent large signal wiring is usually used, and semiconductor integrated circuits have been proposed in which shielding electrodes are provided below, above, and on both sides of the small signal wiring ( JP-A-2
-82531 publication).

FIG. 10 is a cross-sectional view showing the conventional semiconductor integrated circuit described above.

An insulating film 104a is formed on the semiconductor substrate 103.
, 104b, and 104c, the small signal wiring 101 is arranged. An insulating film 1 is provided below this small signal wiring 101.
04c, and an insulating film 1 above.
04d, and an insulating film 1 on both sides.
A shielding electrode 106b is disposed to surround the small signal wiring 101 via 04d. Shield electrodes 106a, 106
b and 106c are connected to a power source or the like and have a fixed potential.

In the semiconductor integrated circuit configured in this manner, noise generated due to changes in signals flowing through the large signal wirings 102a, 102b, and 102c is absorbed by the shielding electrodes 106a, 102b, and 102c.
Since it is shielded by 106b and 106c, it is possible to prevent a small signal amplitude circuit such as a sense amplifier from malfunctioning due to a change in the level of the signal flowing through the small signal wiring 101.

[0006]

However, in the conventional semiconductor integrated circuit described above, since the shield electrodes 106a, 106c or 106a, 106b, 106c are arranged individually for each small signal wiring 101, the memory This is an effective method when the number of small signal wires is small, such as in the sense amplifier circuit of Electrodes must be frequently placed on the semiconductor integrated circuit, and the shielding electrode becomes an obstacle to the wiring path, making the layout design extremely complicated, and the wiring density also decreases. .

Furthermore, it is virtually impossible to apply the above-described method to an integrated circuit as described below.

In other words, as the degree of integration has increased, it has become difficult to design an entire semiconductor integrated circuit chip at once. Therefore, it is divided into multiple macrocells by function, and circuit design is performed for each. After designing the layout,
A so-called hierarchical design method is widely used in which the design of one semiconductor integrated circuit chip is completed by arranging macro cells and wiring between the macro cells. FIG. 11 shows a conceptual diagram of a semiconductor integrated circuit chip designed using the hierarchical design method.
11 is wired by inter-macro wiring (not shown). Furthermore, the macro cells 111-1 and 111-4 are connected to a plurality of inter-macro wiring lines 111 passing over the macro cell 111-3.
-1, and macrocell 111-1 is interconnected by 11
1-6 are also interconnected by a plurality of inter-macro wirings 112-2 passing over macro cells 111-3 and 111-5. Each macrocell is mainly CMOS
It includes a large number of elements necessary to construct a circuit, and macro wiring is performed between the elements to realize a specified function using multiple wiring layers. In a semiconductor integrated circuit designed using the hierarchical design method shown in FIG. 11, the length of the inter-macro wiring 112 connecting macro cells becomes extremely long, and the capacitance of the wiring increases, causing a delay in signal propagation between macro cells. However, in order to reduce this, conventional BiCMOS
(Bipolar CMOS) circuit into macrocell 11
1 and thereby drive the inter-macro wiring 112.

However, as large-scale integration and multifunctional integration due to miniaturization of elements will continue, the number of macro cells mounted on a single semiconductor integrated circuit will increase, and the wiring paths between macros will become more complex. Wire lengths are expected to increase, and on the other hand, there is also a demand for higher-speed operation of semiconductor integrated circuits, so in order to further reduce signal propagation delays in interconnects between macros, we are replacing conventional BiCMOS circuits with even higher load capacitance driving capabilities. Consideration has begun to be given to the use of ECL circuits. FIG. 12 is a macro cell configuration diagram when the signal level of the inter-macro wiring is set to the ECL level (normally 0.5 volt amplitude). In Figure 12, inter-macro wiring 1
12, an ECL level signal flows through the macro cell 111, an ECL/CMOS level conversion circuit 121, a CMOS logic circuit 122 mainly composed of CMOS, and a CMOS
Consists of S/ECL level conversion circuit 123, ECL/C
MOS level conversion circuit 121 converts ECL level to CMO
Perform level conversion to S level (usually 5 volt amplitude),
The CMOS logic circuit 122 performs a logical operation of the function specified in the macro cell 111, and the CMOS/ECL level conversion circuit 123 sends the signal as an ECL level again to the inter-macro wiring 112 via the built-in ECL circuit.

By adopting the configuration shown in FIG. 12, it is possible to reduce delays even when large-scale integration progresses in the future, but on the other hand, as the number of macro cells increases,
The number of interconnects between macro cells increases dramatically, and the length of the interconnects also increases, making the design of the conventional semiconductor integrated circuit shown in FIG. 10 extremely complicated and impossible.

The present invention has been made in view of such problems, and is capable of avoiding malfunctions of the small signal amplitude circuit and reducing the number of small signal wirings in a semiconductor circuit equipped with a large signal amplitude circuit and a small signal amplitude circuit. An object of the present invention is to provide a semiconductor integrated circuit that is easy to design and can be highly integrated even when there are a large number of semiconductor devices.

0012

[Means for Solving the Problems] A semiconductor integrated circuit of the present invention includes a large signal wiring through which a signal with a large amplitude flows and a small signal wiring through which a signal with a small amplitude flows. The present invention is characterized in that a plurality of small signal wirings are arranged together, and the small signal wiring is arranged using an upper wiring layer in the semiconductor integrated circuit.

[0013]

[Operation] In the present invention, a plurality of small signal wirings are arranged together in an upper wiring layer. The amplitude of the signals flowing through these small signal wires is small, so even if they are placed close to each other on the same wiring layer, the noise generated due to changes in other small signal wires is extremely small and can be virtually ignored. In addition, by placing the small signal wirings together in the upper wiring layer, it is possible to reduce the capacitive coupling between the small signal wirings and the large signal wirings placed in the lower wiring layer. By suppressing noise generated in small signal wiring due to changes in
Malfunctions of the small signal amplitude circuit can be avoided. In order to facilitate the wiring layout design between elements in a macro cell, two or more wiring layers are usually used, one or more each in the X direction and the Y direction perpendicular to this, so for example, the number of wiring layers is three or more. In a semiconductor integrated circuit, small signal wirings are placed together on the topmost wiring layer, or in a semiconductor integrated circuit with four or more wiring layers, small signal wirings are placed together on the topmost wiring layer and the wiring layer below it. It is effective to implement the above structure. Furthermore, by arranging a noise shielding electrode that covers most of the semiconductor chip, for example, between the wiring layer where the small signal wiring is provided and the lower layer wiring layer where the large signal wiring is provided, the small signal wiring and the large signal wiring are Capacitive coupling with the wiring can be significantly reduced, and malfunctions of the small signal amplitude circuit can be more reliably avoided. In addition, the interlayer insulating film interposed between the wiring layer where the small signal wiring is provided and the lower wiring layer where the large signal wiring is provided may be thickened.
Alternatively, the capacitive coupling between the two can be reduced by forming them with a material having a low dielectric constant. Furthermore, if part of the large signal wiring is also installed in the upper wiring layer where the small signal wiring is arranged together in a plan view, the boundary between the group of small signal wiring and the large signal wiring is the interval between the small signal wiring. Since they are separated by more than , it is possible to suppress noise in small signal wirings caused by changes in signals flowing to large signal wirings arranged in the same wiring layer in plan view. In addition, if a power supply line whose potential does not change is placed at the boundary between a group of small signal wirings and a large signal wiring in a plan view, this power supply line also acts as a shielding electrode, causing changes in the signal flowing to the large signal wiring. Noise in small signal wiring can be further reduced. Furthermore, by arranging only the small signal wiring and power supply line in the upper wiring layer, there is no large signal wiring that can be a source of noise in the upper wiring layer where the small signal wiring is placed, so that the signal flows to the large signal wiring. Noise in small signal wiring caused by signal changes can be reduced. Furthermore, capacitive coupling between the small signal wiring and the large signal wiring can also be reduced by separating the small signal wiring and the large signal wiring at the portions where they intersect in plan view by two or more wiring levels.

[0014]

Embodiments Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a sectional view showing a first embodiment of the present invention. In this embodiment, the macro cell 111-3 in FIG.
and macro cells 111-1 and 111-4 passing over it.
A part of the inter-macro wiring 112-1 that interconnects the two is shown. A plurality of first large signal wirings 12a are arranged in parallel to each other on the semiconductor substrate 13 with an insulating film 14a interposed therebetween. An insulating film 1 is formed on this first large signal wiring 12a.
4b, a plurality of second large signal wirings 12b are arranged parallel to each other, and the first large signal wiring 12a and the second large signal wiring 12b are arranged in parallel with each other.
The large signal wiring 12b is connected by a through hole 15 as necessary. The second large signal wiring 12b is formed substantially perpendicular to the first large signal wiring 12a in plan view, and is formed between the first large signal wiring 12a and the second large signal wiring 12b.
Wiring between elements within the macrocell is done. On this second large signal wiring 12b, a plurality of small signal wirings 11 are arranged with an insulating film 14c interposed therebetween.
An insulating film 14d is formed thereon. This small signal wiring 11 is provided as an inter-macro wiring (112-1).

In this embodiment, three wiring layers are used to connect the first large signal wiring 12a and the second large signal wiring 12b.
are formed in the first layer and the second layer, respectively, and the small signal wiring 11 is formed in the third layer, which is the uppermost layer. This results in
Even in semiconductor integrated circuits that have a large number of interconnects between macros at the ECL signal level, there is no need to consider capacitive coupling with adjacent interconnects, and there is no need to form a special shielding electrode, making the design simple and easy, and the integration density can be reduced. It's also expensive.

FIG. 2 is a sectional view showing a second embodiment of the present invention. This embodiment also has interconnects between macros (112-1, 112
-2) passage structure. A plurality of first large signal wirings 22a are arranged in parallel to each other on the semiconductor substrate 23 with an insulating film 24a interposed therebetween. This first large signal wiring 22a
A plurality of second large signal wirings 22b are arranged above in parallel with each other with an insulating film 24b interposed therebetween, and the first large signal wiring 22a and the second large signal wiring 22b can be passed through as necessary. It is connected through the hole 25a. The second large signal wiring 22b is formed substantially perpendicular to the first large signal wiring 22a in plan view, and the elements in the macro cell are connected to the first large signal wiring 22a and the second large signal wiring 22b. Wiring has been done between them. On this second large signal wiring 22b, a plurality of small signal wirings 21a are arranged in parallel with each other with an insulating film 24c interposed therebetween. The first small signal wiring 21a is formed substantially perpendicular to the second large signal wiring 22b in plan view, and is arranged substantially parallel to the first large signal wiring 22a. A plurality of second small signal wirings 21b are arranged in parallel with each other on the first small signal wiring 21a with an insulating film 24d interposed therebetween. The second small signal wiring 21b is formed substantially perpendicular to the first small signal wiring 21a in plan view,
It is arranged substantially parallel to the second large signal wiring 22b. An insulating film 24e is formed on this second small signal wiring 21b. The first small signal wiring 21a and the second small signal wiring 21b are used as inter-macro wiring.

In this embodiment, four wiring layers are used to form the first large signal wiring 22a and the second large signal wiring 22b in the first and second layers, respectively. The signal wiring 22a and the second small signal wiring 22b are formed in the third layer immediately below the uppermost layer and the fourth layer immediately below the uppermost layer, respectively. As a result, even in a semiconductor integrated circuit having a large number of interconnects between macros at the ECL signal level, there is no need to consider capacitive coupling with adjacent interconnects, and there is no need to form a special shield electrode, as shown in the first implementation shown in FIG. Although it is similar to the example, since the small signal wirings are arranged using two wiring layers orthogonal to each other, it is possible for the small signal wirings to intersect with each other. The design is simpler and easier, and the degree of integration is also significantly improved.

FIG. 3(a) is a plan view showing a third embodiment of the present invention, and FIG. 3(b) is a sectional view taken along line IIIb--IIIb in FIG. 3(a). In this embodiment, the inter-macro wiring 112-1 that extends from the macro cell 111-1 to the macro cell 111-3 in FIG.
Mainly shows the structure connected to. A plurality of first large signal wirings 3 are arranged on the semiconductor substrate 33 via an insulating film 34a.
2a are arranged parallel to each other. On this first large signal wiring 32a, a plurality of second large signal wirings 32b are arranged in parallel with each other with an insulating film 34b interposed therebetween.
The large signal wiring 32a and the second large signal wiring 32b are connected by a through hole 35 as necessary. This second large signal wiring 32b is similar to the first large signal wiring 32a in plan view.
The first large signal wiring 32a is formed substantially perpendicular to the first large signal wiring 32a.
and second large signal wiring 32b provide wiring between elements within the macrocell. A shielding electrode 36 covering substantially the entire surface of the substrate 33 is provided on the second large signal wiring 32b with an insulating film 34c interposed therebetween. The small signal wiring 31 is formed above the shield electrode 36 with an insulating film 34d interposed therebetween. A window 37 is opened in a predetermined area of the shielding electrode 36, and the output 31a of the small signal amplitude circuit formed on the surface of the substrate 33 is connected to a through hole 35a and an extremely short wiring 31b. It is connected to the small signal wiring 31 arranged in the upper layer via a through hole 35b selectively formed in the upper layer. In this way, the inter-macro wiring 31 is connected to the target macro cell. Further, inter-macro wiring is drawn out from the macro cell in the same manner.

In this embodiment, the upper layer small signal wiring 31
The capacitive coupling between the first large signal wiring 32a and the second large signal wiring 32b in the lower layer is almost completely blocked. Therefore, malfunction of the small signal amplitude circuit can be reliably avoided. Note that since the shield electrode 36 covers substantially the entire surface of the semiconductor substrate 33, a large capacitance is formed between the shield electrode 36 and the semiconductor substrate 33. Therefore, the shielding effect can be obtained without electrically fixing the shielding electrode 42 to a ground potential or the like. Therefore, in the manufacturing of this embodiment, additional steps for potential fixing in design and manufacturing are unnecessary. As a result, even in semiconductor integrated circuits that have a large number of interconnects between macros at the ECL signal level, there is no need to consider capacitive coupling with adjacent interconnects, and there is no need to consider capacitive coupling with large signal interconnects in the lower layer, making the design easier. It is simple and easy, and has a high degree of integration.

FIG. 4 is a sectional view showing a fourth embodiment of the present invention. This embodiment also has a structure in which inter-macro wiring passes through, and the following embodiments are also the same. A plurality of first large signal wirings 42a are arranged in parallel to each other on the semiconductor substrate 43 with an insulating film 44a interposed therebetween. This first large signal wiring 42a
A plurality of second large signal wirings 42b are arranged above in parallel with each other with an insulating film 44b interposed therebetween, and the first large signal wiring 42a and the second large signal wiring 42b can be passed through as necessary. It is connected through a hole 45. The second large signal wiring 42b is formed to be substantially orthogonal to the first large signal wiring 42a in plan view, and the first large signal wiring 42a and the second large signal wiring 42b connect elements within the macro cell. Wiring has been done between them. An insulating film 4 is formed on this second large signal wiring 42b.
4c is formed thickly. This insulating film 44c
A plurality of small signal wirings 41 are arranged on the small signal wirings 41, and an insulating film 44d is formed on the small signal wirings 41. This small signal wiring 41 is provided for inter-macro wiring.

In this embodiment, the large signal wiring 42a,
An insulating film 44c is interposed between the small signal wiring 42b and the small signal wiring 41, and since the insulation film 44c is thick, the coupling capacitance between the small signal wiring 41 and the large signal wiring 42a, 42b is small. This makes it possible to suppress malfunctions of the small signal amplitude circuit due to changes in the signals flowing through the large signal wirings 42a and 42b. This embodiment has the advantage that the above-mentioned effects can be obtained without increasing the number of integrated circuit manufacturing steps compared to the conventional method. As a result, even in semiconductor integrated circuits that have a large number of interconnects between macros at the ECL signal level, there is no need to consider capacitive coupling with adjacent interconnects, and there is no need to consider capacitive coupling with large signal interconnects in the lower layer, making the design easier. It is simple and easy, and has a high degree of integration.

FIG. 5 is a sectional view showing a fifth embodiment of the present invention. Silicon dioxide (SiO2
) A plurality of first large signal wirings 52a are arranged in parallel with each other with an insulating film 54a interposed therebetween. An insulating film 54 made of silicon dioxide is provided on the first large signal wiring 52a.
A plurality of second large signal wirings 52b are formed in parallel to each other via b, and the first large signal wiring 52a and the second large signal wiring 52b are connected by a through hole 55 as necessary. Ru. The second large signal wiring 52b is formed to be substantially orthogonal to the first large signal wiring 52a in plan view, and the first large signal wiring 52a and the second large signal wiring 52b connect elements within the macro cell. Wiring has been done between them. This second
An insulating film 54c made of polyimide is formed on the large signal wiring 52b. A plurality of small signal wires 51 are arranged on the insulating film 54c, and an insulating film 54d is formed on the small signal wires 51. This small signal wiring 51 is provided for inter-macro wiring.

In this embodiment, the insulating film 54c interposed between the small signal wiring 51 and the large signal wiring 52b is formed of a polyimide resin such as siloxane-modified polyimide. In general, the dielectric constant of an insulating film made of silicon dioxide provided between wiring layers is about 3.8 to 4, whereas the dielectric constant of siloxane-modified polyimide is as low as about 3 to 3.5. Therefore, in this embodiment, as in the fourth embodiment, the capacitive coupling between the upper layer small signal wiring 51 and the lower layers 52a and 52b is small, and malfunctions of the small signal amplitude circuit can be suppressed. As a result, E
Even in semiconductor integrated circuits that have a large number of interconnects between macros at the CL signal level, there is no need to consider capacitive coupling with adjacent interconnects, and there is no need to consider capacitive coupling with large signal interconnects in the lower layer, making the design simple and easy. It also has a high degree of integration.

FIG. 6 is a plan view showing a sixth embodiment of the present invention. Although not shown in FIG. 6 to avoid complication, in this embodiment, as in the first to fifth embodiments, the first large signal wiring in the first wiring layer and the large signal wiring in the second wiring layer The large signal wirings No. 2 are arranged approximately perpendicularly with each other with an insulating film interposed therebetween.
The first small signal wiring 61a and the third large signal wiring 62a shown in FIG. As a layer, a second small signal wiring 61b and a fourth
A large signal wiring 62b is arranged, and the small signal wiring consisting of the first small signal wiring 61a and the second small signal wiring 61b is arranged together, and the outermost wiring of this small signal wiring and the third Large signal wiring 62a and fourth large signal wiring 62b
The distance between the first small signal wiring 61a and the large signal wiring consisting of
and the second small signal wiring 61b. Through holes 65 are selectively provided at the intersections of the first small signal wiring 61a and the second small signal wiring 61b and the intersections of the third large signal wiring 62a and the fourth large signal wiring 62b as necessary. It is set in.

In this embodiment, the small signal wiring 61a,
61b is placed in the upper wiring layer, and some large signal wirings 62a and 62b are also placed in the upper wiring layer, but the large signal wiring 62a is separated from the small signal wirings 61a and 61b arranged together , 62b, the coupling capacitance between them can be reduced, and malfunctions of the small signal amplitude circuit can be prevented. Therefore, E.C.
In integrated circuit chips where the number of L-level inter-macro interconnects is not very large, small signal interconnects 6, which are inter-macro interconnects,
This embodiment is applied to the extra or unused wiring paths that occur when only 1a and 61b are arranged in the upper wiring layer, and large signal wirings 62a and 62a, which are inter-element wirings in a macro cell, are
By arranging 62b, the degree of integration can be further improved.

FIG. 7 is a plan view showing a seventh embodiment of the present invention. Although not shown in FIG. 7 to avoid complication, in this embodiment, as in the first to fifth embodiments, the first large signal wiring in the first wiring layer and the first large signal wiring in the second wiring layer The second large signal wirings are arranged substantially perpendicularly with each other through an insulating film, and the first small signal wiring shown in FIG. The wiring 71a, the power supply line 76a, and the third large signal wiring 72a are arranged in the third wiring layer substantially perpendicular to the second large signal wiring, and the small signal wiring is further placed in the uppermost fourth wiring layer via an insulating film. A second small signal wiring 71b, a power supply line 76b, and a fourth large signal wiring 72b are arranged in a direction orthogonal to the wiring 71a and the large signal wiring 72a, and the first small signal wiring 71a and the second small signal wiring The small signal wirings 71b are arranged together, and the outermost wiring of the small signal wirings, the third large signal wiring 72a, and the fourth large signal wiring 7
A power supply line made up of 76a and 76b is arranged between the large signal line made up of 2b. First small signal wiring 61a
Through holes 65 are selectively provided as necessary at the intersections of the and second small signal wirings 61b, and at the intersections of the third large signal wirings 62a and the fourth large signal wirings 62b. 76a and 76b are connected by a through hole 65.

In this embodiment as well, similar to the sixth embodiment shown in FIG. 6, small signal wirings 71a and 71b are arranged in the upper wiring layer, and some large signal wirings 72a and 72b are also arranged in the upper wiring layer. However, the potential is fixed between the small signal wirings 71a, 71b and the large signal wirings 72a, 72b arranged together, and the power supply line 76 acts as a shielding electrode.
a, 76b, small signal wiring 71a, 71b
Since the coupling capacitance between the large signal wirings 72a and 72b can be made extremely small, malfunctions of the small signal amplitude circuit can be more reliably prevented. Therefore, E.C.L.
In an integrated circuit chip in which the number of inter-level macro wirings is not so large, this embodiment can be applied to excess or unused wiring paths that occur when only the small signal wirings 71a and 71b are placed in the upper wiring layer. Applying large signal wiring 72a,
By arranging 72b, the degree of integration can be further improved.

FIG. 8(a) is a plan view showing the eighth embodiment of the present invention, and FIG. 8(b) is a plan view showing the eighth embodiment of the present invention.
FIG. An insulating film 8 is formed on the semiconductor substrate 83.
A plurality of first large signal wirings 82a are arranged in parallel with each other via 4a. A plurality of second large signal wirings 8 are disposed on the first large signal wiring 82a via an insulating film 84b.
2b are arranged parallel to each other. The second large signal wiring 82b is formed to be substantially perpendicular to the first large signal wiring 82a in plan view, and is connected to the first large signal wiring 82a and the second large signal wiring 82b.
The large signal wiring 82b provides wiring between elements within the macro cell. An insulating film 8 is formed on this second large signal wiring 82b.
4c, a plurality of first small signal wirings 81a, a first power supply wiring 86a that supplies a voltage of 5 volts, and a first ground wiring 87a that is a power supply wiring that supplies a voltage of 0 volts.
are arranged in parallel. This first small signal wiring 8
1a, first power supply wiring 86a and first ground wiring 87a
is formed substantially perpendicular to the second large signal wiring 82b in plan view. A voltage of 5 volts is supplied to a plurality of second small signal wirings 81b over the first small signal wiring 81a, the first power supply wiring 86a, and the first ground wiring 87a via an insulating film 84d. Only the second power supply wiring 86b and the second ground wiring 87b that supply a voltage of 0 volts are arranged in parallel. The second small signal wiring 81b, first power wiring 86b, and first ground wiring 87b are orthogonal to the first small signal wiring 81a, first power wiring 86a, and first ground wiring 87a in plan view. The insulating film 84 is formed on the upper surface.
e is formed. The first large signal wiring 82a and the second large signal wiring 82b are connected via a through hole penetrating the insulating film 84b as necessary (though not shown). The signal wiring 81a and the second small signal wiring 81b, the first power wiring 86a and the second power wiring 86b, and the first ground wiring 87a and the second ground wiring 87
b are connected via a through hole 85 penetrating the insulating film 84d as necessary.

In the present invention, the third wiring layer and the fourth wiring layer located in the upper layer are small signal wirings 81a and 81b, power supply wirings 86a and 86b that supply a voltage of 5 volts, and
Ground wiring 87a, which is a power wiring that supplies voltage of volts.
, 87b, and there are no large signal wirings that can cause noise in the third and fourth wiring layers, so it is not possible to design without considering the risk of malfunction due to coupling capacitance with adjacent wirings. , In addition, in integrated circuit chips where the number of ECL-level inter-macro interconnects is not very large, small signal interconnects 8
By applying this embodiment and installing power supply wirings 86a, 86b, 87a, and 87b in the surplus or unused wiring paths that occur when only 1a and 81b are placed in the upper wiring layer, the lower wiring layer It is possible to further increase the density by reducing the number of power supply wirings in the first wiring layer and the second wiring layer, and by providing a large number of power supply wirings in parallel, the resistance value of the power supply wiring can be reduced. Therefore, even with a large power supply current, it is possible to more stably fix the potential of the power supply wiring over the entire area on the integrated circuit chip.

FIG. 9(a) is a plan view showing a ninth embodiment of the present invention, FIG. 9(b) is a sectional view taken along the line IXb--IXb of FIG. 9(a), and FIG. 9(c) is a cross-sectional view of FIG. It is a sectional view taken along the line IXc-IXc.

A first wiring layer is formed with a first wiring pattern on the semiconductor substrate 93 via an insulating film 94a, and this first wiring layer has a plurality of large wires (two wires in the figure). A signal wiring 92a is provided. Further, a second wiring layer is formed with a second wiring pattern on this first wiring layer via an insulating film 94b, and a plurality of wires (two wires in the figure) are formed in this second wiring layer. A large signal wiring 92b is provided. This large signal wiring 92b is arranged so as to be orthogonal to the large signal wiring 92a in plan view. In addition, the large signal wiring 92
b is a through hole 9 selectively provided in the insulating film 94b.
It is electrically connected to the large signal wiring 92a via 5a.

On this second wiring layer, a third wiring layer is formed with a third wiring pattern via an insulating film 94c, and this third wiring layer has a plurality of wires (two wires in the figure). A small signal wiring 91a is provided. However, this small signal wiring 91a is arranged parallel to the large signal wiring 92b, avoiding the arrangement position of the large signal wiring 92b in plan view.

On this third wiring layer, a fourth wiring layer is formed with a fourth wiring pattern via an insulating film 94d, and this fourth wiring layer has a plurality of wires (two wires in the figure). A small signal wiring 91b is provided. This small signal wiring 91
b is a through hole 9 selectively provided in the insulating film 94d.
It is electrically connected to the large signal wiring 92a via 5b.

In this embodiment, the small signal wiring 91a of the third wiring layer and the large signal wiring 92a of the first wiring layer are two
Since only the wiring hierarchy is different, an extremely thick insulating film is interposed between the two. Therefore, the coupling capacitance between the small signal wiring 91a and the large signal wiring 92a is small. Similarly, since the small signal wiring 91b in the fourth wiring layer and the large signal wiring 92b in the second wiring layer differ by two wiring levels, an extremely thick insulating film is interposed between them. Therefore, the coupling capacity between the two is also small. As a result, the large signal wiring 9
Malfunctions of the small signal amplitude circuit due to changes in the signals flowing through 2a and 92b can be avoided.

[0036]

[Effects of the Invention] As explained above, according to the present invention, since small signal wirings are routed together as an upper wiring layer,
Noise can be generated in the small signal wiring due to changes in the signal flowing to the large signal wiring, without having to specially form dedicated shielding electrodes above, below, and on the sides of each individual small signal wiring as in the past. This can be prevented from occurring. Therefore, the semiconductor integrated circuit according to the present invention is easier to design than in the past.
Also, it can be highly integrated. In particular, in semiconductor integrated circuits in which the ECL level is used as the amplitude level of the signal flowing in the connection wiring between macro cells, the number of small signal wirings is large and the average wiring length is long. The effect of high integration is remarkable.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the invention.

FIG. 3 is a plan view and a sectional view showing a third embodiment of the present invention.

FIG. 4 is a sectional view showing a fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a fifth embodiment of the present invention.

FIG. 6 is a plan view showing a sixth embodiment of the present invention.

FIG. 7 is a plan view showing a seventh embodiment of the present invention.

FIG. 8 is a plan view and a sectional view showing an eighth embodiment of the present invention.

FIG. 9 is a plan view and a sectional view showing a ninth embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a conventional semiconductor integrated circuit.

FIG. 11 is a conceptual diagram of a semiconductor integrated circuit designed using hierarchical design.

FIG. 12 is a macro cell configuration diagram when the signal level of inter-macro wiring is set to ECL level.

Claims (10)

[Claims] 1. In a semiconductor integrated circuit comprising a large signal wiring through which a signal with a large amplitude flows and a small signal wiring through which a signal with a small amplitude flows, a plurality of the small signal wirings are arranged together, and the small signal wiring A semiconductor integrated circuit characterized in that wiring is arranged using an upper wiring layer in the semiconductor integrated circuit. 2. The semiconductor circuit according to claim 1, wherein the number of wiring layers is three or more, and a plurality of the small signal wirings are arranged together in the uppermost layer. 3. The semiconductor circuit according to claim 1, wherein the number of wiring layers is four or more, and a plurality of the small signal wirings are arranged in a top layer and a second wiring layer from the top. 4. A noise shielding electrode layer made of a noise shielding electrode is arranged between an upper wiring layer in which the small signal wiring is arranged and a lower wiring layer in which the large signal wiring is arranged. The semiconductor integrated circuit according to claim 1. 5. The thickness of the interlayer insulating film interposed between the upper wiring layer in which the small signal wiring is arranged and the lower wiring layer in which the large signal wiring is arranged is equal to the thickness of the interlayer insulating film interposed between the other wiring layers. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is made thicker than the interlayer insulating film. 6. The dielectric constant of the interlayer insulating film interposed between the upper wiring layer in which the small signal wiring is disposed and the lower wiring layer in which the large signal wiring is disposed is determined by adjusting the dielectric constant of the interlayer insulating film interposed between the other wiring layers. 2. The semiconductor integrated circuit according to claim 1, wherein the dielectric constant is lower than that of the interlayer insulating film. 7. A plurality of small signal wirings are arranged together in an upper layer, and the outermost small signal wirings are arranged together in a plan view, and the large signal wirings are arranged in the same layer. 2. The semiconductor integrated circuit according to claim 1, wherein an interval is set larger than an interval between the small signal wirings. 8. A plurality of small signal wirings are arranged together in an upper layer, and the outermost small signal wirings are arranged together in a plan view, and the large signal wirings are arranged in the same layer. 2. The semiconductor integrated circuit according to claim 1, further comprising a power supply line arranged between them. 9. The semiconductor integrated circuit according to claim 1, wherein the small signal wiring and the power supply line constitute an upper layer wiring. 10. The semiconductor integrated circuit according to claim 1, wherein the small signal wiring and the large signal wiring in portions that intersect with each other in a plan view are separated by at least two wiring levels.