JPH04355861A - Peripheral control processing device - Google Patents

Abstract

PURPOSE:To determine the priority of data transmission by the data transfer time for the purpose of preventing the transmission request from a peripheral device having a low priority level from being left unaccepted for a long time. CONSTITUTION:This device is characterized by providing a data transfer speed storage part 7 where the data transfer speed set for each peripheral device is stored, a data transfer volume storage part 8 where the data volume of data transfer to a host computer from each peripheral device is stored, a calculating circuit part 9 which calculates the data transfer time of each peripheral device based on values stored in the data transfer volume storage part 8 and the data transfer speed storage part 7, a comparing circuit 10 which compares calculation results of calculating circuits 9 with one another, and a data transfer request selecting part 11 which selects one of data transmission requests of plural peripheral devices by the output of the comparing circuit 10 and requests data transfer to the host computer.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peripheral control processing device, and more particularly to a transmission request control device for sending data from a peripheral device to a host computer. The peripheral control device is connected to an upper host computer through a channel interface, and has a plurality of device interfaces to which various peripheral devices are connected to the lower layer.

0002

2. Description of the Related Art A conventional peripheral control processing device includes a data buffer that temporarily stores data transferred between a host computer and a peripheral device, and a data buffer that detects data transmission requests from a plurality of peripheral devices to the host computer. a transmission request detection means; a priority circuit that selects transmission requests from a plurality of peripheral devices detected by the transmission request detection means based on numbers assigned to the device interface; and a host for transmission requests selected by the priority circuit. It has a means to notify the computer.

When data to be transmitted to a host computer is generated from a plurality of peripheral devices, each peripheral device reports a transmission request to the peripheral control processing device. The peripheral control processing device determines the priority of each transmission request, and sends transmission requests to the host computer in order of priority.

0004

[Problems to be Solved by the Invention] When the conventional peripheral control processing device described above receives transmission requests from multiple peripheral devices, it determines the priority and sends the transmission requests to the host computer in order of priority. Therefore, if data transfer is performed continuously in response to a transmission request from a high-priority peripheral device, a situation continues where no transmission request from a low-priority peripheral device is received. There is a problem in that data transfer is not performed for a long time in response to a transmission request from a peripheral device with a low priority.

[0005]

[Means for Solving the Problems] The device of the present invention has a plurality of device interfaces connected to an upper host computer through a channel interface and connected to lower peripheral devices, and has a plurality of device interfaces connected to a lower level peripheral device. A peripheral control processing device that controls data transfer includes a data buffer that temporarily stores data transferred between the host computer and a plurality of peripheral devices, and a data transfer that stores data transfer speeds set for each of the peripheral devices. a speed storage unit; a data transfer amount storage unit that stores the amount of data transferred to the host computer for each peripheral device;
an arithmetic circuit unit that calculates a data transfer time for each peripheral device based on a value stored in the data transfer amount storage unit and a value stored in the data transfer rate storage unit; and an arithmetic circuit unit that calculates a data transfer time for each peripheral device; It has a comparison circuit that compares the magnitude of the results, and a data transfer request selection section that selects one of the data transmission requests of a plurality of peripheral devices based on the output signal of the comparison circuit and issues a data transfer request to the host computer. It is characterized by

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The peripheral control processing device 2 of the present invention is connected to the host computer 1 through an upper channel interface 4, and is connected to a plurality of lower device interfaces 5.
It is connected to the peripheral device 3 by.

The peripheral control processing device 2 includes a data buffer 6 for temporarily storing data transferred between the host computer 1 and a plurality of peripheral devices 3, and a data buffer 6 for temporarily storing data transferred between the host computer 1 and a plurality of peripheral devices 3, and a data buffer 6 for transferring data to the host computer 1 for each of the plurality of peripheral devices 3. The data transfer rate storage unit 8 stores the amount of data to be transferred, the data transfer rate storage unit 7 stores the data transfer rate set for each of the plurality of peripheral devices 3, and the data transfer rate storage unit 7 stores the data transfer rate set for each of the plurality of peripheral devices 3. an arithmetic circuit unit 9 that calculates the data transfer time for each peripheral device 3 based on the value and the value stored in the data transfer amount storage unit 8; and a comparison circuit 10 that compares the calculation results of the arithmetic circuit unit 9 in magnitude. and a data transfer request selection section 11 that selects one of the data transmission requests from a plurality of peripheral devices 3 based on the output signal of the comparison circuit 10 and issues a data transfer request to the host computer 1.

Next, the operation of the peripheral control processing device 2 of the present invention will be explained using a specific example. It is assumed that data transfer between the host computer 1 and the peripheral device 3 is normally performed as follows.

1) From the host computer 1 to the peripheral device 3
When transferring data to the peripheral device 3, the host computer 1 issues a channel program to the peripheral control processing device 2 of the present invention, temporarily stores the data in the data buffer 6, and then transfers the data to the peripheral device 3.

2) From peripheral device 3 to host computer 1
When transferring data to, the peripheral device 3 notifies the peripheral control processing unit 2 of a data transmission request and the amount of data to be transferred via the device interface 5.

Next, the data transfer request selection section 11 issues a data transmission request to the host computer 1, and the data is transferred from the peripheral device 3 to the host computer 1 via the data buffer 6.

A case in which data is transferred from a plurality of peripheral devices 3 to the host computer 1 will be explained in detail.

It is assumed that the data transfer rate of the peripheral device 3 connected to the device interface 5 is stored in the data transfer rate storage section 7 in advance. Each peripheral device 3 notifies the peripheral control processing device 2 of a data transmission request and data transfer amount via the device interface 5. The notified data transfer amount is stored in the data transfer amount storage section 8.

Next, based on the value stored in the data transfer rate storage section 7 and the value stored in the data transfer amount storage section 8, the arithmetic circuit section 9 transfers data from the peripheral device 3 to the host computer 1. Calculate time. The comparison circuit 10 compares the calculation results of the calculation circuit section 9 in magnitude, and the data transfer request selection section 11 selects the data transmission request of the peripheral device 3 with the smallest value among the results of the comparison circuit 10 and sends the data to the host computer 1. After making a transfer request, the data is transferred from the peripheral device 3 to the host computer 1 via the data buffer 6.

[0017]

As explained above, the present invention calculates the data transfer time from the data transfer amount and the data transfer speed of the peripheral devices when transferring data from a plurality of peripheral devices to a host computer, and calculates the data transfer time. Since data transmission requests from multiple peripheral devices are selected and sent to the host computer, data transfers from peripheral devices with low priority are no longer delayed due to data transfers from peripheral devices with high priority. The problem of being in a waiting state can be eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

1 Host computer 2 Peripheral control processing device 3 Peripheral devices 4 Channel interface 5 Device interface 6 Data buffer 7 Data transfer rate storage section 8 Data transfer amount storage section 9 Arithmetic circuit section 10 Comparison circuit 11 Data transfer request selection section

Claims (1)

[Claims] 1. A peripheral control processing device that is connected to an upper host computer through a channel interface, has a plurality of device interfaces that are connected to lower peripheral devices, and controls data transfer between the host computer and the peripheral devices. , a data buffer for temporarily storing data transferred between the host computer and a plurality of peripheral devices; a data transfer rate storage section for storing a data transfer rate set for each peripheral device; A data transfer amount storage unit that stores the amount of data transferred to the computer; and a data transfer rate storage unit for each peripheral device based on the value stored in the data transfer amount storage unit and the value stored in the data transfer rate storage unit an arithmetic circuit unit that calculates the data transfer time; a comparator circuit that compares the calculation results of each arithmetic circuit; and a comparator circuit that compares the computation results of each arithmetic circuit, and selects one of the data transmission requests from multiple peripheral devices based on the output signal of the comparator circuit and sends it to the host. A peripheral control processing device comprising: a data transfer request selection unit that requests a data transfer to a computer.